Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
b413d7a0 | 14 | #include <linux/acpi.h> |
644f3da0 | 15 | #include <linux/gpio/driver.h> |
054ccdef | 16 | #include <linux/gpio/consumer.h> |
9e60fdcf | 17 | #include <linux/i2c.h> |
b413d7a0 AS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_platform.h> | |
5877457a | 22 | #include <linux/platform_data/pca953x.h> |
49427232 | 23 | #include <linux/regmap.h> |
b413d7a0 | 24 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
b413d7a0 | 26 | |
9b8e3ec3 | 27 | #include <asm/unaligned.h> |
9e60fdcf | 28 | |
0950c19a NS |
29 | #define PCA953X_INPUT 0x00 |
30 | #define PCA953X_OUTPUT 0x01 | |
31 | #define PCA953X_INVERT 0x02 | |
32 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 33 | |
49427232 MV |
34 | #define REG_ADDR_MASK 0x3f |
35 | #define REG_ADDR_EXT 0x40 | |
ae79c190 AS |
36 | #define REG_ADDR_AI 0x80 |
37 | ||
0950c19a NS |
38 | #define PCA957X_IN 0x00 |
39 | #define PCA957X_INVRT 0x01 | |
40 | #define PCA957X_BKEN 0x02 | |
41 | #define PCA957X_PUPD 0x03 | |
42 | #define PCA957X_CFG 0x04 | |
43 | #define PCA957X_OUT 0x05 | |
44 | #define PCA957X_MSK 0x06 | |
45 | #define PCA957X_INTS 0x07 | |
33226ffd | 46 | |
6315d231 | 47 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 48 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
49 | #define PCAL953X_PULL_EN 0x23 |
50 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
51 | #define PCAL953X_INT_MASK 0x25 |
52 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 53 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 54 | |
a0ecbccc NS |
55 | #define PCAL6524_INT_EDGE 0x28 |
56 | #define PCAL6524_INT_CLR 0x2a | |
57 | #define PCAL6524_IN_STATUS 0x2b | |
58 | #define PCAL6524_OUT_INDCONF 0x2c | |
59 | #define PCAL6524_DEBOUNCE 0x2d | |
60 | ||
33226ffd | 61 | #define PCA_GPIO_MASK 0x00FF |
394aeef8 NS |
62 | |
63 | #define PCAL_GPIO_MASK 0x1f | |
92f45ebe | 64 | #define PCAL_PINCTRL_MASK 0x60 |
394aeef8 | 65 | |
33226ffd | 66 | #define PCA_INT 0x0100 |
8c7a92da | 67 | #define PCA_PCAL 0x0200 |
0cdf21b3 | 68 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
33226ffd HZ |
69 | #define PCA953X_TYPE 0x1000 |
70 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
71 | #define PCA_TYPE_MASK 0xF000 |
72 | ||
73 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 74 | |
3760f736 | 75 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 76 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
77 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
78 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "pca9536", 4 | PCA953X_TYPE, }, | |
80 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
83 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
84 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
85 | { "pca9556", 8 | PCA953X_TYPE, }, | |
86 | { "pca9557", 8 | PCA953X_TYPE, }, | |
87 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
88 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 89 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 90 | |
3a711e0d | 91 | { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
747e42a1 AS |
92 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
93 | ||
33226ffd HZ |
94 | { "max7310", 8 | PCA953X_TYPE, }, |
95 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
96 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
97 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 98 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
99 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
100 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
101 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 102 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 103 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 104 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 105 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 106 | { } |
f5e8ff48 | 107 | }; |
3760f736 | 108 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 109 | |
f32517bf | 110 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 111 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
112 | { } |
113 | }; | |
114 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
115 | ||
f5f0b7aa GC |
116 | #define MAX_BANK 5 |
117 | #define BANK_SZ 8 | |
118 | ||
a246b819 | 119 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 120 | |
53661f3b BG |
121 | struct pca953x_reg_config { |
122 | int direction; | |
123 | int output; | |
124 | int input; | |
7a04aaa3 | 125 | int invert; |
53661f3b BG |
126 | }; |
127 | ||
128 | static const struct pca953x_reg_config pca953x_regs = { | |
129 | .direction = PCA953X_DIRECTION, | |
130 | .output = PCA953X_OUTPUT, | |
131 | .input = PCA953X_INPUT, | |
7a04aaa3 | 132 | .invert = PCA953X_INVERT, |
53661f3b BG |
133 | }; |
134 | ||
135 | static const struct pca953x_reg_config pca957x_regs = { | |
136 | .direction = PCA957X_CFG, | |
137 | .output = PCA957X_OUT, | |
138 | .input = PCA957X_IN, | |
7a04aaa3 | 139 | .invert = PCA957X_INVRT, |
53661f3b BG |
140 | }; |
141 | ||
f3dc3630 | 142 | struct pca953x_chip { |
9e60fdcf | 143 | unsigned gpio_start; |
6e20fb18 | 144 | struct mutex i2c_lock; |
49427232 | 145 | struct regmap *regmap; |
9e60fdcf | 146 | |
89ea8bbe MZ |
147 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
148 | struct mutex irq_lock; | |
f5f0b7aa GC |
149 | u8 irq_mask[MAX_BANK]; |
150 | u8 irq_stat[MAX_BANK]; | |
151 | u8 irq_trig_raise[MAX_BANK]; | |
152 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
153 | #endif |
154 | ||
9e60fdcf | 155 | struct i2c_client *client; |
156 | struct gpio_chip gpio_chip; | |
62154991 | 157 | const char *const *names; |
c6664149 | 158 | unsigned long driver_data; |
e23efa31 | 159 | struct regulator *regulator; |
53661f3b BG |
160 | |
161 | const struct pca953x_reg_config *regs; | |
9e60fdcf | 162 | }; |
163 | ||
873d1e8e MV |
164 | static int pca953x_bank_shift(struct pca953x_chip *chip) |
165 | { | |
166 | return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
167 | } | |
168 | ||
49427232 MV |
169 | #define PCA953x_BANK_INPUT BIT(0) |
170 | #define PCA953x_BANK_OUTPUT BIT(1) | |
171 | #define PCA953x_BANK_POLARITY BIT(2) | |
172 | #define PCA953x_BANK_CONFIG BIT(3) | |
173 | ||
174 | #define PCA957x_BANK_INPUT BIT(0) | |
175 | #define PCA957x_BANK_POLARITY BIT(1) | |
176 | #define PCA957x_BANK_BUSHOLD BIT(2) | |
177 | #define PCA957x_BANK_CONFIG BIT(4) | |
178 | #define PCA957x_BANK_OUTPUT BIT(5) | |
179 | ||
180 | #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) | |
181 | #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) | |
182 | #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) | |
183 | ||
184 | /* | |
185 | * We care about the following registers: | |
186 | * - Standard set, below 0x40, each port can be replicated up to 8 times | |
187 | * - PCA953x standard | |
188 | * Input port 0x00 + 0 * bank_size R | |
189 | * Output port 0x00 + 1 * bank_size RW | |
190 | * Polarity Inversion port 0x00 + 2 * bank_size RW | |
191 | * Configuration port 0x00 + 3 * bank_size RW | |
192 | * - PCA957x with mixed up registers | |
193 | * Input port 0x00 + 0 * bank_size R | |
194 | * Polarity Inversion port 0x00 + 1 * bank_size RW | |
195 | * Bus hold port 0x00 + 2 * bank_size RW | |
196 | * Configuration port 0x00 + 4 * bank_size RW | |
197 | * Output port 0x00 + 5 * bank_size RW | |
198 | * | |
199 | * - Extended set, above 0x40, often chip specific. | |
200 | * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: | |
201 | * Input latch register 0x40 + 2 * bank_size RW | |
202 | * Interrupt mask register 0x40 + 5 * bank_size RW | |
203 | * Interrupt status register 0x40 + 6 * bank_size R | |
204 | * | |
205 | * - Registers with bit 0x80 set, the AI bit | |
206 | * The bit is cleared and the registers fall into one of the | |
207 | * categories above. | |
208 | */ | |
209 | ||
210 | static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, | |
211 | u32 checkbank) | |
212 | { | |
213 | int bank_shift = pca953x_bank_shift(chip); | |
214 | int bank = (reg & REG_ADDR_MASK) >> bank_shift; | |
215 | int offset = reg & (BIT(bank_shift) - 1); | |
216 | ||
217 | /* Special PCAL extended register check. */ | |
218 | if (reg & REG_ADDR_EXT) { | |
219 | if (!(chip->driver_data & PCA_PCAL)) | |
220 | return false; | |
221 | bank += 8; | |
222 | } | |
223 | ||
224 | /* Register is not in the matching bank. */ | |
225 | if (!(BIT(bank) & checkbank)) | |
226 | return false; | |
227 | ||
228 | /* Register is not within allowed range of bank. */ | |
229 | if (offset >= NBANK(chip)) | |
230 | return false; | |
231 | ||
232 | return true; | |
233 | } | |
234 | ||
235 | static bool pca953x_readable_register(struct device *dev, unsigned int reg) | |
236 | { | |
237 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
238 | u32 bank; | |
239 | ||
240 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { | |
241 | bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | | |
242 | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; | |
243 | } else { | |
244 | bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | | |
245 | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | | |
246 | PCA957x_BANK_BUSHOLD; | |
247 | } | |
248 | ||
249 | if (chip->driver_data & PCA_PCAL) { | |
250 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_IRQ_MASK | | |
251 | PCAL9xxx_BANK_IRQ_STAT; | |
252 | } | |
253 | ||
254 | return pca953x_check_register(chip, reg, bank); | |
255 | } | |
256 | ||
257 | static bool pca953x_writeable_register(struct device *dev, unsigned int reg) | |
258 | { | |
259 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
260 | u32 bank; | |
261 | ||
262 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { | |
263 | bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | | |
264 | PCA953x_BANK_CONFIG; | |
265 | } else { | |
266 | bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | | |
267 | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; | |
268 | } | |
269 | ||
270 | if (chip->driver_data & PCA_PCAL) | |
271 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_IRQ_MASK; | |
272 | ||
273 | return pca953x_check_register(chip, reg, bank); | |
274 | } | |
275 | ||
276 | static bool pca953x_volatile_register(struct device *dev, unsigned int reg) | |
277 | { | |
278 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
279 | u32 bank; | |
280 | ||
281 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) | |
282 | bank = PCA953x_BANK_INPUT; | |
283 | else | |
284 | bank = PCA957x_BANK_INPUT; | |
285 | ||
286 | if (chip->driver_data & PCA_PCAL) | |
287 | bank |= PCAL9xxx_BANK_IRQ_STAT; | |
288 | ||
289 | return pca953x_check_register(chip, reg, bank); | |
290 | } | |
291 | ||
292 | const struct regmap_config pca953x_i2c_regmap = { | |
293 | .reg_bits = 8, | |
294 | .val_bits = 8, | |
295 | ||
296 | .readable_reg = pca953x_readable_register, | |
297 | .writeable_reg = pca953x_writeable_register, | |
298 | .volatile_reg = pca953x_volatile_register, | |
299 | ||
300 | .cache_type = REGCACHE_RBTREE, | |
301 | .max_register = 0x7f, | |
302 | }; | |
303 | ||
b32cecb4 MV |
304 | static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, |
305 | bool write, bool addrinc) | |
306 | { | |
307 | int bank_shift = pca953x_bank_shift(chip); | |
308 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; | |
309 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
310 | u8 regaddr = pinctrl | addr | (off / BANK_SZ); | |
311 | ||
312 | /* Single byte read doesn't need AI bit set. */ | |
313 | if (!addrinc) | |
314 | return regaddr; | |
315 | ||
316 | /* Chips with 24 and more GPIOs always support Auto Increment */ | |
317 | if (write && NBANK(chip) > 2) | |
318 | regaddr |= REG_ADDR_AI; | |
319 | ||
320 | /* PCA9575 needs address-increment on multi-byte writes */ | |
321 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) | |
322 | regaddr |= REG_ADDR_AI; | |
323 | ||
324 | return regaddr; | |
325 | } | |
326 | ||
f5f0b7aa GC |
327 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
328 | int off) | |
329 | { | |
b32cecb4 | 330 | u8 regaddr = pca953x_recalc_addr(chip, reg, off, false, false); |
f5f0b7aa | 331 | int ret; |
f5f0b7aa | 332 | |
49427232 | 333 | ret = regmap_read(chip->regmap, regaddr, val); |
f5f0b7aa GC |
334 | if (ret < 0) { |
335 | dev_err(&chip->client->dev, "failed reading register\n"); | |
336 | return ret; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
90adb097 | 342 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) |
7acc66e3 | 343 | { |
b32cecb4 | 344 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); |
90adb097 | 345 | int ret; |
49e71373 | 346 | |
49427232 | 347 | ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); |
f5e8ff48 GL |
348 | if (ret < 0) { |
349 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 350 | return ret; |
f5e8ff48 GL |
351 | } |
352 | ||
353 | return 0; | |
9e60fdcf | 354 | } |
355 | ||
90adb097 | 356 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
c6e3cf01 | 357 | { |
b32cecb4 | 358 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); |
90adb097 | 359 | int ret; |
49e71373 | 360 | |
49427232 | 361 | ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); |
9e60fdcf | 362 | if (ret < 0) { |
363 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 364 | return ret; |
9e60fdcf | 365 | } |
366 | ||
9e60fdcf | 367 | return 0; |
368 | } | |
369 | ||
f3dc3630 | 370 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 371 | { |
468e67f6 | 372 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
373 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
374 | true, false); | |
375 | u8 bit = BIT(off % BANK_SZ); | |
53661f3b | 376 | int ret; |
9e60fdcf | 377 | |
6e20fb18 | 378 | mutex_lock(&chip->i2c_lock); |
0f25fda8 | 379 | ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); |
6e20fb18 RS |
380 | mutex_unlock(&chip->i2c_lock); |
381 | return ret; | |
9e60fdcf | 382 | } |
383 | ||
f3dc3630 | 384 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 385 | unsigned off, int val) |
386 | { | |
468e67f6 | 387 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
388 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
389 | true, false); | |
ec82d1eb MV |
390 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
391 | true, false); | |
0f25fda8 | 392 | u8 bit = BIT(off % BANK_SZ); |
53661f3b | 393 | int ret; |
9e60fdcf | 394 | |
6e20fb18 | 395 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 396 | /* set output level */ |
ec82d1eb | 397 | ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
9e60fdcf | 398 | if (ret) |
6e20fb18 | 399 | goto exit; |
9e60fdcf | 400 | |
9e60fdcf | 401 | /* then direction */ |
0f25fda8 | 402 | ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); |
6e20fb18 RS |
403 | exit: |
404 | mutex_unlock(&chip->i2c_lock); | |
405 | return ret; | |
9e60fdcf | 406 | } |
407 | ||
f3dc3630 | 408 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 409 | { |
468e67f6 | 410 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 411 | u32 reg_val; |
53661f3b | 412 | int ret; |
9e60fdcf | 413 | |
6e20fb18 | 414 | mutex_lock(&chip->i2c_lock); |
53661f3b | 415 | ret = pca953x_read_single(chip, chip->regs->input, ®_val, off); |
6e20fb18 | 416 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 417 | if (ret < 0) { |
418 | /* NOTE: diagnostic already emitted; that's all we should | |
419 | * do unless gpio_*_value_cansleep() calls become different | |
420 | * from their nonsleeping siblings (and report faults). | |
421 | */ | |
422 | return 0; | |
423 | } | |
424 | ||
40a625da | 425 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 426 | } |
427 | ||
f3dc3630 | 428 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 429 | { |
468e67f6 | 430 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ec82d1eb MV |
431 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
432 | true, false); | |
433 | u8 bit = BIT(off % BANK_SZ); | |
9e60fdcf | 434 | |
6e20fb18 | 435 | mutex_lock(&chip->i2c_lock); |
ec82d1eb | 436 | regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
6e20fb18 | 437 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 438 | } |
439 | ||
66e57192 AS |
440 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
441 | { | |
442 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
0f25fda8 MV |
443 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
444 | true, false); | |
445 | u8 bit = BIT(off % BANK_SZ); | |
66e57192 AS |
446 | u32 reg_val; |
447 | int ret; | |
448 | ||
449 | mutex_lock(&chip->i2c_lock); | |
0f25fda8 | 450 | ret = regmap_read(chip->regmap, dirreg, ®_val); |
66e57192 AS |
451 | mutex_unlock(&chip->i2c_lock); |
452 | if (ret < 0) | |
453 | return ret; | |
454 | ||
0f25fda8 | 455 | return !!(reg_val & bit); |
66e57192 AS |
456 | } |
457 | ||
b4818afe | 458 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 459 | unsigned long *mask, unsigned long *bits) |
b4818afe | 460 | { |
468e67f6 | 461 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d | 462 | unsigned int bank_mask, bank_val; |
873d1e8e | 463 | int bank; |
b4818afe | 464 | u8 reg_val[MAX_BANK]; |
53661f3b | 465 | int ret; |
ea3d579d | 466 | |
b4818afe | 467 | mutex_lock(&chip->i2c_lock); |
ec82d1eb MV |
468 | ret = pca953x_read_regs(chip, chip->regs->output, reg_val); |
469 | if (ret) | |
470 | goto exit; | |
471 | ||
ea3d579d BG |
472 | for (bank = 0; bank < NBANK(chip); bank++) { |
473 | bank_mask = mask[bank / sizeof(*mask)] >> | |
474 | ((bank % sizeof(*mask)) * 8); | |
475 | if (bank_mask) { | |
476 | bank_val = bits[bank / sizeof(*bits)] >> | |
477 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 478 | bank_val &= bank_mask; |
ea3d579d | 479 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
480 | } |
481 | } | |
ea3d579d | 482 | |
ec82d1eb | 483 | pca953x_write_regs(chip, chip->regs->output, reg_val); |
b4818afe PR |
484 | exit: |
485 | mutex_unlock(&chip->i2c_lock); | |
486 | } | |
487 | ||
f5e8ff48 | 488 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 489 | { |
490 | struct gpio_chip *gc; | |
491 | ||
492 | gc = &chip->gpio_chip; | |
493 | ||
f3dc3630 GL |
494 | gc->direction_input = pca953x_gpio_direction_input; |
495 | gc->direction_output = pca953x_gpio_direction_output; | |
496 | gc->get = pca953x_gpio_get_value; | |
497 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 498 | gc->get_direction = pca953x_gpio_get_direction; |
b4818afe | 499 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 500 | gc->can_sleep = true; |
9e60fdcf | 501 | |
502 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
503 | gc->ngpio = gpios; |
504 | gc->label = chip->client->name; | |
58383c78 | 505 | gc->parent = &chip->client->dev; |
d72cbed0 | 506 | gc->owner = THIS_MODULE; |
77906a54 | 507 | gc->names = chip->names; |
9e60fdcf | 508 | } |
509 | ||
89ea8bbe | 510 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 511 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 512 | { |
7bcbce55 | 513 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 514 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 515 | |
f5f0b7aa | 516 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
517 | } |
518 | ||
6f5cfc0e | 519 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 520 | { |
7bcbce55 | 521 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 522 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 523 | |
f5f0b7aa | 524 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
525 | } |
526 | ||
6f5cfc0e | 527 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 528 | { |
7bcbce55 | 529 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 530 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
531 | |
532 | mutex_lock(&chip->irq_lock); | |
533 | } | |
534 | ||
6f5cfc0e | 535 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 536 | { |
7bcbce55 | 537 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 538 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
539 | u8 new_irqs; |
540 | int level, i; | |
44896bea | 541 | u8 invert_irq_mask[MAX_BANK]; |
0f25fda8 MV |
542 | int reg_direction[MAX_BANK]; |
543 | ||
544 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, | |
545 | NBANK(chip)); | |
44896bea YL |
546 | |
547 | if (chip->driver_data & PCA_PCAL) { | |
548 | /* Enable latch on interrupt-enabled inputs */ | |
549 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
550 | ||
551 | for (i = 0; i < NBANK(chip); i++) | |
552 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
553 | ||
554 | /* Unmask enabled interrupts */ | |
555 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
556 | } | |
a2cb9aeb MZ |
557 | |
558 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
559 | for (i = 0; i < NBANK(chip); i++) { |
560 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
0f25fda8 | 561 | new_irqs &= reg_direction[i]; |
f5f0b7aa GC |
562 | |
563 | while (new_irqs) { | |
564 | level = __ffs(new_irqs); | |
565 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
566 | level + (BANK_SZ * i)); | |
567 | new_irqs &= ~(1 << level); | |
568 | } | |
a2cb9aeb | 569 | } |
89ea8bbe MZ |
570 | |
571 | mutex_unlock(&chip->irq_lock); | |
572 | } | |
573 | ||
6f5cfc0e | 574 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 575 | { |
7bcbce55 | 576 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 577 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
578 | int bank_nb = d->hwirq / BANK_SZ; |
579 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
580 | |
581 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
582 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 583 | d->irq, type); |
89ea8bbe MZ |
584 | return -EINVAL; |
585 | } | |
586 | ||
587 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 588 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 589 | else |
f5f0b7aa | 590 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
591 | |
592 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 593 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 594 | else |
f5f0b7aa | 595 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 596 | |
a2cb9aeb | 597 | return 0; |
89ea8bbe MZ |
598 | } |
599 | ||
0a70fe00 GD |
600 | static void pca953x_irq_shutdown(struct irq_data *d) |
601 | { | |
602 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); | |
603 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
604 | ||
605 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | |
606 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | |
607 | } | |
608 | ||
89ea8bbe MZ |
609 | static struct irq_chip pca953x_irq_chip = { |
610 | .name = "pca953x", | |
6f5cfc0e LB |
611 | .irq_mask = pca953x_irq_mask, |
612 | .irq_unmask = pca953x_irq_unmask, | |
613 | .irq_bus_lock = pca953x_irq_bus_lock, | |
614 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
615 | .irq_set_type = pca953x_irq_set_type, | |
0a70fe00 | 616 | .irq_shutdown = pca953x_irq_shutdown, |
89ea8bbe MZ |
617 | }; |
618 | ||
b6ac1280 | 619 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 620 | { |
f5f0b7aa GC |
621 | u8 cur_stat[MAX_BANK]; |
622 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
623 | bool pending_seen = false; |
624 | bool trigger_seen = false; | |
625 | u8 trigger[MAX_BANK]; | |
0f25fda8 | 626 | int reg_direction[MAX_BANK]; |
53661f3b | 627 | int ret, i; |
33226ffd | 628 | |
44896bea YL |
629 | if (chip->driver_data & PCA_PCAL) { |
630 | /* Read the current interrupt status from the device */ | |
631 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
632 | if (ret) | |
633 | return false; | |
634 | ||
635 | /* Check latched inputs and clear interrupt status */ | |
636 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
637 | if (ret) | |
638 | return false; | |
639 | ||
640 | for (i = 0; i < NBANK(chip); i++) { | |
641 | /* Apply filter for rising/falling edge selection */ | |
642 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
643 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
644 | pending[i] &= trigger[i]; | |
645 | if (pending[i]) | |
646 | pending_seen = true; | |
647 | } | |
648 | ||
649 | return pending_seen; | |
650 | } | |
651 | ||
53661f3b | 652 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 653 | if (ret) |
b6ac1280 | 654 | return false; |
89ea8bbe MZ |
655 | |
656 | /* Remove output pins from the equation */ | |
0f25fda8 MV |
657 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, |
658 | NBANK(chip)); | |
f5f0b7aa | 659 | for (i = 0; i < NBANK(chip); i++) |
0f25fda8 | 660 | cur_stat[i] &= reg_direction[i]; |
89ea8bbe | 661 | |
f5f0b7aa | 662 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 663 | |
f5f0b7aa GC |
664 | for (i = 0; i < NBANK(chip); i++) { |
665 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
666 | if (trigger[i]) |
667 | trigger_seen = true; | |
f5f0b7aa GC |
668 | } |
669 | ||
b6ac1280 JS |
670 | if (!trigger_seen) |
671 | return false; | |
89ea8bbe | 672 | |
f5f0b7aa | 673 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 674 | |
f5f0b7aa GC |
675 | for (i = 0; i < NBANK(chip); i++) { |
676 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
677 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
678 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
679 | if (pending[i]) |
680 | pending_seen = true; | |
f5f0b7aa | 681 | } |
89ea8bbe | 682 | |
b6ac1280 | 683 | return pending_seen; |
89ea8bbe MZ |
684 | } |
685 | ||
686 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
687 | { | |
688 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
689 | u8 pending[MAX_BANK]; |
690 | u8 level; | |
3275d072 | 691 | unsigned nhandled = 0; |
f5f0b7aa | 692 | int i; |
89ea8bbe | 693 | |
f5f0b7aa | 694 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 695 | return IRQ_NONE; |
89ea8bbe | 696 | |
f5f0b7aa GC |
697 | for (i = 0; i < NBANK(chip); i++) { |
698 | while (pending[i]) { | |
699 | level = __ffs(pending[i]); | |
f0fbe7bc | 700 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
f5f0b7aa GC |
701 | level + (BANK_SZ * i))); |
702 | pending[i] &= ~(1 << level); | |
3275d072 | 703 | nhandled++; |
f5f0b7aa GC |
704 | } |
705 | } | |
89ea8bbe | 706 | |
3275d072 | 707 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
708 | } |
709 | ||
710 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 711 | int irq_base) |
89ea8bbe MZ |
712 | { |
713 | struct i2c_client *client = chip->client; | |
0f25fda8 | 714 | int reg_direction[MAX_BANK]; |
53661f3b | 715 | int ret, i; |
89ea8bbe | 716 | |
4bb93349 | 717 | if (client->irq && irq_base != -1 |
c6664149 | 718 | && (chip->driver_data & PCA_INT)) { |
53661f3b BG |
719 | ret = pca953x_read_regs(chip, |
720 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 721 | if (ret) |
b42748c9 | 722 | return ret; |
89ea8bbe MZ |
723 | |
724 | /* | |
725 | * There is no way to know which GPIO line generated the | |
726 | * interrupt. We have to rely on the previous read for | |
727 | * this purpose. | |
728 | */ | |
0f25fda8 MV |
729 | regmap_bulk_read(chip->regmap, chip->regs->direction, |
730 | reg_direction, NBANK(chip)); | |
f5f0b7aa | 731 | for (i = 0; i < NBANK(chip); i++) |
0f25fda8 | 732 | chip->irq_stat[i] &= reg_direction[i]; |
89ea8bbe MZ |
733 | mutex_init(&chip->irq_lock); |
734 | ||
b42748c9 LW |
735 | ret = devm_request_threaded_irq(&client->dev, |
736 | client->irq, | |
89ea8bbe MZ |
737 | NULL, |
738 | pca953x_irq_handler, | |
91329132 TS |
739 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
740 | IRQF_SHARED, | |
89ea8bbe MZ |
741 | dev_name(&client->dev), chip); |
742 | if (ret) { | |
743 | dev_err(&client->dev, "failed to request irq %d\n", | |
744 | client->irq); | |
0e8f2fda | 745 | return ret; |
89ea8bbe MZ |
746 | } |
747 | ||
d245b3f9 LW |
748 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, |
749 | &pca953x_irq_chip, | |
750 | irq_base, | |
751 | handle_simple_irq, | |
752 | IRQ_TYPE_NONE); | |
7bcbce55 LW |
753 | if (ret) { |
754 | dev_err(&client->dev, | |
755 | "could not connect irqchip to gpiochip\n"); | |
756 | return ret; | |
757 | } | |
fdd50409 | 758 | |
d245b3f9 LW |
759 | gpiochip_set_nested_irqchip(&chip->gpio_chip, |
760 | &pca953x_irq_chip, | |
761 | client->irq); | |
89ea8bbe MZ |
762 | } |
763 | ||
764 | return 0; | |
89ea8bbe MZ |
765 | } |
766 | ||
89ea8bbe MZ |
767 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
768 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 769 | int irq_base) |
89ea8bbe MZ |
770 | { |
771 | struct i2c_client *client = chip->client; | |
89ea8bbe | 772 | |
72b38caf | 773 | if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
774 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
775 | ||
776 | return 0; | |
777 | } | |
89ea8bbe MZ |
778 | #endif |
779 | ||
7a04aaa3 | 780 | static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
781 | { |
782 | int ret; | |
f5f0b7aa | 783 | u8 val[MAX_BANK]; |
33226ffd | 784 | |
ec82d1eb MV |
785 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
786 | chip->regs->output + NBANK(chip)); | |
787 | if (ret != 0) | |
33226ffd HZ |
788 | goto out; |
789 | ||
0f25fda8 MV |
790 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
791 | chip->regs->direction + NBANK(chip)); | |
792 | if (ret != 0) | |
33226ffd HZ |
793 | goto out; |
794 | ||
795 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
796 | if (invert) |
797 | memset(val, 0xFF, NBANK(chip)); | |
798 | else | |
799 | memset(val, 0, NBANK(chip)); | |
800 | ||
7a04aaa3 | 801 | ret = pca953x_write_regs(chip, chip->regs->invert, val); |
33226ffd HZ |
802 | out: |
803 | return ret; | |
804 | } | |
805 | ||
3836309d | 806 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
807 | { |
808 | int ret; | |
f5f0b7aa | 809 | u8 val[MAX_BANK]; |
33226ffd | 810 | |
7a04aaa3 | 811 | ret = device_pca95xx_init(chip, invert); |
c75a3772 NK |
812 | if (ret) |
813 | goto out; | |
33226ffd | 814 | |
20a8a968 | 815 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 816 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
817 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
818 | if (ret) | |
819 | goto out; | |
33226ffd HZ |
820 | |
821 | return 0; | |
822 | out: | |
823 | return ret; | |
824 | } | |
825 | ||
6f29c9af BD |
826 | static const struct of_device_id pca953x_dt_ids[]; |
827 | ||
3836309d | 828 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 829 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 830 | { |
f3dc3630 GL |
831 | struct pca953x_platform_data *pdata; |
832 | struct pca953x_chip *chip; | |
6a7b36aa | 833 | int irq_base = 0; |
7ea2aa20 | 834 | int ret; |
6a7b36aa | 835 | u32 invert = 0; |
e23efa31 | 836 | struct regulator *reg; |
9e60fdcf | 837 | |
b42748c9 LW |
838 | chip = devm_kzalloc(&client->dev, |
839 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
840 | if (chip == NULL) |
841 | return -ENOMEM; | |
842 | ||
e56aee18 | 843 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
844 | if (pdata) { |
845 | irq_base = pdata->irq_base; | |
846 | chip->gpio_start = pdata->gpio_base; | |
847 | invert = pdata->invert; | |
848 | chip->names = pdata->names; | |
849 | } else { | |
054ccdef SL |
850 | struct gpio_desc *reset_gpio; |
851 | ||
4bb93349 MP |
852 | chip->gpio_start = -1; |
853 | irq_base = 0; | |
054ccdef | 854 | |
96530b37 AS |
855 | /* |
856 | * See if we need to de-assert a reset pin. | |
857 | * | |
858 | * There is no known ACPI-enabled platforms that are | |
859 | * using "reset" GPIO. Otherwise any of those platform | |
860 | * must use _DSD method with corresponding property. | |
861 | */ | |
054ccdef SL |
862 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
863 | GPIOD_OUT_LOW); | |
864 | if (IS_ERR(reset_gpio)) | |
865 | return PTR_ERR(reset_gpio); | |
1965d303 | 866 | } |
9e60fdcf | 867 | |
868 | chip->client = client; | |
869 | ||
e23efa31 PR |
870 | reg = devm_regulator_get(&client->dev, "vcc"); |
871 | if (IS_ERR(reg)) { | |
872 | ret = PTR_ERR(reg); | |
873 | if (ret != -EPROBE_DEFER) | |
874 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
875 | return ret; | |
876 | } | |
877 | ret = regulator_enable(reg); | |
878 | if (ret) { | |
879 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
880 | return ret; | |
881 | } | |
882 | chip->regulator = reg; | |
883 | ||
6212e1d6 WS |
884 | if (i2c_id) { |
885 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 886 | } else { |
6212e1d6 | 887 | const struct acpi_device_id *acpi_id; |
67bab935 | 888 | struct device *dev = &client->dev; |
f32517bf | 889 | |
67bab935 TR |
890 | chip->driver_data = (uintptr_t)of_device_get_match_data(dev); |
891 | if (!chip->driver_data) { | |
892 | acpi_id = acpi_match_device(pca953x_acpi_ids, dev); | |
87840a2b | 893 | if (!acpi_id) { |
e23efa31 PR |
894 | ret = -ENODEV; |
895 | goto err_exit; | |
896 | } | |
f32517bf | 897 | |
6212e1d6 | 898 | chip->driver_data = acpi_id->driver_data; |
6f29c9af | 899 | } |
f32517bf AS |
900 | } |
901 | ||
49427232 MV |
902 | i2c_set_clientdata(client, chip); |
903 | ||
904 | chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); | |
905 | if (IS_ERR(chip->regmap)) { | |
906 | ret = PTR_ERR(chip->regmap); | |
907 | goto err_exit; | |
908 | } | |
909 | ||
0f25fda8 MV |
910 | regcache_mark_dirty(chip->regmap); |
911 | ||
6e20fb18 | 912 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
913 | /* |
914 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
915 | * expander using the same driver higher on the device tree, read the | |
916 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
917 | * subclass for chip->i2c_lock. | |
918 | * | |
919 | * REVISIT: This solution is not complete. It protects us from lockdep | |
920 | * false positives when the expander controlling the i2c-mux is on | |
921 | * a different level on the device tree, but not when it's on the same | |
922 | * level on a different branch (in which case the subclass number | |
923 | * would be the same). | |
924 | * | |
925 | * TODO: Once a correct solution is developed, a similar fix should be | |
926 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
927 | * regmap-i2c). | |
928 | */ | |
559b4699 BG |
929 | lockdep_set_subclass(&chip->i2c_lock, |
930 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 931 | |
9e60fdcf | 932 | /* initialize cached registers from their original values. |
933 | * we can't share this chip with another i2c master. | |
934 | */ | |
c6664149 | 935 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 936 | |
7a04aaa3 MV |
937 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
938 | chip->regs = &pca953x_regs; | |
939 | ret = device_pca95xx_init(chip, invert); | |
940 | } else { | |
941 | chip->regs = &pca957x_regs; | |
7ea2aa20 | 942 | ret = device_pca957x_init(chip, invert); |
7a04aaa3 | 943 | } |
7ea2aa20 | 944 | if (ret) |
e23efa31 | 945 | goto err_exit; |
9e60fdcf | 946 | |
0ece84f5 | 947 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 948 | if (ret) |
e23efa31 | 949 | goto err_exit; |
f5e8ff48 | 950 | |
c6664149 | 951 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 952 | if (ret) |
e23efa31 | 953 | goto err_exit; |
9e60fdcf | 954 | |
c6dcf592 | 955 | if (pdata && pdata->setup) { |
9e60fdcf | 956 | ret = pdata->setup(client, chip->gpio_chip.base, |
957 | chip->gpio_chip.ngpio, pdata->context); | |
958 | if (ret < 0) | |
959 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
960 | } | |
961 | ||
9e60fdcf | 962 | return 0; |
e23efa31 PR |
963 | |
964 | err_exit: | |
965 | regulator_disable(chip->regulator); | |
966 | return ret; | |
9e60fdcf | 967 | } |
968 | ||
f3dc3630 | 969 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 970 | { |
e56aee18 | 971 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 972 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 973 | int ret; |
9e60fdcf | 974 | |
c6dcf592 | 975 | if (pdata && pdata->teardown) { |
9e60fdcf | 976 | ret = pdata->teardown(client, chip->gpio_chip.base, |
977 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 978 | if (ret < 0) |
9e60fdcf | 979 | dev_err(&client->dev, "%s failed, %d\n", |
980 | "teardown", ret); | |
bf62efeb AB |
981 | } else { |
982 | ret = 0; | |
9e60fdcf | 983 | } |
984 | ||
e23efa31 PR |
985 | regulator_disable(chip->regulator); |
986 | ||
987 | return ret; | |
9e60fdcf | 988 | } |
989 | ||
6f29c9af BD |
990 | /* convenience to stop overlong match-table lines */ |
991 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
992 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
993 | ||
ed32620e | 994 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
995 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
996 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
997 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
998 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
999 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
1000 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
1001 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
1002 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
1003 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
1004 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
1005 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
1006 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
1007 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
1008 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
1009 | ||
0cdf21b3 NS |
1010 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
1011 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, | |
3a711e0d | 1012 | |
6f29c9af BD |
1013 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
1014 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
1015 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
1016 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 1017 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1018 | |
1019 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 1020 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
1021 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
1022 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
1023 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
1024 | ||
8a64e557 | 1025 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6f29c9af BD |
1026 | |
1027 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
1028 | { } |
1029 | }; | |
1030 | ||
1031 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
1032 | ||
f3dc3630 | 1033 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 1034 | .driver = { |
f3dc3630 | 1035 | .name = "pca953x", |
ed32620e | 1036 | .of_match_table = pca953x_dt_ids, |
f32517bf | 1037 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 1038 | }, |
f3dc3630 GL |
1039 | .probe = pca953x_probe, |
1040 | .remove = pca953x_remove, | |
3760f736 | 1041 | .id_table = pca953x_id, |
9e60fdcf | 1042 | }; |
1043 | ||
f3dc3630 | 1044 | static int __init pca953x_init(void) |
9e60fdcf | 1045 | { |
f3dc3630 | 1046 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 1047 | } |
2f8d1197 DB |
1048 | /* register after i2c postcore initcall and before |
1049 | * subsys initcalls that may rely on these GPIOs | |
1050 | */ | |
1051 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1052 | |
f3dc3630 | 1053 | static void __exit pca953x_exit(void) |
9e60fdcf | 1054 | { |
f3dc3630 | 1055 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1056 | } |
f3dc3630 | 1057 | module_exit(pca953x_exit); |
9e60fdcf | 1058 | |
1059 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1060 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1061 | MODULE_LICENSE("GPL"); |