Commit | Line | Data |
---|---|---|
9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
b413d7a0 | 14 | #include <linux/acpi.h> |
d120c17f | 15 | #include <linux/gpio.h> |
054ccdef | 16 | #include <linux/gpio/consumer.h> |
9e60fdcf | 17 | #include <linux/i2c.h> |
b413d7a0 AS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_platform.h> | |
5877457a | 22 | #include <linux/platform_data/pca953x.h> |
b413d7a0 | 23 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
b413d7a0 | 25 | |
9b8e3ec3 | 26 | #include <asm/unaligned.h> |
9e60fdcf | 27 | |
0950c19a NS |
28 | #define PCA953X_INPUT 0x00 |
29 | #define PCA953X_OUTPUT 0x01 | |
30 | #define PCA953X_INVERT 0x02 | |
31 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 32 | |
ae79c190 AS |
33 | #define REG_ADDR_AI 0x80 |
34 | ||
0950c19a NS |
35 | #define PCA957X_IN 0x00 |
36 | #define PCA957X_INVRT 0x01 | |
37 | #define PCA957X_BKEN 0x02 | |
38 | #define PCA957X_PUPD 0x03 | |
39 | #define PCA957X_CFG 0x04 | |
40 | #define PCA957X_OUT 0x05 | |
41 | #define PCA957X_MSK 0x06 | |
42 | #define PCA957X_INTS 0x07 | |
33226ffd | 43 | |
6315d231 | 44 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 45 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
46 | #define PCAL953X_PULL_EN 0x23 |
47 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
48 | #define PCAL953X_INT_MASK 0x25 |
49 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 50 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 51 | |
a0ecbccc NS |
52 | #define PCAL6524_INT_EDGE 0x28 |
53 | #define PCAL6524_INT_CLR 0x2a | |
54 | #define PCAL6524_IN_STATUS 0x2b | |
55 | #define PCAL6524_OUT_INDCONF 0x2c | |
56 | #define PCAL6524_DEBOUNCE 0x2d | |
57 | ||
33226ffd | 58 | #define PCA_GPIO_MASK 0x00FF |
394aeef8 NS |
59 | |
60 | #define PCAL_GPIO_MASK 0x1f | |
61 | #define PCAL_PINCTRL_MASK 0xe0 | |
62 | ||
33226ffd | 63 | #define PCA_INT 0x0100 |
8c7a92da | 64 | #define PCA_PCAL 0x0200 |
0cdf21b3 | 65 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
33226ffd HZ |
66 | #define PCA953X_TYPE 0x1000 |
67 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
68 | #define PCA_TYPE_MASK 0xF000 |
69 | ||
70 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 71 | |
3760f736 | 72 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 73 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
74 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
75 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
76 | { "pca9536", 4 | PCA953X_TYPE, }, | |
77 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
78 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
80 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9556", 8 | PCA953X_TYPE, }, | |
83 | { "pca9557", 8 | PCA953X_TYPE, }, | |
84 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
85 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 86 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 87 | |
3a711e0d | 88 | { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
747e42a1 AS |
89 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
90 | ||
33226ffd HZ |
91 | { "max7310", 8 | PCA953X_TYPE, }, |
92 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
93 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
94 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 95 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
96 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
97 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
98 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 99 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 100 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 101 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 102 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 103 | { } |
f5e8ff48 | 104 | }; |
3760f736 | 105 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 106 | |
f32517bf | 107 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 108 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
109 | { } |
110 | }; | |
111 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
112 | ||
f5f0b7aa GC |
113 | #define MAX_BANK 5 |
114 | #define BANK_SZ 8 | |
115 | ||
a246b819 | 116 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 117 | |
53661f3b BG |
118 | struct pca953x_reg_config { |
119 | int direction; | |
120 | int output; | |
121 | int input; | |
122 | }; | |
123 | ||
124 | static const struct pca953x_reg_config pca953x_regs = { | |
125 | .direction = PCA953X_DIRECTION, | |
126 | .output = PCA953X_OUTPUT, | |
127 | .input = PCA953X_INPUT, | |
128 | }; | |
129 | ||
130 | static const struct pca953x_reg_config pca957x_regs = { | |
131 | .direction = PCA957X_CFG, | |
132 | .output = PCA957X_OUT, | |
133 | .input = PCA957X_IN, | |
134 | }; | |
135 | ||
f3dc3630 | 136 | struct pca953x_chip { |
9e60fdcf | 137 | unsigned gpio_start; |
f5f0b7aa GC |
138 | u8 reg_output[MAX_BANK]; |
139 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 140 | struct mutex i2c_lock; |
9e60fdcf | 141 | |
89ea8bbe MZ |
142 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
143 | struct mutex irq_lock; | |
f5f0b7aa GC |
144 | u8 irq_mask[MAX_BANK]; |
145 | u8 irq_stat[MAX_BANK]; | |
146 | u8 irq_trig_raise[MAX_BANK]; | |
147 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
148 | #endif |
149 | ||
9e60fdcf | 150 | struct i2c_client *client; |
151 | struct gpio_chip gpio_chip; | |
62154991 | 152 | const char *const *names; |
c6664149 | 153 | unsigned long driver_data; |
e23efa31 | 154 | struct regulator *regulator; |
53661f3b BG |
155 | |
156 | const struct pca953x_reg_config *regs; | |
7acc66e3 BG |
157 | |
158 | int (*write_regs)(struct pca953x_chip *, int, u8 *); | |
c6e3cf01 | 159 | int (*read_regs)(struct pca953x_chip *, int, u8 *); |
9e60fdcf | 160 | }; |
161 | ||
f5f0b7aa GC |
162 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
163 | int off) | |
164 | { | |
165 | int ret; | |
166 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
167 | int offset = off / BANK_SZ; | |
168 | ||
169 | ret = i2c_smbus_read_byte_data(chip->client, | |
170 | (reg << bank_shift) + offset); | |
171 | *val = ret; | |
172 | ||
173 | if (ret < 0) { | |
174 | dev_err(&chip->client->dev, "failed reading register\n"); | |
175 | return ret; | |
176 | } | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
182 | int off) | |
183 | { | |
8c7a92da | 184 | int ret; |
f5f0b7aa GC |
185 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
186 | int offset = off / BANK_SZ; | |
187 | ||
188 | ret = i2c_smbus_write_byte_data(chip->client, | |
189 | (reg << bank_shift) + offset, val); | |
190 | ||
191 | if (ret < 0) { | |
192 | dev_err(&chip->client->dev, "failed writing register\n"); | |
193 | return ret; | |
194 | } | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
7acc66e3 | 199 | static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 200 | { |
7acc66e3 BG |
201 | return i2c_smbus_write_byte_data(chip->client, reg, *val); |
202 | } | |
f5e8ff48 | 203 | |
7acc66e3 BG |
204 | static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) |
205 | { | |
b2dc4110 | 206 | u16 word = get_unaligned((u16 *)val); |
c4d1cbd7 | 207 | |
b2dc4110 | 208 | return i2c_smbus_write_word_data(chip->client, reg << 1, word); |
7acc66e3 BG |
209 | } |
210 | ||
211 | static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
212 | { | |
213 | int ret; | |
214 | ||
215 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]); | |
216 | if (ret < 0) | |
217 | return ret; | |
218 | ||
219 | return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]); | |
220 | } | |
f5e8ff48 | 221 | |
7acc66e3 BG |
222 | static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) |
223 | { | |
224 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
225 | ||
226 | return i2c_smbus_write_i2c_block_data(chip->client, | |
227 | (reg << bank_shift) | REG_ADDR_AI, | |
228 | NBANK(chip), val); | |
229 | } | |
230 | ||
231 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
232 | { | |
233 | int ret = 0; | |
234 | ||
235 | ret = chip->write_regs(chip, reg, val); | |
f5e8ff48 GL |
236 | if (ret < 0) { |
237 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 238 | return ret; |
f5e8ff48 GL |
239 | } |
240 | ||
241 | return 0; | |
9e60fdcf | 242 | } |
243 | ||
c6e3cf01 | 244 | static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 245 | { |
246 | int ret; | |
247 | ||
c6e3cf01 BG |
248 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
249 | *val = ret; | |
f5f0b7aa | 250 | |
c6e3cf01 BG |
251 | return ret; |
252 | } | |
253 | ||
254 | static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
255 | { | |
256 | int ret; | |
257 | ||
258 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); | |
b2dc4110 | 259 | put_unaligned(ret, (u16 *)val); |
c6e3cf01 BG |
260 | |
261 | return ret; | |
262 | } | |
263 | ||
264 | static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) | |
265 | { | |
266 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
267 | ||
268 | return i2c_smbus_read_i2c_block_data(chip->client, | |
269 | (reg << bank_shift) | REG_ADDR_AI, | |
270 | NBANK(chip), val); | |
271 | } | |
272 | ||
273 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
274 | { | |
275 | int ret; | |
276 | ||
277 | ret = chip->read_regs(chip, reg, val); | |
9e60fdcf | 278 | if (ret < 0) { |
279 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 280 | return ret; |
9e60fdcf | 281 | } |
282 | ||
9e60fdcf | 283 | return 0; |
284 | } | |
285 | ||
f3dc3630 | 286 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 287 | { |
468e67f6 | 288 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 289 | u8 reg_val; |
53661f3b | 290 | int ret; |
9e60fdcf | 291 | |
6e20fb18 | 292 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 293 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd | 294 | |
53661f3b | 295 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 296 | if (ret) |
6e20fb18 | 297 | goto exit; |
9e60fdcf | 298 | |
f5f0b7aa | 299 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
300 | exit: |
301 | mutex_unlock(&chip->i2c_lock); | |
302 | return ret; | |
9e60fdcf | 303 | } |
304 | ||
f3dc3630 | 305 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 306 | unsigned off, int val) |
307 | { | |
468e67f6 | 308 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 309 | u8 reg_val; |
53661f3b | 310 | int ret; |
9e60fdcf | 311 | |
6e20fb18 | 312 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 313 | /* set output level */ |
314 | if (val) | |
f5f0b7aa GC |
315 | reg_val = chip->reg_output[off / BANK_SZ] |
316 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 317 | else |
f5f0b7aa GC |
318 | reg_val = chip->reg_output[off / BANK_SZ] |
319 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 320 | |
53661f3b | 321 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 322 | if (ret) |
6e20fb18 | 323 | goto exit; |
9e60fdcf | 324 | |
f5f0b7aa | 325 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 326 | |
327 | /* then direction */ | |
f5f0b7aa | 328 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
53661f3b | 329 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 330 | if (ret) |
6e20fb18 | 331 | goto exit; |
9e60fdcf | 332 | |
f5f0b7aa | 333 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
334 | exit: |
335 | mutex_unlock(&chip->i2c_lock); | |
336 | return ret; | |
9e60fdcf | 337 | } |
338 | ||
f3dc3630 | 339 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 340 | { |
468e67f6 | 341 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 342 | u32 reg_val; |
53661f3b | 343 | int ret; |
9e60fdcf | 344 | |
6e20fb18 | 345 | mutex_lock(&chip->i2c_lock); |
53661f3b | 346 | ret = pca953x_read_single(chip, chip->regs->input, ®_val, off); |
6e20fb18 | 347 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 348 | if (ret < 0) { |
349 | /* NOTE: diagnostic already emitted; that's all we should | |
350 | * do unless gpio_*_value_cansleep() calls become different | |
351 | * from their nonsleeping siblings (and report faults). | |
352 | */ | |
353 | return 0; | |
354 | } | |
355 | ||
40a625da | 356 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 357 | } |
358 | ||
f3dc3630 | 359 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 360 | { |
468e67f6 | 361 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 362 | u8 reg_val; |
53661f3b | 363 | int ret; |
9e60fdcf | 364 | |
6e20fb18 | 365 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 366 | if (val) |
f5f0b7aa GC |
367 | reg_val = chip->reg_output[off / BANK_SZ] |
368 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 369 | else |
f5f0b7aa GC |
370 | reg_val = chip->reg_output[off / BANK_SZ] |
371 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 372 | |
53661f3b | 373 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 374 | if (ret) |
6e20fb18 | 375 | goto exit; |
9e60fdcf | 376 | |
f5f0b7aa | 377 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
378 | exit: |
379 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 380 | } |
381 | ||
66e57192 AS |
382 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
383 | { | |
384 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
385 | u32 reg_val; | |
386 | int ret; | |
387 | ||
388 | mutex_lock(&chip->i2c_lock); | |
389 | ret = pca953x_read_single(chip, chip->regs->direction, ®_val, off); | |
390 | mutex_unlock(&chip->i2c_lock); | |
391 | if (ret < 0) | |
392 | return ret; | |
393 | ||
394 | return !!(reg_val & (1u << (off % BANK_SZ))); | |
395 | } | |
396 | ||
b4818afe | 397 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 398 | unsigned long *mask, unsigned long *bits) |
b4818afe | 399 | { |
468e67f6 | 400 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d BG |
401 | unsigned int bank_mask, bank_val; |
402 | int bank_shift, bank; | |
b4818afe | 403 | u8 reg_val[MAX_BANK]; |
53661f3b | 404 | int ret; |
ea3d579d BG |
405 | |
406 | bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
b4818afe | 407 | |
b4818afe | 408 | mutex_lock(&chip->i2c_lock); |
386377b5 | 409 | memcpy(reg_val, chip->reg_output, NBANK(chip)); |
ea3d579d BG |
410 | for (bank = 0; bank < NBANK(chip); bank++) { |
411 | bank_mask = mask[bank / sizeof(*mask)] >> | |
412 | ((bank % sizeof(*mask)) * 8); | |
413 | if (bank_mask) { | |
414 | bank_val = bits[bank / sizeof(*bits)] >> | |
415 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 416 | bank_val &= bank_mask; |
ea3d579d | 417 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
418 | } |
419 | } | |
ea3d579d | 420 | |
53661f3b BG |
421 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
422 | chip->regs->output << bank_shift, | |
423 | NBANK(chip), reg_val); | |
b4818afe PR |
424 | if (ret) |
425 | goto exit; | |
426 | ||
427 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
428 | exit: | |
429 | mutex_unlock(&chip->i2c_lock); | |
430 | } | |
431 | ||
f5e8ff48 | 432 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 433 | { |
434 | struct gpio_chip *gc; | |
435 | ||
436 | gc = &chip->gpio_chip; | |
437 | ||
f3dc3630 GL |
438 | gc->direction_input = pca953x_gpio_direction_input; |
439 | gc->direction_output = pca953x_gpio_direction_output; | |
440 | gc->get = pca953x_gpio_get_value; | |
441 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 442 | gc->get_direction = pca953x_gpio_get_direction; |
b4818afe | 443 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 444 | gc->can_sleep = true; |
9e60fdcf | 445 | |
446 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
447 | gc->ngpio = gpios; |
448 | gc->label = chip->client->name; | |
58383c78 | 449 | gc->parent = &chip->client->dev; |
d72cbed0 | 450 | gc->owner = THIS_MODULE; |
77906a54 | 451 | gc->names = chip->names; |
9e60fdcf | 452 | } |
453 | ||
89ea8bbe | 454 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 455 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 456 | { |
7bcbce55 | 457 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 458 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 459 | |
f5f0b7aa | 460 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
461 | } |
462 | ||
6f5cfc0e | 463 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 464 | { |
7bcbce55 | 465 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 466 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 467 | |
f5f0b7aa | 468 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
469 | } |
470 | ||
6f5cfc0e | 471 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 472 | { |
7bcbce55 | 473 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 474 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
475 | |
476 | mutex_lock(&chip->irq_lock); | |
477 | } | |
478 | ||
6f5cfc0e | 479 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 480 | { |
7bcbce55 | 481 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 482 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
483 | u8 new_irqs; |
484 | int level, i; | |
44896bea YL |
485 | u8 invert_irq_mask[MAX_BANK]; |
486 | ||
487 | if (chip->driver_data & PCA_PCAL) { | |
488 | /* Enable latch on interrupt-enabled inputs */ | |
489 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
490 | ||
491 | for (i = 0; i < NBANK(chip); i++) | |
492 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
493 | ||
494 | /* Unmask enabled interrupts */ | |
495 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
496 | } | |
a2cb9aeb MZ |
497 | |
498 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
499 | for (i = 0; i < NBANK(chip); i++) { |
500 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
501 | new_irqs &= ~chip->reg_direction[i]; | |
502 | ||
503 | while (new_irqs) { | |
504 | level = __ffs(new_irqs); | |
505 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
506 | level + (BANK_SZ * i)); | |
507 | new_irqs &= ~(1 << level); | |
508 | } | |
a2cb9aeb | 509 | } |
89ea8bbe MZ |
510 | |
511 | mutex_unlock(&chip->irq_lock); | |
512 | } | |
513 | ||
6f5cfc0e | 514 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 515 | { |
7bcbce55 | 516 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 517 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
518 | int bank_nb = d->hwirq / BANK_SZ; |
519 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
520 | |
521 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
522 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 523 | d->irq, type); |
89ea8bbe MZ |
524 | return -EINVAL; |
525 | } | |
526 | ||
527 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 528 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 529 | else |
f5f0b7aa | 530 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
531 | |
532 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 533 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 534 | else |
f5f0b7aa | 535 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 536 | |
a2cb9aeb | 537 | return 0; |
89ea8bbe MZ |
538 | } |
539 | ||
0a70fe00 GD |
540 | static void pca953x_irq_shutdown(struct irq_data *d) |
541 | { | |
542 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); | |
543 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
544 | ||
545 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | |
546 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | |
547 | } | |
548 | ||
89ea8bbe MZ |
549 | static struct irq_chip pca953x_irq_chip = { |
550 | .name = "pca953x", | |
6f5cfc0e LB |
551 | .irq_mask = pca953x_irq_mask, |
552 | .irq_unmask = pca953x_irq_unmask, | |
553 | .irq_bus_lock = pca953x_irq_bus_lock, | |
554 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
555 | .irq_set_type = pca953x_irq_set_type, | |
0a70fe00 | 556 | .irq_shutdown = pca953x_irq_shutdown, |
89ea8bbe MZ |
557 | }; |
558 | ||
b6ac1280 | 559 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 560 | { |
f5f0b7aa GC |
561 | u8 cur_stat[MAX_BANK]; |
562 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
563 | bool pending_seen = false; |
564 | bool trigger_seen = false; | |
565 | u8 trigger[MAX_BANK]; | |
53661f3b | 566 | int ret, i; |
33226ffd | 567 | |
44896bea YL |
568 | if (chip->driver_data & PCA_PCAL) { |
569 | /* Read the current interrupt status from the device */ | |
570 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
571 | if (ret) | |
572 | return false; | |
573 | ||
574 | /* Check latched inputs and clear interrupt status */ | |
575 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
576 | if (ret) | |
577 | return false; | |
578 | ||
579 | for (i = 0; i < NBANK(chip); i++) { | |
580 | /* Apply filter for rising/falling edge selection */ | |
581 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
582 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
583 | pending[i] &= trigger[i]; | |
584 | if (pending[i]) | |
585 | pending_seen = true; | |
586 | } | |
587 | ||
588 | return pending_seen; | |
589 | } | |
590 | ||
53661f3b | 591 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 592 | if (ret) |
b6ac1280 | 593 | return false; |
89ea8bbe MZ |
594 | |
595 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
596 | for (i = 0; i < NBANK(chip); i++) |
597 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 598 | |
f5f0b7aa | 599 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 600 | |
f5f0b7aa GC |
601 | for (i = 0; i < NBANK(chip); i++) { |
602 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
603 | if (trigger[i]) |
604 | trigger_seen = true; | |
f5f0b7aa GC |
605 | } |
606 | ||
b6ac1280 JS |
607 | if (!trigger_seen) |
608 | return false; | |
89ea8bbe | 609 | |
f5f0b7aa | 610 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 611 | |
f5f0b7aa GC |
612 | for (i = 0; i < NBANK(chip); i++) { |
613 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
614 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
615 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
616 | if (pending[i]) |
617 | pending_seen = true; | |
f5f0b7aa | 618 | } |
89ea8bbe | 619 | |
b6ac1280 | 620 | return pending_seen; |
89ea8bbe MZ |
621 | } |
622 | ||
623 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
624 | { | |
625 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
626 | u8 pending[MAX_BANK]; |
627 | u8 level; | |
3275d072 | 628 | unsigned nhandled = 0; |
f5f0b7aa | 629 | int i; |
89ea8bbe | 630 | |
f5f0b7aa | 631 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 632 | return IRQ_NONE; |
89ea8bbe | 633 | |
f5f0b7aa GC |
634 | for (i = 0; i < NBANK(chip); i++) { |
635 | while (pending[i]) { | |
636 | level = __ffs(pending[i]); | |
f0fbe7bc | 637 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
f5f0b7aa GC |
638 | level + (BANK_SZ * i))); |
639 | pending[i] &= ~(1 << level); | |
3275d072 | 640 | nhandled++; |
f5f0b7aa GC |
641 | } |
642 | } | |
89ea8bbe | 643 | |
3275d072 | 644 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
645 | } |
646 | ||
647 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 648 | int irq_base) |
89ea8bbe MZ |
649 | { |
650 | struct i2c_client *client = chip->client; | |
53661f3b | 651 | int ret, i; |
89ea8bbe | 652 | |
4bb93349 | 653 | if (client->irq && irq_base != -1 |
c6664149 | 654 | && (chip->driver_data & PCA_INT)) { |
53661f3b BG |
655 | ret = pca953x_read_regs(chip, |
656 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 657 | if (ret) |
b42748c9 | 658 | return ret; |
89ea8bbe MZ |
659 | |
660 | /* | |
661 | * There is no way to know which GPIO line generated the | |
662 | * interrupt. We have to rely on the previous read for | |
663 | * this purpose. | |
664 | */ | |
f5f0b7aa GC |
665 | for (i = 0; i < NBANK(chip); i++) |
666 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
667 | mutex_init(&chip->irq_lock); |
668 | ||
b42748c9 LW |
669 | ret = devm_request_threaded_irq(&client->dev, |
670 | client->irq, | |
89ea8bbe MZ |
671 | NULL, |
672 | pca953x_irq_handler, | |
91329132 TS |
673 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
674 | IRQF_SHARED, | |
89ea8bbe MZ |
675 | dev_name(&client->dev), chip); |
676 | if (ret) { | |
677 | dev_err(&client->dev, "failed to request irq %d\n", | |
678 | client->irq); | |
0e8f2fda | 679 | return ret; |
89ea8bbe MZ |
680 | } |
681 | ||
d245b3f9 LW |
682 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, |
683 | &pca953x_irq_chip, | |
684 | irq_base, | |
685 | handle_simple_irq, | |
686 | IRQ_TYPE_NONE); | |
7bcbce55 LW |
687 | if (ret) { |
688 | dev_err(&client->dev, | |
689 | "could not connect irqchip to gpiochip\n"); | |
690 | return ret; | |
691 | } | |
fdd50409 | 692 | |
d245b3f9 LW |
693 | gpiochip_set_nested_irqchip(&chip->gpio_chip, |
694 | &pca953x_irq_chip, | |
695 | client->irq); | |
89ea8bbe MZ |
696 | } |
697 | ||
698 | return 0; | |
89ea8bbe MZ |
699 | } |
700 | ||
89ea8bbe MZ |
701 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
702 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 703 | int irq_base) |
89ea8bbe MZ |
704 | { |
705 | struct i2c_client *client = chip->client; | |
89ea8bbe | 706 | |
c6664149 | 707 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
708 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
709 | ||
710 | return 0; | |
711 | } | |
89ea8bbe MZ |
712 | #endif |
713 | ||
3836309d | 714 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
715 | { |
716 | int ret; | |
f5f0b7aa | 717 | u8 val[MAX_BANK]; |
33226ffd | 718 | |
53661f3b BG |
719 | chip->regs = &pca953x_regs; |
720 | ||
721 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
722 | if (ret) |
723 | goto out; | |
724 | ||
53661f3b BG |
725 | ret = pca953x_read_regs(chip, chip->regs->direction, |
726 | chip->reg_direction); | |
33226ffd HZ |
727 | if (ret) |
728 | goto out; | |
729 | ||
730 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
731 | if (invert) |
732 | memset(val, 0xFF, NBANK(chip)); | |
733 | else | |
734 | memset(val, 0, NBANK(chip)); | |
735 | ||
736 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
737 | out: |
738 | return ret; | |
739 | } | |
740 | ||
3836309d | 741 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
742 | { |
743 | int ret; | |
f5f0b7aa | 744 | u8 val[MAX_BANK]; |
33226ffd | 745 | |
53661f3b BG |
746 | chip->regs = &pca957x_regs; |
747 | ||
748 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
749 | if (ret) |
750 | goto out; | |
53661f3b BG |
751 | ret = pca953x_read_regs(chip, chip->regs->direction, |
752 | chip->reg_direction); | |
33226ffd HZ |
753 | if (ret) |
754 | goto out; | |
755 | ||
756 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
757 | if (invert) |
758 | memset(val, 0xFF, NBANK(chip)); | |
759 | else | |
760 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
761 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
762 | if (ret) | |
763 | goto out; | |
33226ffd | 764 | |
20a8a968 | 765 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 766 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
767 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
768 | if (ret) | |
769 | goto out; | |
33226ffd HZ |
770 | |
771 | return 0; | |
772 | out: | |
773 | return ret; | |
774 | } | |
775 | ||
6f29c9af BD |
776 | static const struct of_device_id pca953x_dt_ids[]; |
777 | ||
3836309d | 778 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 779 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 780 | { |
f3dc3630 GL |
781 | struct pca953x_platform_data *pdata; |
782 | struct pca953x_chip *chip; | |
6a7b36aa | 783 | int irq_base = 0; |
7ea2aa20 | 784 | int ret; |
6a7b36aa | 785 | u32 invert = 0; |
e23efa31 | 786 | struct regulator *reg; |
9e60fdcf | 787 | |
b42748c9 LW |
788 | chip = devm_kzalloc(&client->dev, |
789 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
790 | if (chip == NULL) |
791 | return -ENOMEM; | |
792 | ||
e56aee18 | 793 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
794 | if (pdata) { |
795 | irq_base = pdata->irq_base; | |
796 | chip->gpio_start = pdata->gpio_base; | |
797 | invert = pdata->invert; | |
798 | chip->names = pdata->names; | |
799 | } else { | |
054ccdef SL |
800 | struct gpio_desc *reset_gpio; |
801 | ||
4bb93349 MP |
802 | chip->gpio_start = -1; |
803 | irq_base = 0; | |
054ccdef | 804 | |
96530b37 AS |
805 | /* |
806 | * See if we need to de-assert a reset pin. | |
807 | * | |
808 | * There is no known ACPI-enabled platforms that are | |
809 | * using "reset" GPIO. Otherwise any of those platform | |
810 | * must use _DSD method with corresponding property. | |
811 | */ | |
054ccdef SL |
812 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
813 | GPIOD_OUT_LOW); | |
814 | if (IS_ERR(reset_gpio)) | |
815 | return PTR_ERR(reset_gpio); | |
1965d303 | 816 | } |
9e60fdcf | 817 | |
818 | chip->client = client; | |
819 | ||
e23efa31 PR |
820 | reg = devm_regulator_get(&client->dev, "vcc"); |
821 | if (IS_ERR(reg)) { | |
822 | ret = PTR_ERR(reg); | |
823 | if (ret != -EPROBE_DEFER) | |
824 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
825 | return ret; | |
826 | } | |
827 | ret = regulator_enable(reg); | |
828 | if (ret) { | |
829 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
830 | return ret; | |
831 | } | |
832 | chip->regulator = reg; | |
833 | ||
6212e1d6 WS |
834 | if (i2c_id) { |
835 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 836 | } else { |
6212e1d6 | 837 | const struct acpi_device_id *acpi_id; |
67bab935 | 838 | struct device *dev = &client->dev; |
f32517bf | 839 | |
67bab935 TR |
840 | chip->driver_data = (uintptr_t)of_device_get_match_data(dev); |
841 | if (!chip->driver_data) { | |
842 | acpi_id = acpi_match_device(pca953x_acpi_ids, dev); | |
87840a2b | 843 | if (!acpi_id) { |
e23efa31 PR |
844 | ret = -ENODEV; |
845 | goto err_exit; | |
846 | } | |
f32517bf | 847 | |
6212e1d6 | 848 | chip->driver_data = acpi_id->driver_data; |
6f29c9af | 849 | } |
f32517bf AS |
850 | } |
851 | ||
6e20fb18 | 852 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
853 | /* |
854 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
855 | * expander using the same driver higher on the device tree, read the | |
856 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
857 | * subclass for chip->i2c_lock. | |
858 | * | |
859 | * REVISIT: This solution is not complete. It protects us from lockdep | |
860 | * false positives when the expander controlling the i2c-mux is on | |
861 | * a different level on the device tree, but not when it's on the same | |
862 | * level on a different branch (in which case the subclass number | |
863 | * would be the same). | |
864 | * | |
865 | * TODO: Once a correct solution is developed, a similar fix should be | |
866 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
867 | * regmap-i2c). | |
868 | */ | |
559b4699 BG |
869 | lockdep_set_subclass(&chip->i2c_lock, |
870 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 871 | |
9e60fdcf | 872 | /* initialize cached registers from their original values. |
873 | * we can't share this chip with another i2c master. | |
874 | */ | |
c6664149 | 875 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 876 | |
7acc66e3 BG |
877 | if (chip->gpio_chip.ngpio <= 8) { |
878 | chip->write_regs = pca953x_write_regs_8; | |
c6e3cf01 | 879 | chip->read_regs = pca953x_read_regs_8; |
7acc66e3 BG |
880 | } else if (chip->gpio_chip.ngpio >= 24) { |
881 | chip->write_regs = pca953x_write_regs_24; | |
c6e3cf01 | 882 | chip->read_regs = pca953x_read_regs_24; |
7acc66e3 BG |
883 | } else { |
884 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) | |
885 | chip->write_regs = pca953x_write_regs_16; | |
886 | else | |
887 | chip->write_regs = pca957x_write_regs_16; | |
c6e3cf01 | 888 | chip->read_regs = pca953x_read_regs_16; |
7acc66e3 BG |
889 | } |
890 | ||
60f547be | 891 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
7ea2aa20 | 892 | ret = device_pca953x_init(chip, invert); |
33226ffd | 893 | else |
7ea2aa20 WS |
894 | ret = device_pca957x_init(chip, invert); |
895 | if (ret) | |
e23efa31 | 896 | goto err_exit; |
9e60fdcf | 897 | |
0ece84f5 | 898 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 899 | if (ret) |
e23efa31 | 900 | goto err_exit; |
f5e8ff48 | 901 | |
c6664149 | 902 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 903 | if (ret) |
e23efa31 | 904 | goto err_exit; |
9e60fdcf | 905 | |
c6dcf592 | 906 | if (pdata && pdata->setup) { |
9e60fdcf | 907 | ret = pdata->setup(client, chip->gpio_chip.base, |
908 | chip->gpio_chip.ngpio, pdata->context); | |
909 | if (ret < 0) | |
910 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
911 | } | |
912 | ||
913 | i2c_set_clientdata(client, chip); | |
914 | return 0; | |
e23efa31 PR |
915 | |
916 | err_exit: | |
917 | regulator_disable(chip->regulator); | |
918 | return ret; | |
9e60fdcf | 919 | } |
920 | ||
f3dc3630 | 921 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 922 | { |
e56aee18 | 923 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 924 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 925 | int ret; |
9e60fdcf | 926 | |
c6dcf592 | 927 | if (pdata && pdata->teardown) { |
9e60fdcf | 928 | ret = pdata->teardown(client, chip->gpio_chip.base, |
929 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 930 | if (ret < 0) |
9e60fdcf | 931 | dev_err(&client->dev, "%s failed, %d\n", |
932 | "teardown", ret); | |
bf62efeb AB |
933 | } else { |
934 | ret = 0; | |
9e60fdcf | 935 | } |
936 | ||
e23efa31 PR |
937 | regulator_disable(chip->regulator); |
938 | ||
939 | return ret; | |
9e60fdcf | 940 | } |
941 | ||
6f29c9af BD |
942 | /* convenience to stop overlong match-table lines */ |
943 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
944 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
945 | ||
ed32620e | 946 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
947 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
948 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
949 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
950 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
951 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
952 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
953 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
954 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
955 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
956 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
957 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
958 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
959 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
960 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
961 | ||
0cdf21b3 NS |
962 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
963 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, | |
3a711e0d | 964 | |
6f29c9af BD |
965 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
966 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
967 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
968 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 969 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
970 | |
971 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 972 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
973 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
974 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
975 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
976 | ||
8a64e557 | 977 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6f29c9af BD |
978 | |
979 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
980 | { } |
981 | }; | |
982 | ||
983 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
984 | ||
f3dc3630 | 985 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 986 | .driver = { |
f3dc3630 | 987 | .name = "pca953x", |
ed32620e | 988 | .of_match_table = pca953x_dt_ids, |
f32517bf | 989 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 990 | }, |
f3dc3630 GL |
991 | .probe = pca953x_probe, |
992 | .remove = pca953x_remove, | |
3760f736 | 993 | .id_table = pca953x_id, |
9e60fdcf | 994 | }; |
995 | ||
f3dc3630 | 996 | static int __init pca953x_init(void) |
9e60fdcf | 997 | { |
f3dc3630 | 998 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 999 | } |
2f8d1197 DB |
1000 | /* register after i2c postcore initcall and before |
1001 | * subsys initcalls that may rely on these GPIOs | |
1002 | */ | |
1003 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1004 | |
f3dc3630 | 1005 | static void __exit pca953x_exit(void) |
9e60fdcf | 1006 | { |
f3dc3630 | 1007 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1008 | } |
f3dc3630 | 1009 | module_exit(pca953x_exit); |
9e60fdcf | 1010 | |
1011 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1012 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1013 | MODULE_LICENSE("GPL"); |