Commit | Line | Data |
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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9e60fdcf | 2 | /* |
1e191695 | 3 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 4 | * |
5 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
6 | * Copyright (C) 2007 Marvell International Ltd. | |
7 | * | |
8 | * Derived from drivers/i2c/chips/pca9539.c | |
9e60fdcf | 9 | */ |
10 | ||
b413d7a0 | 11 | #include <linux/acpi.h> |
63b484c2 | 12 | #include <linux/bits.h> |
644f3da0 | 13 | #include <linux/gpio/driver.h> |
054ccdef | 14 | #include <linux/gpio/consumer.h> |
9e60fdcf | 15 | #include <linux/i2c.h> |
b413d7a0 AS |
16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of_platform.h> | |
5877457a | 20 | #include <linux/platform_data/pca953x.h> |
49427232 | 21 | #include <linux/regmap.h> |
b413d7a0 | 22 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
b413d7a0 | 24 | |
9b8e3ec3 | 25 | #include <asm/unaligned.h> |
9e60fdcf | 26 | |
0950c19a NS |
27 | #define PCA953X_INPUT 0x00 |
28 | #define PCA953X_OUTPUT 0x01 | |
29 | #define PCA953X_INVERT 0x02 | |
30 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 31 | |
63b484c2 AS |
32 | #define REG_ADDR_MASK GENMASK(5, 0) |
33 | #define REG_ADDR_EXT BIT(6) | |
34 | #define REG_ADDR_AI BIT(7) | |
ae79c190 | 35 | |
0950c19a NS |
36 | #define PCA957X_IN 0x00 |
37 | #define PCA957X_INVRT 0x01 | |
38 | #define PCA957X_BKEN 0x02 | |
39 | #define PCA957X_PUPD 0x03 | |
40 | #define PCA957X_CFG 0x04 | |
41 | #define PCA957X_OUT 0x05 | |
42 | #define PCA957X_MSK 0x06 | |
43 | #define PCA957X_INTS 0x07 | |
33226ffd | 44 | |
6315d231 | 45 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 46 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
47 | #define PCAL953X_PULL_EN 0x23 |
48 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
49 | #define PCAL953X_INT_MASK 0x25 |
50 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 51 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 52 | |
a0ecbccc NS |
53 | #define PCAL6524_INT_EDGE 0x28 |
54 | #define PCAL6524_INT_CLR 0x2a | |
55 | #define PCAL6524_IN_STATUS 0x2b | |
56 | #define PCAL6524_OUT_INDCONF 0x2c | |
57 | #define PCAL6524_DEBOUNCE 0x2d | |
58 | ||
63b484c2 | 59 | #define PCA_GPIO_MASK GENMASK(7, 0) |
394aeef8 | 60 | |
63b484c2 AS |
61 | #define PCAL_GPIO_MASK GENMASK(4, 0) |
62 | #define PCAL_PINCTRL_MASK GENMASK(6, 5) | |
394aeef8 | 63 | |
63b484c2 AS |
64 | #define PCA_INT BIT(8) |
65 | #define PCA_PCAL BIT(9) | |
2870b3c5 | 66 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
63b484c2 AS |
67 | #define PCA953X_TYPE BIT(12) |
68 | #define PCA957X_TYPE BIT(13) | |
69 | #define PCA_TYPE_MASK GENMASK(15, 12) | |
c6664149 AS |
70 | |
71 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 72 | |
3760f736 | 73 | static const struct i2c_device_id pca953x_id[] = { |
12c7a4fc | 74 | { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, |
89f5df01 | 75 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
76 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
77 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
78 | { "pca9536", 4 | PCA953X_TYPE, }, | |
79 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
80 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
83 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
84 | { "pca9556", 8 | PCA953X_TYPE, }, | |
85 | { "pca9557", 8 | PCA953X_TYPE, }, | |
86 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
87 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 88 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 89 | |
2870b3c5 AS |
90 | { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
91 | { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, | |
92 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, | |
747e42a1 | 93 | |
33226ffd HZ |
94 | { "max7310", 8 | PCA953X_TYPE, }, |
95 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
96 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
97 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 98 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
99 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
100 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
101 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 102 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 103 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 104 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 105 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 106 | { } |
f5e8ff48 | 107 | }; |
3760f736 | 108 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 109 | |
f32517bf | 110 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
2870b3c5 | 111 | { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
f32517bf AS |
112 | { } |
113 | }; | |
114 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
115 | ||
f5f0b7aa GC |
116 | #define MAX_BANK 5 |
117 | #define BANK_SZ 8 | |
118 | ||
a246b819 | 119 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 120 | |
53661f3b BG |
121 | struct pca953x_reg_config { |
122 | int direction; | |
123 | int output; | |
124 | int input; | |
7a04aaa3 | 125 | int invert; |
53661f3b BG |
126 | }; |
127 | ||
128 | static const struct pca953x_reg_config pca953x_regs = { | |
129 | .direction = PCA953X_DIRECTION, | |
130 | .output = PCA953X_OUTPUT, | |
131 | .input = PCA953X_INPUT, | |
7a04aaa3 | 132 | .invert = PCA953X_INVERT, |
53661f3b BG |
133 | }; |
134 | ||
135 | static const struct pca953x_reg_config pca957x_regs = { | |
136 | .direction = PCA957X_CFG, | |
137 | .output = PCA957X_OUT, | |
138 | .input = PCA957X_IN, | |
7a04aaa3 | 139 | .invert = PCA957X_INVRT, |
53661f3b BG |
140 | }; |
141 | ||
f3dc3630 | 142 | struct pca953x_chip { |
9e60fdcf | 143 | unsigned gpio_start; |
6e20fb18 | 144 | struct mutex i2c_lock; |
49427232 | 145 | struct regmap *regmap; |
9e60fdcf | 146 | |
89ea8bbe MZ |
147 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
148 | struct mutex irq_lock; | |
f5f0b7aa GC |
149 | u8 irq_mask[MAX_BANK]; |
150 | u8 irq_stat[MAX_BANK]; | |
151 | u8 irq_trig_raise[MAX_BANK]; | |
152 | u8 irq_trig_fall[MAX_BANK]; | |
5c4fee63 | 153 | struct irq_chip irq_chip; |
89ea8bbe | 154 | #endif |
f70fbc15 | 155 | atomic_t wakeup_path; |
89ea8bbe | 156 | |
9e60fdcf | 157 | struct i2c_client *client; |
158 | struct gpio_chip gpio_chip; | |
62154991 | 159 | const char *const *names; |
c6664149 | 160 | unsigned long driver_data; |
e23efa31 | 161 | struct regulator *regulator; |
53661f3b BG |
162 | |
163 | const struct pca953x_reg_config *regs; | |
9e60fdcf | 164 | }; |
165 | ||
873d1e8e | 166 | static int pca953x_bank_shift(struct pca953x_chip *chip) |
f5f0b7aa | 167 | { |
873d1e8e MV |
168 | return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
169 | } | |
f5f0b7aa | 170 | |
49427232 MV |
171 | #define PCA953x_BANK_INPUT BIT(0) |
172 | #define PCA953x_BANK_OUTPUT BIT(1) | |
173 | #define PCA953x_BANK_POLARITY BIT(2) | |
174 | #define PCA953x_BANK_CONFIG BIT(3) | |
f5f0b7aa | 175 | |
49427232 MV |
176 | #define PCA957x_BANK_INPUT BIT(0) |
177 | #define PCA957x_BANK_POLARITY BIT(1) | |
178 | #define PCA957x_BANK_BUSHOLD BIT(2) | |
179 | #define PCA957x_BANK_CONFIG BIT(4) | |
180 | #define PCA957x_BANK_OUTPUT BIT(5) | |
181 | ||
182 | #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) | |
15add068 TP |
183 | #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) |
184 | #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) | |
49427232 MV |
185 | #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) |
186 | #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) | |
187 | ||
188 | /* | |
189 | * We care about the following registers: | |
190 | * - Standard set, below 0x40, each port can be replicated up to 8 times | |
191 | * - PCA953x standard | |
192 | * Input port 0x00 + 0 * bank_size R | |
193 | * Output port 0x00 + 1 * bank_size RW | |
194 | * Polarity Inversion port 0x00 + 2 * bank_size RW | |
195 | * Configuration port 0x00 + 3 * bank_size RW | |
196 | * - PCA957x with mixed up registers | |
197 | * Input port 0x00 + 0 * bank_size R | |
198 | * Polarity Inversion port 0x00 + 1 * bank_size RW | |
199 | * Bus hold port 0x00 + 2 * bank_size RW | |
200 | * Configuration port 0x00 + 4 * bank_size RW | |
201 | * Output port 0x00 + 5 * bank_size RW | |
202 | * | |
203 | * - Extended set, above 0x40, often chip specific. | |
204 | * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: | |
205 | * Input latch register 0x40 + 2 * bank_size RW | |
15add068 TP |
206 | * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW |
207 | * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW | |
49427232 MV |
208 | * Interrupt mask register 0x40 + 5 * bank_size RW |
209 | * Interrupt status register 0x40 + 6 * bank_size R | |
210 | * | |
211 | * - Registers with bit 0x80 set, the AI bit | |
212 | * The bit is cleared and the registers fall into one of the | |
213 | * categories above. | |
214 | */ | |
215 | ||
216 | static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, | |
217 | u32 checkbank) | |
218 | { | |
219 | int bank_shift = pca953x_bank_shift(chip); | |
220 | int bank = (reg & REG_ADDR_MASK) >> bank_shift; | |
221 | int offset = reg & (BIT(bank_shift) - 1); | |
222 | ||
223 | /* Special PCAL extended register check. */ | |
224 | if (reg & REG_ADDR_EXT) { | |
225 | if (!(chip->driver_data & PCA_PCAL)) | |
226 | return false; | |
227 | bank += 8; | |
f5f0b7aa GC |
228 | } |
229 | ||
49427232 MV |
230 | /* Register is not in the matching bank. */ |
231 | if (!(BIT(bank) & checkbank)) | |
232 | return false; | |
233 | ||
234 | /* Register is not within allowed range of bank. */ | |
235 | if (offset >= NBANK(chip)) | |
236 | return false; | |
237 | ||
238 | return true; | |
f5f0b7aa GC |
239 | } |
240 | ||
49427232 | 241 | static bool pca953x_readable_register(struct device *dev, unsigned int reg) |
f5f0b7aa | 242 | { |
49427232 MV |
243 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
244 | u32 bank; | |
f5f0b7aa | 245 | |
49427232 MV |
246 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
247 | bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | | |
248 | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; | |
249 | } else { | |
250 | bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | | |
251 | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | | |
252 | PCA957x_BANK_BUSHOLD; | |
253 | } | |
f5f0b7aa | 254 | |
49427232 | 255 | if (chip->driver_data & PCA_PCAL) { |
15add068 TP |
256 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | |
257 | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | | |
49427232 | 258 | PCAL9xxx_BANK_IRQ_STAT; |
f5f0b7aa GC |
259 | } |
260 | ||
49427232 | 261 | return pca953x_check_register(chip, reg, bank); |
f5f0b7aa GC |
262 | } |
263 | ||
49427232 | 264 | static bool pca953x_writeable_register(struct device *dev, unsigned int reg) |
9e60fdcf | 265 | { |
49427232 MV |
266 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
267 | u32 bank; | |
f5e8ff48 | 268 | |
49427232 MV |
269 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
270 | bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | | |
271 | PCA953x_BANK_CONFIG; | |
272 | } else { | |
273 | bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | | |
274 | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; | |
275 | } | |
c4d1cbd7 | 276 | |
49427232 | 277 | if (chip->driver_data & PCA_PCAL) |
15add068 TP |
278 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | |
279 | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; | |
49427232 MV |
280 | |
281 | return pca953x_check_register(chip, reg, bank); | |
7acc66e3 BG |
282 | } |
283 | ||
49427232 | 284 | static bool pca953x_volatile_register(struct device *dev, unsigned int reg) |
7acc66e3 | 285 | { |
49427232 MV |
286 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
287 | u32 bank; | |
7acc66e3 | 288 | |
49427232 MV |
289 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
290 | bank = PCA953x_BANK_INPUT; | |
291 | else | |
292 | bank = PCA957x_BANK_INPUT; | |
293 | ||
294 | if (chip->driver_data & PCA_PCAL) | |
295 | bank |= PCAL9xxx_BANK_IRQ_STAT; | |
7acc66e3 | 296 | |
49427232 | 297 | return pca953x_check_register(chip, reg, bank); |
7acc66e3 | 298 | } |
f5e8ff48 | 299 | |
d04e779f | 300 | static const struct regmap_config pca953x_i2c_regmap = { |
49427232 MV |
301 | .reg_bits = 8, |
302 | .val_bits = 8, | |
303 | ||
304 | .readable_reg = pca953x_readable_register, | |
305 | .writeable_reg = pca953x_writeable_register, | |
306 | .volatile_reg = pca953x_volatile_register, | |
307 | ||
308 | .cache_type = REGCACHE_RBTREE, | |
3b00691c NS |
309 | /* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */ |
310 | .max_register = 0xff, | |
49427232 MV |
311 | }; |
312 | ||
b32cecb4 MV |
313 | static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, |
314 | bool write, bool addrinc) | |
7acc66e3 | 315 | { |
b32cecb4 | 316 | int bank_shift = pca953x_bank_shift(chip); |
d5dbf9c2 NS |
317 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; |
318 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
b32cecb4 MV |
319 | u8 regaddr = pinctrl | addr | (off / BANK_SZ); |
320 | ||
321 | /* Single byte read doesn't need AI bit set. */ | |
322 | if (!addrinc) | |
323 | return regaddr; | |
324 | ||
325 | /* Chips with 24 and more GPIOs always support Auto Increment */ | |
326 | if (write && NBANK(chip) > 2) | |
327 | regaddr |= REG_ADDR_AI; | |
7acc66e3 | 328 | |
b32cecb4 MV |
329 | /* PCA9575 needs address-increment on multi-byte writes */ |
330 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) | |
331 | regaddr |= REG_ADDR_AI; | |
332 | ||
333 | return regaddr; | |
7acc66e3 BG |
334 | } |
335 | ||
336 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
337 | { | |
b32cecb4 | 338 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); |
90adb097 | 339 | int ret; |
7acc66e3 | 340 | |
49427232 | 341 | ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); |
f5e8ff48 GL |
342 | if (ret < 0) { |
343 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 344 | return ret; |
f5e8ff48 GL |
345 | } |
346 | ||
347 | return 0; | |
9e60fdcf | 348 | } |
349 | ||
c6e3cf01 BG |
350 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
351 | { | |
b32cecb4 | 352 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); |
c6e3cf01 BG |
353 | int ret; |
354 | ||
49427232 | 355 | ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); |
9e60fdcf | 356 | if (ret < 0) { |
357 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 358 | return ret; |
9e60fdcf | 359 | } |
360 | ||
9e60fdcf | 361 | return 0; |
362 | } | |
363 | ||
f3dc3630 | 364 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 365 | { |
468e67f6 | 366 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
367 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
368 | true, false); | |
369 | u8 bit = BIT(off % BANK_SZ); | |
53661f3b | 370 | int ret; |
9e60fdcf | 371 | |
6e20fb18 | 372 | mutex_lock(&chip->i2c_lock); |
0f25fda8 | 373 | ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); |
6e20fb18 RS |
374 | mutex_unlock(&chip->i2c_lock); |
375 | return ret; | |
9e60fdcf | 376 | } |
377 | ||
f3dc3630 | 378 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 379 | unsigned off, int val) |
380 | { | |
468e67f6 | 381 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
382 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
383 | true, false); | |
ec82d1eb MV |
384 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
385 | true, false); | |
0f25fda8 | 386 | u8 bit = BIT(off % BANK_SZ); |
53661f3b | 387 | int ret; |
9e60fdcf | 388 | |
6e20fb18 | 389 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 390 | /* set output level */ |
ec82d1eb | 391 | ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
9e60fdcf | 392 | if (ret) |
6e20fb18 | 393 | goto exit; |
9e60fdcf | 394 | |
9e60fdcf | 395 | /* then direction */ |
0f25fda8 | 396 | ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); |
6e20fb18 RS |
397 | exit: |
398 | mutex_unlock(&chip->i2c_lock); | |
399 | return ret; | |
9e60fdcf | 400 | } |
401 | ||
f3dc3630 | 402 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 403 | { |
468e67f6 | 404 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
87813cf3 MV |
405 | u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, |
406 | true, false); | |
407 | u8 bit = BIT(off % BANK_SZ); | |
ae79c190 | 408 | u32 reg_val; |
53661f3b | 409 | int ret; |
9e60fdcf | 410 | |
6e20fb18 | 411 | mutex_lock(&chip->i2c_lock); |
87813cf3 | 412 | ret = regmap_read(chip->regmap, inreg, ®_val); |
6e20fb18 | 413 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 414 | if (ret < 0) { |
415 | /* NOTE: diagnostic already emitted; that's all we should | |
416 | * do unless gpio_*_value_cansleep() calls become different | |
417 | * from their nonsleeping siblings (and report faults). | |
418 | */ | |
419 | return 0; | |
420 | } | |
421 | ||
87813cf3 | 422 | return !!(reg_val & bit); |
9e60fdcf | 423 | } |
424 | ||
f3dc3630 | 425 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 426 | { |
468e67f6 | 427 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ec82d1eb MV |
428 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
429 | true, false); | |
430 | u8 bit = BIT(off % BANK_SZ); | |
9e60fdcf | 431 | |
6e20fb18 | 432 | mutex_lock(&chip->i2c_lock); |
ec82d1eb | 433 | regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
6e20fb18 | 434 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 435 | } |
436 | ||
66e57192 AS |
437 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
438 | { | |
439 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
0f25fda8 MV |
440 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
441 | true, false); | |
442 | u8 bit = BIT(off % BANK_SZ); | |
66e57192 AS |
443 | u32 reg_val; |
444 | int ret; | |
445 | ||
446 | mutex_lock(&chip->i2c_lock); | |
0f25fda8 | 447 | ret = regmap_read(chip->regmap, dirreg, ®_val); |
66e57192 AS |
448 | mutex_unlock(&chip->i2c_lock); |
449 | if (ret < 0) | |
450 | return ret; | |
451 | ||
0f25fda8 | 452 | return !!(reg_val & bit); |
66e57192 AS |
453 | } |
454 | ||
b4818afe | 455 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 456 | unsigned long *mask, unsigned long *bits) |
b4818afe | 457 | { |
468e67f6 | 458 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d | 459 | unsigned int bank_mask, bank_val; |
873d1e8e | 460 | int bank; |
b4818afe | 461 | u8 reg_val[MAX_BANK]; |
53661f3b | 462 | int ret; |
ea3d579d | 463 | |
b4818afe | 464 | mutex_lock(&chip->i2c_lock); |
ec82d1eb MV |
465 | ret = pca953x_read_regs(chip, chip->regs->output, reg_val); |
466 | if (ret) | |
467 | goto exit; | |
468 | ||
ea3d579d BG |
469 | for (bank = 0; bank < NBANK(chip); bank++) { |
470 | bank_mask = mask[bank / sizeof(*mask)] >> | |
471 | ((bank % sizeof(*mask)) * 8); | |
472 | if (bank_mask) { | |
473 | bank_val = bits[bank / sizeof(*bits)] >> | |
474 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 475 | bank_val &= bank_mask; |
ea3d579d | 476 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
477 | } |
478 | } | |
ea3d579d | 479 | |
ec82d1eb | 480 | pca953x_write_regs(chip, chip->regs->output, reg_val); |
b4818afe PR |
481 | exit: |
482 | mutex_unlock(&chip->i2c_lock); | |
483 | } | |
484 | ||
15add068 TP |
485 | static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, |
486 | unsigned int offset, | |
487 | unsigned long config) | |
488 | { | |
489 | u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset, | |
490 | true, false); | |
491 | u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset, | |
492 | true, false); | |
493 | u8 bit = BIT(offset % BANK_SZ); | |
494 | int ret; | |
495 | ||
496 | /* | |
497 | * pull-up/pull-down configuration requires PCAL extended | |
498 | * registers | |
499 | */ | |
500 | if (!(chip->driver_data & PCA_PCAL)) | |
501 | return -ENOTSUPP; | |
502 | ||
503 | mutex_lock(&chip->i2c_lock); | |
504 | ||
505 | /* Disable pull-up/pull-down */ | |
506 | ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); | |
507 | if (ret) | |
508 | goto exit; | |
509 | ||
510 | /* Configure pull-up/pull-down */ | |
511 | if (config == PIN_CONFIG_BIAS_PULL_UP) | |
512 | ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); | |
513 | else if (config == PIN_CONFIG_BIAS_PULL_DOWN) | |
514 | ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); | |
515 | if (ret) | |
516 | goto exit; | |
517 | ||
518 | /* Enable pull-up/pull-down */ | |
519 | ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); | |
520 | ||
521 | exit: | |
522 | mutex_unlock(&chip->i2c_lock); | |
523 | return ret; | |
524 | } | |
525 | ||
526 | static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, | |
527 | unsigned long config) | |
528 | { | |
529 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
530 | ||
531 | switch (config) { | |
532 | case PIN_CONFIG_BIAS_PULL_UP: | |
533 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
534 | return pca953x_gpio_set_pull_up_down(chip, offset, config); | |
535 | default: | |
536 | return -ENOTSUPP; | |
537 | } | |
538 | } | |
539 | ||
f5e8ff48 | 540 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 541 | { |
542 | struct gpio_chip *gc; | |
543 | ||
544 | gc = &chip->gpio_chip; | |
545 | ||
f3dc3630 GL |
546 | gc->direction_input = pca953x_gpio_direction_input; |
547 | gc->direction_output = pca953x_gpio_direction_output; | |
548 | gc->get = pca953x_gpio_get_value; | |
549 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 550 | gc->get_direction = pca953x_gpio_get_direction; |
b4818afe | 551 | gc->set_multiple = pca953x_gpio_set_multiple; |
15add068 | 552 | gc->set_config = pca953x_gpio_set_config; |
9fb1f39e | 553 | gc->can_sleep = true; |
9e60fdcf | 554 | |
555 | gc->base = chip->gpio_start; | |
f5e8ff48 | 556 | gc->ngpio = gpios; |
5128f8d4 | 557 | gc->label = dev_name(&chip->client->dev); |
58383c78 | 558 | gc->parent = &chip->client->dev; |
d72cbed0 | 559 | gc->owner = THIS_MODULE; |
77906a54 | 560 | gc->names = chip->names; |
9e60fdcf | 561 | } |
562 | ||
89ea8bbe | 563 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 564 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 565 | { |
7bcbce55 | 566 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 567 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 568 | |
63b484c2 | 569 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~BIT(d->hwirq % BANK_SZ); |
89ea8bbe MZ |
570 | } |
571 | ||
6f5cfc0e | 572 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 573 | { |
7bcbce55 | 574 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 575 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 576 | |
63b484c2 | 577 | chip->irq_mask[d->hwirq / BANK_SZ] |= BIT(d->hwirq % BANK_SZ); |
89ea8bbe MZ |
578 | } |
579 | ||
2a9a2f27 GU |
580 | static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) |
581 | { | |
582 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
583 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
584 | ||
f70fbc15 GU |
585 | if (on) |
586 | atomic_inc(&chip->wakeup_path); | |
587 | else | |
588 | atomic_dec(&chip->wakeup_path); | |
589 | ||
2a9a2f27 GU |
590 | return irq_set_irq_wake(chip->client->irq, on); |
591 | } | |
592 | ||
6f5cfc0e | 593 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 594 | { |
7bcbce55 | 595 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 596 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
597 | |
598 | mutex_lock(&chip->irq_lock); | |
599 | } | |
600 | ||
6f5cfc0e | 601 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 602 | { |
7bcbce55 | 603 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 604 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
605 | u8 new_irqs; |
606 | int level, i; | |
44896bea | 607 | u8 invert_irq_mask[MAX_BANK]; |
bc624a06 | 608 | u8 reg_direction[MAX_BANK]; |
0f25fda8 | 609 | |
438b6c20 | 610 | pca953x_read_regs(chip, chip->regs->direction, reg_direction); |
44896bea YL |
611 | |
612 | if (chip->driver_data & PCA_PCAL) { | |
613 | /* Enable latch on interrupt-enabled inputs */ | |
614 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
615 | ||
616 | for (i = 0; i < NBANK(chip); i++) | |
617 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
618 | ||
619 | /* Unmask enabled interrupts */ | |
620 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
621 | } | |
a2cb9aeb MZ |
622 | |
623 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
624 | for (i = 0; i < NBANK(chip); i++) { |
625 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
0f25fda8 | 626 | new_irqs &= reg_direction[i]; |
f5f0b7aa GC |
627 | |
628 | while (new_irqs) { | |
629 | level = __ffs(new_irqs); | |
630 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
631 | level + (BANK_SZ * i)); | |
632 | new_irqs &= ~(1 << level); | |
633 | } | |
a2cb9aeb | 634 | } |
89ea8bbe MZ |
635 | |
636 | mutex_unlock(&chip->irq_lock); | |
637 | } | |
638 | ||
6f5cfc0e | 639 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 640 | { |
7bcbce55 | 641 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 642 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 643 | int bank_nb = d->hwirq / BANK_SZ; |
63b484c2 | 644 | u8 mask = BIT(d->hwirq % BANK_SZ); |
89ea8bbe MZ |
645 | |
646 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
647 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 648 | d->irq, type); |
89ea8bbe MZ |
649 | return -EINVAL; |
650 | } | |
651 | ||
652 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 653 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 654 | else |
f5f0b7aa | 655 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
656 | |
657 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 658 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 659 | else |
f5f0b7aa | 660 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 661 | |
a2cb9aeb | 662 | return 0; |
89ea8bbe MZ |
663 | } |
664 | ||
0a70fe00 GD |
665 | static void pca953x_irq_shutdown(struct irq_data *d) |
666 | { | |
c378b3aa MW |
667 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
668 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
63b484c2 | 669 | u8 mask = BIT(d->hwirq % BANK_SZ); |
0a70fe00 GD |
670 | |
671 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | |
672 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | |
673 | } | |
674 | ||
b6ac1280 | 675 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 676 | { |
f5f0b7aa GC |
677 | u8 cur_stat[MAX_BANK]; |
678 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
679 | bool pending_seen = false; |
680 | bool trigger_seen = false; | |
681 | u8 trigger[MAX_BANK]; | |
bc624a06 | 682 | u8 reg_direction[MAX_BANK]; |
53661f3b | 683 | int ret, i; |
33226ffd | 684 | |
44896bea YL |
685 | if (chip->driver_data & PCA_PCAL) { |
686 | /* Read the current interrupt status from the device */ | |
687 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
688 | if (ret) | |
689 | return false; | |
690 | ||
691 | /* Check latched inputs and clear interrupt status */ | |
692 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
693 | if (ret) | |
694 | return false; | |
695 | ||
696 | for (i = 0; i < NBANK(chip); i++) { | |
697 | /* Apply filter for rising/falling edge selection */ | |
698 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
699 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
700 | pending[i] &= trigger[i]; | |
701 | if (pending[i]) | |
702 | pending_seen = true; | |
703 | } | |
704 | ||
705 | return pending_seen; | |
706 | } | |
707 | ||
53661f3b | 708 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 709 | if (ret) |
b6ac1280 | 710 | return false; |
89ea8bbe MZ |
711 | |
712 | /* Remove output pins from the equation */ | |
438b6c20 | 713 | pca953x_read_regs(chip, chip->regs->direction, reg_direction); |
f5f0b7aa | 714 | for (i = 0; i < NBANK(chip); i++) |
0f25fda8 | 715 | cur_stat[i] &= reg_direction[i]; |
89ea8bbe | 716 | |
f5f0b7aa | 717 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 718 | |
f5f0b7aa GC |
719 | for (i = 0; i < NBANK(chip); i++) { |
720 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
721 | if (trigger[i]) |
722 | trigger_seen = true; | |
f5f0b7aa GC |
723 | } |
724 | ||
b6ac1280 JS |
725 | if (!trigger_seen) |
726 | return false; | |
89ea8bbe | 727 | |
f5f0b7aa | 728 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 729 | |
f5f0b7aa GC |
730 | for (i = 0; i < NBANK(chip); i++) { |
731 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
732 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
733 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
734 | if (pending[i]) |
735 | pending_seen = true; | |
f5f0b7aa | 736 | } |
89ea8bbe | 737 | |
b6ac1280 | 738 | return pending_seen; |
89ea8bbe MZ |
739 | } |
740 | ||
741 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
742 | { | |
743 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
744 | u8 pending[MAX_BANK]; |
745 | u8 level; | |
3275d072 | 746 | unsigned nhandled = 0; |
f5f0b7aa | 747 | int i; |
89ea8bbe | 748 | |
f5f0b7aa | 749 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 750 | return IRQ_NONE; |
89ea8bbe | 751 | |
f5f0b7aa GC |
752 | for (i = 0; i < NBANK(chip); i++) { |
753 | while (pending[i]) { | |
754 | level = __ffs(pending[i]); | |
f0fbe7bc | 755 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
f5f0b7aa GC |
756 | level + (BANK_SZ * i))); |
757 | pending[i] &= ~(1 << level); | |
3275d072 | 758 | nhandled++; |
f5f0b7aa GC |
759 | } |
760 | } | |
89ea8bbe | 761 | |
3275d072 | 762 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
763 | } |
764 | ||
765 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 766 | int irq_base) |
89ea8bbe MZ |
767 | { |
768 | struct i2c_client *client = chip->client; | |
5c4fee63 | 769 | struct irq_chip *irq_chip = &chip->irq_chip; |
bc624a06 | 770 | u8 reg_direction[MAX_BANK]; |
53661f3b | 771 | int ret, i; |
89ea8bbe | 772 | |
7341fa7a TP |
773 | if (!client->irq) |
774 | return 0; | |
89ea8bbe | 775 | |
7341fa7a TP |
776 | if (irq_base == -1) |
777 | return 0; | |
89ea8bbe | 778 | |
7341fa7a TP |
779 | if (!(chip->driver_data & PCA_INT)) |
780 | return 0; | |
fdd50409 | 781 | |
7341fa7a TP |
782 | ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat); |
783 | if (ret) | |
784 | return ret; | |
785 | ||
786 | /* | |
787 | * There is no way to know which GPIO line generated the | |
788 | * interrupt. We have to rely on the previous read for | |
789 | * this purpose. | |
790 | */ | |
438b6c20 | 791 | pca953x_read_regs(chip, chip->regs->direction, reg_direction); |
7341fa7a TP |
792 | for (i = 0; i < NBANK(chip); i++) |
793 | chip->irq_stat[i] &= reg_direction[i]; | |
794 | mutex_init(&chip->irq_lock); | |
795 | ||
796 | ret = devm_request_threaded_irq(&client->dev, client->irq, | |
797 | NULL, pca953x_irq_handler, | |
798 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | | |
799 | IRQF_SHARED, | |
800 | dev_name(&client->dev), chip); | |
801 | if (ret) { | |
802 | dev_err(&client->dev, "failed to request irq %d\n", | |
803 | client->irq); | |
804 | return ret; | |
89ea8bbe MZ |
805 | } |
806 | ||
5c4fee63 TP |
807 | irq_chip->name = dev_name(&chip->client->dev); |
808 | irq_chip->irq_mask = pca953x_irq_mask; | |
809 | irq_chip->irq_unmask = pca953x_irq_unmask; | |
2a9a2f27 | 810 | irq_chip->irq_set_wake = pca953x_irq_set_wake; |
5c4fee63 TP |
811 | irq_chip->irq_bus_lock = pca953x_irq_bus_lock; |
812 | irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; | |
813 | irq_chip->irq_set_type = pca953x_irq_set_type; | |
814 | irq_chip->irq_shutdown = pca953x_irq_shutdown; | |
815 | ||
816 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip, | |
7341fa7a TP |
817 | irq_base, handle_simple_irq, |
818 | IRQ_TYPE_NONE); | |
819 | if (ret) { | |
820 | dev_err(&client->dev, | |
821 | "could not connect irqchip to gpiochip\n"); | |
822 | return ret; | |
823 | } | |
824 | ||
5c4fee63 | 825 | gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq); |
7341fa7a | 826 | |
89ea8bbe | 827 | return 0; |
89ea8bbe MZ |
828 | } |
829 | ||
89ea8bbe MZ |
830 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
831 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 832 | int irq_base) |
89ea8bbe MZ |
833 | { |
834 | struct i2c_client *client = chip->client; | |
89ea8bbe | 835 | |
72b38caf | 836 | if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
837 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
838 | ||
839 | return 0; | |
840 | } | |
89ea8bbe MZ |
841 | #endif |
842 | ||
7a04aaa3 | 843 | static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
844 | { |
845 | int ret; | |
f5f0b7aa | 846 | u8 val[MAX_BANK]; |
33226ffd | 847 | |
ec82d1eb MV |
848 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
849 | chip->regs->output + NBANK(chip)); | |
6dd6a2d2 | 850 | if (ret) |
33226ffd HZ |
851 | goto out; |
852 | ||
0f25fda8 MV |
853 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
854 | chip->regs->direction + NBANK(chip)); | |
6dd6a2d2 | 855 | if (ret) |
33226ffd HZ |
856 | goto out; |
857 | ||
858 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
859 | if (invert) |
860 | memset(val, 0xFF, NBANK(chip)); | |
861 | else | |
862 | memset(val, 0, NBANK(chip)); | |
863 | ||
7a04aaa3 | 864 | ret = pca953x_write_regs(chip, chip->regs->invert, val); |
33226ffd HZ |
865 | out: |
866 | return ret; | |
867 | } | |
868 | ||
3836309d | 869 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
870 | { |
871 | int ret; | |
f5f0b7aa | 872 | u8 val[MAX_BANK]; |
33226ffd | 873 | |
7a04aaa3 | 874 | ret = device_pca95xx_init(chip, invert); |
c75a3772 NK |
875 | if (ret) |
876 | goto out; | |
33226ffd | 877 | |
20a8a968 | 878 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 879 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
880 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
881 | if (ret) | |
882 | goto out; | |
33226ffd HZ |
883 | |
884 | return 0; | |
885 | out: | |
886 | return ret; | |
887 | } | |
888 | ||
6f29c9af BD |
889 | static const struct of_device_id pca953x_dt_ids[]; |
890 | ||
3836309d | 891 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 892 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 893 | { |
f3dc3630 GL |
894 | struct pca953x_platform_data *pdata; |
895 | struct pca953x_chip *chip; | |
6a7b36aa | 896 | int irq_base = 0; |
7ea2aa20 | 897 | int ret; |
6a7b36aa | 898 | u32 invert = 0; |
e23efa31 | 899 | struct regulator *reg; |
9e60fdcf | 900 | |
b42748c9 LW |
901 | chip = devm_kzalloc(&client->dev, |
902 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
903 | if (chip == NULL) |
904 | return -ENOMEM; | |
905 | ||
e56aee18 | 906 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
907 | if (pdata) { |
908 | irq_base = pdata->irq_base; | |
909 | chip->gpio_start = pdata->gpio_base; | |
910 | invert = pdata->invert; | |
911 | chip->names = pdata->names; | |
912 | } else { | |
054ccdef SL |
913 | struct gpio_desc *reset_gpio; |
914 | ||
4bb93349 MP |
915 | chip->gpio_start = -1; |
916 | irq_base = 0; | |
054ccdef | 917 | |
96530b37 AS |
918 | /* |
919 | * See if we need to de-assert a reset pin. | |
920 | * | |
921 | * There is no known ACPI-enabled platforms that are | |
922 | * using "reset" GPIO. Otherwise any of those platform | |
923 | * must use _DSD method with corresponding property. | |
924 | */ | |
054ccdef SL |
925 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
926 | GPIOD_OUT_LOW); | |
927 | if (IS_ERR(reset_gpio)) | |
928 | return PTR_ERR(reset_gpio); | |
1965d303 | 929 | } |
9e60fdcf | 930 | |
931 | chip->client = client; | |
932 | ||
e23efa31 PR |
933 | reg = devm_regulator_get(&client->dev, "vcc"); |
934 | if (IS_ERR(reg)) { | |
935 | ret = PTR_ERR(reg); | |
936 | if (ret != -EPROBE_DEFER) | |
937 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
938 | return ret; | |
939 | } | |
940 | ret = regulator_enable(reg); | |
941 | if (ret) { | |
942 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
943 | return ret; | |
944 | } | |
945 | chip->regulator = reg; | |
946 | ||
6212e1d6 WS |
947 | if (i2c_id) { |
948 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 949 | } else { |
8eeb467d AS |
950 | const void *match; |
951 | ||
952 | match = device_get_match_data(&client->dev); | |
953 | if (!match) { | |
954 | ret = -ENODEV; | |
955 | goto err_exit; | |
6f29c9af | 956 | } |
8eeb467d AS |
957 | |
958 | chip->driver_data = (uintptr_t)match; | |
f32517bf AS |
959 | } |
960 | ||
49427232 MV |
961 | i2c_set_clientdata(client, chip); |
962 | ||
963 | chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); | |
964 | if (IS_ERR(chip->regmap)) { | |
965 | ret = PTR_ERR(chip->regmap); | |
966 | goto err_exit; | |
967 | } | |
968 | ||
0f25fda8 MV |
969 | regcache_mark_dirty(chip->regmap); |
970 | ||
6e20fb18 | 971 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
972 | /* |
973 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
974 | * expander using the same driver higher on the device tree, read the | |
975 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
976 | * subclass for chip->i2c_lock. | |
977 | * | |
978 | * REVISIT: This solution is not complete. It protects us from lockdep | |
979 | * false positives when the expander controlling the i2c-mux is on | |
980 | * a different level on the device tree, but not when it's on the same | |
981 | * level on a different branch (in which case the subclass number | |
982 | * would be the same). | |
983 | * | |
984 | * TODO: Once a correct solution is developed, a similar fix should be | |
985 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
986 | * regmap-i2c). | |
987 | */ | |
559b4699 BG |
988 | lockdep_set_subclass(&chip->i2c_lock, |
989 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 990 | |
9e60fdcf | 991 | /* initialize cached registers from their original values. |
992 | * we can't share this chip with another i2c master. | |
993 | */ | |
c6664149 | 994 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 995 | |
7a04aaa3 MV |
996 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
997 | chip->regs = &pca953x_regs; | |
998 | ret = device_pca95xx_init(chip, invert); | |
7acc66e3 | 999 | } else { |
7a04aaa3 | 1000 | chip->regs = &pca957x_regs; |
7ea2aa20 | 1001 | ret = device_pca957x_init(chip, invert); |
7a04aaa3 | 1002 | } |
7ea2aa20 | 1003 | if (ret) |
e23efa31 | 1004 | goto err_exit; |
9e60fdcf | 1005 | |
0ece84f5 | 1006 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 1007 | if (ret) |
e23efa31 | 1008 | goto err_exit; |
f5e8ff48 | 1009 | |
c6664149 | 1010 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 1011 | if (ret) |
e23efa31 | 1012 | goto err_exit; |
9e60fdcf | 1013 | |
c6dcf592 | 1014 | if (pdata && pdata->setup) { |
9e60fdcf | 1015 | ret = pdata->setup(client, chip->gpio_chip.base, |
1016 | chip->gpio_chip.ngpio, pdata->context); | |
1017 | if (ret < 0) | |
1018 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
1019 | } | |
1020 | ||
9e60fdcf | 1021 | return 0; |
e23efa31 PR |
1022 | |
1023 | err_exit: | |
1024 | regulator_disable(chip->regulator); | |
1025 | return ret; | |
9e60fdcf | 1026 | } |
1027 | ||
f3dc3630 | 1028 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 1029 | { |
e56aee18 | 1030 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 1031 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 1032 | int ret; |
9e60fdcf | 1033 | |
c6dcf592 | 1034 | if (pdata && pdata->teardown) { |
9e60fdcf | 1035 | ret = pdata->teardown(client, chip->gpio_chip.base, |
1036 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 1037 | if (ret < 0) |
f4160faa | 1038 | dev_err(&client->dev, "teardown failed, %d\n", ret); |
bf62efeb AB |
1039 | } else { |
1040 | ret = 0; | |
9e60fdcf | 1041 | } |
1042 | ||
e23efa31 PR |
1043 | regulator_disable(chip->regulator); |
1044 | ||
1045 | return ret; | |
9e60fdcf | 1046 | } |
1047 | ||
b7657430 MV |
1048 | #ifdef CONFIG_PM_SLEEP |
1049 | static int pca953x_regcache_sync(struct device *dev) | |
1050 | { | |
1051 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1052 | int ret; | |
1053 | ||
1054 | /* | |
1055 | * The ordering between direction and output is important, | |
1056 | * sync these registers first and only then sync the rest. | |
1057 | */ | |
1058 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, | |
1059 | chip->regs->direction + NBANK(chip)); | |
6dd6a2d2 | 1060 | if (ret) { |
b7657430 MV |
1061 | dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); |
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | ret = regcache_sync_region(chip->regmap, chip->regs->output, | |
1066 | chip->regs->output + NBANK(chip)); | |
6dd6a2d2 | 1067 | if (ret) { |
b7657430 MV |
1068 | dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | #ifdef CONFIG_GPIO_PCA953X_IRQ | |
1073 | if (chip->driver_data & PCA_PCAL) { | |
1074 | ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, | |
1075 | PCAL953X_IN_LATCH + NBANK(chip)); | |
6dd6a2d2 | 1076 | if (ret) { |
b7657430 MV |
1077 | dev_err(dev, "Failed to sync INT latch registers: %d\n", |
1078 | ret); | |
1079 | return ret; | |
1080 | } | |
1081 | ||
1082 | ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, | |
1083 | PCAL953X_INT_MASK + NBANK(chip)); | |
6dd6a2d2 | 1084 | if (ret) { |
b7657430 MV |
1085 | dev_err(dev, "Failed to sync INT mask registers: %d\n", |
1086 | ret); | |
1087 | return ret; | |
1088 | } | |
1089 | } | |
1090 | #endif | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static int pca953x_suspend(struct device *dev) | |
1096 | { | |
1097 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1098 | ||
1099 | regcache_cache_only(chip->regmap, true); | |
1100 | ||
f70fbc15 GU |
1101 | if (atomic_read(&chip->wakeup_path)) |
1102 | device_set_wakeup_path(dev); | |
1103 | else | |
1104 | regulator_disable(chip->regulator); | |
b7657430 MV |
1105 | |
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static int pca953x_resume(struct device *dev) | |
1110 | { | |
1111 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1112 | int ret; | |
1113 | ||
f70fbc15 GU |
1114 | if (!atomic_read(&chip->wakeup_path)) { |
1115 | ret = regulator_enable(chip->regulator); | |
6dd6a2d2 | 1116 | if (ret) { |
f70fbc15 GU |
1117 | dev_err(dev, "Failed to enable regulator: %d\n", ret); |
1118 | return 0; | |
1119 | } | |
b7657430 MV |
1120 | } |
1121 | ||
1122 | regcache_cache_only(chip->regmap, false); | |
1123 | regcache_mark_dirty(chip->regmap); | |
1124 | ret = pca953x_regcache_sync(dev); | |
1125 | if (ret) | |
1126 | return ret; | |
1127 | ||
1128 | ret = regcache_sync(chip->regmap); | |
6dd6a2d2 | 1129 | if (ret) { |
b7657430 MV |
1130 | dev_err(dev, "Failed to restore register map: %d\n", ret); |
1131 | return ret; | |
1132 | } | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | #endif | |
1137 | ||
6f29c9af BD |
1138 | /* convenience to stop overlong match-table lines */ |
1139 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
1140 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
1141 | ||
ed32620e | 1142 | static const struct of_device_id pca953x_dt_ids[] = { |
12c7a4fc | 1143 | { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1144 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
1145 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
1146 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
1147 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
1148 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
1149 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
1150 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
1151 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
1152 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
1153 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
1154 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
1155 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
1156 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
1157 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
1158 | ||
01769c47 | 1159 | { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, |
0cdf21b3 NS |
1160 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
1161 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, | |
3a711e0d | 1162 | |
6f29c9af BD |
1163 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
1164 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
1165 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
1166 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 1167 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1168 | |
1169 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 1170 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
1171 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
1172 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
1173 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
8b74ae41 | 1174 | { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, |
6f29c9af | 1175 | |
932002f0 | 1176 | { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, |
8a64e557 | 1177 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6f29c9af BD |
1178 | |
1179 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
1180 | { } |
1181 | }; | |
1182 | ||
1183 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
1184 | ||
b7657430 MV |
1185 | static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); |
1186 | ||
f3dc3630 | 1187 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 1188 | .driver = { |
f3dc3630 | 1189 | .name = "pca953x", |
b7657430 | 1190 | .pm = &pca953x_pm_ops, |
ed32620e | 1191 | .of_match_table = pca953x_dt_ids, |
f32517bf | 1192 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 1193 | }, |
f3dc3630 GL |
1194 | .probe = pca953x_probe, |
1195 | .remove = pca953x_remove, | |
3760f736 | 1196 | .id_table = pca953x_id, |
9e60fdcf | 1197 | }; |
1198 | ||
f3dc3630 | 1199 | static int __init pca953x_init(void) |
9e60fdcf | 1200 | { |
f3dc3630 | 1201 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 1202 | } |
2f8d1197 DB |
1203 | /* register after i2c postcore initcall and before |
1204 | * subsys initcalls that may rely on these GPIOs | |
1205 | */ | |
1206 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1207 | |
f3dc3630 | 1208 | static void __exit pca953x_exit(void) |
9e60fdcf | 1209 | { |
f3dc3630 | 1210 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1211 | } |
f3dc3630 | 1212 | module_exit(pca953x_exit); |
9e60fdcf | 1213 | |
1214 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1215 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1216 | MODULE_LICENSE("GPL"); |