Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[linux-2.6-block.git] / drivers / gpio / gpio-pca953x.c
CommitLineData
9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe
MZ
17#include <linux/interrupt.h>
18#include <linux/irq.h>
55ecd263 19#include <linux/irqdomain.h>
9e60fdcf 20#include <linux/i2c.h>
5877457a 21#include <linux/platform_data/pca953x.h>
5a0e3ad6 22#include <linux/slab.h>
1965d303
NC
23#ifdef CONFIG_OF_GPIO
24#include <linux/of_platform.h>
1965d303 25#endif
9e60fdcf 26
33226ffd
HZ
27#define PCA953X_INPUT 0
28#define PCA953X_OUTPUT 1
29#define PCA953X_INVERT 2
30#define PCA953X_DIRECTION 3
31
ae79c190
AS
32#define REG_ADDR_AI 0x80
33
33226ffd
HZ
34#define PCA957X_IN 0
35#define PCA957X_INVRT 1
36#define PCA957X_BKEN 2
37#define PCA957X_PUPD 3
38#define PCA957X_CFG 4
39#define PCA957X_OUT 5
40#define PCA957X_MSK 6
41#define PCA957X_INTS 7
42
43#define PCA_GPIO_MASK 0x00FF
44#define PCA_INT 0x0100
45#define PCA953X_TYPE 0x1000
46#define PCA957X_TYPE 0x2000
89ea8bbe 47
3760f736 48static const struct i2c_device_id pca953x_id[] = {
89f5df01 49 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
50 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
51 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
52 { "pca9536", 4 | PCA953X_TYPE, },
53 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
54 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
55 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
56 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
57 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
58 { "pca9556", 8 | PCA953X_TYPE, },
59 { "pca9557", 8 | PCA953X_TYPE, },
60 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
61 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 62 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd
HZ
63
64 { "max7310", 8 | PCA953X_TYPE, },
65 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
66 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
67 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
68 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
69 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
70 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 71 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
e73760a6 72 { "xra1202", 8 | PCA953X_TYPE },
3760f736 73 { }
f5e8ff48 74};
3760f736 75MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 76
f5f0b7aa
GC
77#define MAX_BANK 5
78#define BANK_SZ 8
79
80#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
81
f3dc3630 82struct pca953x_chip {
9e60fdcf 83 unsigned gpio_start;
f5f0b7aa
GC
84 u8 reg_output[MAX_BANK];
85 u8 reg_direction[MAX_BANK];
6e20fb18 86 struct mutex i2c_lock;
9e60fdcf 87
89ea8bbe
MZ
88#ifdef CONFIG_GPIO_PCA953X_IRQ
89 struct mutex irq_lock;
f5f0b7aa
GC
90 u8 irq_mask[MAX_BANK];
91 u8 irq_stat[MAX_BANK];
92 u8 irq_trig_raise[MAX_BANK];
93 u8 irq_trig_fall[MAX_BANK];
55ecd263 94 struct irq_domain *domain;
89ea8bbe
MZ
95#endif
96
9e60fdcf 97 struct i2c_client *client;
98 struct gpio_chip gpio_chip;
62154991 99 const char *const *names;
33226ffd 100 int chip_type;
9e60fdcf 101};
102
f5f0b7aa
GC
103static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
104 int off)
105{
106 int ret;
107 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
108 int offset = off / BANK_SZ;
109
110 ret = i2c_smbus_read_byte_data(chip->client,
111 (reg << bank_shift) + offset);
112 *val = ret;
113
114 if (ret < 0) {
115 dev_err(&chip->client->dev, "failed reading register\n");
116 return ret;
117 }
118
119 return 0;
120}
121
122static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
123 int off)
124{
125 int ret = 0;
126 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
127 int offset = off / BANK_SZ;
128
129 ret = i2c_smbus_write_byte_data(chip->client,
130 (reg << bank_shift) + offset, val);
131
132 if (ret < 0) {
133 dev_err(&chip->client->dev, "failed writing register\n");
134 return ret;
135 }
136
137 return 0;
138}
139
140static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 141{
33226ffd 142 int ret = 0;
f5e8ff48
GL
143
144 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
145 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
146 else if (chip->gpio_chip.ngpio >= 24) {
147 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 148 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
149 (reg << bank_shift) | REG_ADDR_AI,
150 NBANK(chip), val);
50e44430 151 } else {
33226ffd
HZ
152 switch (chip->chip_type) {
153 case PCA953X_TYPE:
154 ret = i2c_smbus_write_word_data(chip->client,
f5f0b7aa 155 reg << 1, (u16) *val);
33226ffd
HZ
156 break;
157 case PCA957X_TYPE:
158 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 159 val[0]);
33226ffd
HZ
160 if (ret < 0)
161 break;
162 ret = i2c_smbus_write_byte_data(chip->client,
163 (reg << 1) + 1,
f5f0b7aa 164 val[1]);
33226ffd
HZ
165 break;
166 }
167 }
f5e8ff48
GL
168
169 if (ret < 0) {
170 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 171 return ret;
f5e8ff48
GL
172 }
173
174 return 0;
9e60fdcf 175}
176
f5f0b7aa 177static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 178{
179 int ret;
180
96b70641 181 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 182 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 183 *val = ret;
f5f0b7aa
GC
184 } else if (chip->gpio_chip.ngpio >= 24) {
185 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
186
96b70641 187 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
188 (reg << bank_shift) | REG_ADDR_AI,
189 NBANK(chip), val);
96b70641 190 } else {
f5e8ff48 191 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
192 val[0] = (u16)ret & 0xFF;
193 val[1] = (u16)ret >> 8;
96b70641 194 }
9e60fdcf 195 if (ret < 0) {
196 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 197 return ret;
9e60fdcf 198 }
199
9e60fdcf 200 return 0;
201}
202
f3dc3630 203static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 204{
f3dc3630 205 struct pca953x_chip *chip;
f5f0b7aa 206 u8 reg_val;
33226ffd 207 int ret, offset = 0;
9e60fdcf 208
f3dc3630 209 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 210
6e20fb18 211 mutex_lock(&chip->i2c_lock);
f5f0b7aa 212 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
213
214 switch (chip->chip_type) {
215 case PCA953X_TYPE:
216 offset = PCA953X_DIRECTION;
217 break;
218 case PCA957X_TYPE:
219 offset = PCA957X_CFG;
220 break;
221 }
f5f0b7aa 222 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 223 if (ret)
6e20fb18 224 goto exit;
9e60fdcf 225
f5f0b7aa 226 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
227 ret = 0;
228exit:
229 mutex_unlock(&chip->i2c_lock);
230 return ret;
9e60fdcf 231}
232
f3dc3630 233static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 234 unsigned off, int val)
235{
f3dc3630 236 struct pca953x_chip *chip;
f5f0b7aa 237 u8 reg_val;
33226ffd 238 int ret, offset = 0;
9e60fdcf 239
f3dc3630 240 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 241
6e20fb18 242 mutex_lock(&chip->i2c_lock);
9e60fdcf 243 /* set output level */
244 if (val)
f5f0b7aa
GC
245 reg_val = chip->reg_output[off / BANK_SZ]
246 | (1u << (off % BANK_SZ));
9e60fdcf 247 else
f5f0b7aa
GC
248 reg_val = chip->reg_output[off / BANK_SZ]
249 & ~(1u << (off % BANK_SZ));
9e60fdcf 250
33226ffd
HZ
251 switch (chip->chip_type) {
252 case PCA953X_TYPE:
253 offset = PCA953X_OUTPUT;
254 break;
255 case PCA957X_TYPE:
256 offset = PCA957X_OUT;
257 break;
258 }
f5f0b7aa 259 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 260 if (ret)
6e20fb18 261 goto exit;
9e60fdcf 262
f5f0b7aa 263 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 264
265 /* then direction */
f5f0b7aa 266 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
267 switch (chip->chip_type) {
268 case PCA953X_TYPE:
269 offset = PCA953X_DIRECTION;
270 break;
271 case PCA957X_TYPE:
272 offset = PCA957X_CFG;
273 break;
274 }
f5f0b7aa 275 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 276 if (ret)
6e20fb18 277 goto exit;
9e60fdcf 278
f5f0b7aa 279 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
280 ret = 0;
281exit:
282 mutex_unlock(&chip->i2c_lock);
283 return ret;
9e60fdcf 284}
285
f3dc3630 286static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 287{
f3dc3630 288 struct pca953x_chip *chip;
ae79c190 289 u32 reg_val;
33226ffd 290 int ret, offset = 0;
9e60fdcf 291
f3dc3630 292 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 293
6e20fb18 294 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
295 switch (chip->chip_type) {
296 case PCA953X_TYPE:
297 offset = PCA953X_INPUT;
298 break;
299 case PCA957X_TYPE:
300 offset = PCA957X_IN;
301 break;
302 }
f5f0b7aa 303 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 304 mutex_unlock(&chip->i2c_lock);
9e60fdcf 305 if (ret < 0) {
306 /* NOTE: diagnostic already emitted; that's all we should
307 * do unless gpio_*_value_cansleep() calls become different
308 * from their nonsleeping siblings (and report faults).
309 */
310 return 0;
311 }
312
40a625da 313 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 314}
315
f3dc3630 316static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 317{
f3dc3630 318 struct pca953x_chip *chip;
f5f0b7aa 319 u8 reg_val;
33226ffd 320 int ret, offset = 0;
9e60fdcf 321
f3dc3630 322 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 323
6e20fb18 324 mutex_lock(&chip->i2c_lock);
9e60fdcf 325 if (val)
f5f0b7aa
GC
326 reg_val = chip->reg_output[off / BANK_SZ]
327 | (1u << (off % BANK_SZ));
9e60fdcf 328 else
f5f0b7aa
GC
329 reg_val = chip->reg_output[off / BANK_SZ]
330 & ~(1u << (off % BANK_SZ));
9e60fdcf 331
33226ffd
HZ
332 switch (chip->chip_type) {
333 case PCA953X_TYPE:
334 offset = PCA953X_OUTPUT;
335 break;
336 case PCA957X_TYPE:
337 offset = PCA957X_OUT;
338 break;
339 }
f5f0b7aa 340 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 341 if (ret)
6e20fb18 342 goto exit;
9e60fdcf 343
f5f0b7aa 344 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
345exit:
346 mutex_unlock(&chip->i2c_lock);
9e60fdcf 347}
348
f5e8ff48 349static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 350{
351 struct gpio_chip *gc;
352
353 gc = &chip->gpio_chip;
354
f3dc3630
GL
355 gc->direction_input = pca953x_gpio_direction_input;
356 gc->direction_output = pca953x_gpio_direction_output;
357 gc->get = pca953x_gpio_get_value;
358 gc->set = pca953x_gpio_set_value;
9fb1f39e 359 gc->can_sleep = true;
9e60fdcf 360
361 gc->base = chip->gpio_start;
f5e8ff48
GL
362 gc->ngpio = gpios;
363 gc->label = chip->client->name;
d8f388d8 364 gc->dev = &chip->client->dev;
d72cbed0 365 gc->owner = THIS_MODULE;
77906a54 366 gc->names = chip->names;
9e60fdcf 367}
368
89ea8bbe
MZ
369#ifdef CONFIG_GPIO_PCA953X_IRQ
370static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
371{
372 struct pca953x_chip *chip;
373
374 chip = container_of(gc, struct pca953x_chip, gpio_chip);
0e8f2fda 375 return irq_create_mapping(chip->domain, off);
89ea8bbe
MZ
376}
377
6f5cfc0e 378static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 379{
6f5cfc0e 380 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
89ea8bbe 381
f5f0b7aa 382 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
383}
384
6f5cfc0e 385static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 386{
6f5cfc0e 387 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
89ea8bbe 388
f5f0b7aa 389 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
390}
391
6f5cfc0e 392static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 393{
6f5cfc0e 394 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
89ea8bbe
MZ
395
396 mutex_lock(&chip->irq_lock);
397}
398
6f5cfc0e 399static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 400{
6f5cfc0e 401 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
f5f0b7aa
GC
402 u8 new_irqs;
403 int level, i;
a2cb9aeb
MZ
404
405 /* Look for any newly setup interrupt */
f5f0b7aa
GC
406 for (i = 0; i < NBANK(chip); i++) {
407 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
408 new_irqs &= ~chip->reg_direction[i];
409
410 while (new_irqs) {
411 level = __ffs(new_irqs);
412 pca953x_gpio_direction_input(&chip->gpio_chip,
413 level + (BANK_SZ * i));
414 new_irqs &= ~(1 << level);
415 }
a2cb9aeb 416 }
89ea8bbe
MZ
417
418 mutex_unlock(&chip->irq_lock);
419}
420
6f5cfc0e 421static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 422{
6f5cfc0e 423 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
f5f0b7aa
GC
424 int bank_nb = d->hwirq / BANK_SZ;
425 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
426
427 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
428 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 429 d->irq, type);
89ea8bbe
MZ
430 return -EINVAL;
431 }
432
433 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 434 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 435 else
f5f0b7aa 436 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
437
438 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 439 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 440 else
f5f0b7aa 441 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 442
a2cb9aeb 443 return 0;
89ea8bbe
MZ
444}
445
446static struct irq_chip pca953x_irq_chip = {
447 .name = "pca953x",
6f5cfc0e
LB
448 .irq_mask = pca953x_irq_mask,
449 .irq_unmask = pca953x_irq_unmask,
450 .irq_bus_lock = pca953x_irq_bus_lock,
451 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
452 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
453};
454
f5f0b7aa 455static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 456{
f5f0b7aa
GC
457 u8 cur_stat[MAX_BANK];
458 u8 old_stat[MAX_BANK];
459 u8 pendings = 0;
460 u8 trigger[MAX_BANK], triggers = 0;
461 int ret, i, offset = 0;
33226ffd
HZ
462
463 switch (chip->chip_type) {
464 case PCA953X_TYPE:
465 offset = PCA953X_INPUT;
466 break;
467 case PCA957X_TYPE:
468 offset = PCA957X_IN;
469 break;
470 }
f5f0b7aa 471 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe
MZ
472 if (ret)
473 return 0;
474
475 /* Remove output pins from the equation */
f5f0b7aa
GC
476 for (i = 0; i < NBANK(chip); i++)
477 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 478
f5f0b7aa 479 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 480
f5f0b7aa
GC
481 for (i = 0; i < NBANK(chip); i++) {
482 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
483 triggers += trigger[i];
484 }
485
486 if (!triggers)
89ea8bbe
MZ
487 return 0;
488
f5f0b7aa 489 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 490
f5f0b7aa
GC
491 for (i = 0; i < NBANK(chip); i++) {
492 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
493 (cur_stat[i] & chip->irq_trig_raise[i]);
494 pending[i] &= trigger[i];
495 pendings += pending[i];
496 }
89ea8bbe 497
f5f0b7aa 498 return pendings;
89ea8bbe
MZ
499}
500
501static irqreturn_t pca953x_irq_handler(int irq, void *devid)
502{
503 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
504 u8 pending[MAX_BANK];
505 u8 level;
506 int i;
89ea8bbe 507
f5f0b7aa 508 if (!pca953x_irq_pending(chip, pending))
89ea8bbe
MZ
509 return IRQ_HANDLED;
510
f5f0b7aa
GC
511 for (i = 0; i < NBANK(chip); i++) {
512 while (pending[i]) {
513 level = __ffs(pending[i]);
514 handle_nested_irq(irq_find_mapping(chip->domain,
515 level + (BANK_SZ * i)));
516 pending[i] &= ~(1 << level);
517 }
518 }
89ea8bbe
MZ
519
520 return IRQ_HANDLED;
521}
522
0e8f2fda
GC
523static int pca953x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
524 irq_hw_number_t hwirq)
525{
526 irq_clear_status_flags(irq, IRQ_NOREQUEST);
527 irq_set_chip_data(irq, d->host_data);
528 irq_set_chip(irq, &pca953x_irq_chip);
529 irq_set_nested_thread(irq, true);
530#ifdef CONFIG_ARM
531 set_irq_flags(irq, IRQF_VALID);
532#else
533 irq_set_noprobe(irq);
534#endif
535
536 return 0;
537}
538
539static const struct irq_domain_ops pca953x_irq_simple_ops = {
540 .map = pca953x_gpio_irq_map,
541 .xlate = irq_domain_xlate_twocell,
542};
543
89ea8bbe 544static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
545 const struct i2c_device_id *id,
546 int irq_base)
89ea8bbe
MZ
547{
548 struct i2c_client *client = chip->client;
f5f0b7aa 549 int ret, i, offset = 0;
89ea8bbe 550
c6dcf592 551 if (irq_base != -1
33226ffd 552 && (id->driver_data & PCA_INT)) {
89ea8bbe 553
33226ffd
HZ
554 switch (chip->chip_type) {
555 case PCA953X_TYPE:
556 offset = PCA953X_INPUT;
557 break;
558 case PCA957X_TYPE:
559 offset = PCA957X_IN;
560 break;
561 }
f5f0b7aa 562 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 563 if (ret)
b42748c9 564 return ret;
89ea8bbe
MZ
565
566 /*
567 * There is no way to know which GPIO line generated the
568 * interrupt. We have to rely on the previous read for
569 * this purpose.
570 */
f5f0b7aa
GC
571 for (i = 0; i < NBANK(chip); i++)
572 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
573 mutex_init(&chip->irq_lock);
574
0e8f2fda 575 chip->domain = irq_domain_add_simple(client->dev.of_node,
55ecd263 576 chip->gpio_chip.ngpio,
0e8f2fda
GC
577 irq_base,
578 &pca953x_irq_simple_ops,
e7a7f972 579 chip);
0e8f2fda
GC
580 if (!chip->domain)
581 return -ENODEV;
89ea8bbe 582
b42748c9
LW
583 ret = devm_request_threaded_irq(&client->dev,
584 client->irq,
89ea8bbe
MZ
585 NULL,
586 pca953x_irq_handler,
17e8b42c 587 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
89ea8bbe
MZ
588 dev_name(&client->dev), chip);
589 if (ret) {
590 dev_err(&client->dev, "failed to request irq %d\n",
591 client->irq);
0e8f2fda 592 return ret;
89ea8bbe
MZ
593 }
594
595 chip->gpio_chip.to_irq = pca953x_gpio_to_irq;
596 }
597
598 return 0;
89ea8bbe
MZ
599}
600
89ea8bbe
MZ
601#else /* CONFIG_GPIO_PCA953X_IRQ */
602static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
603 const struct i2c_device_id *id,
604 int irq_base)
89ea8bbe
MZ
605{
606 struct i2c_client *client = chip->client;
89ea8bbe 607
c6dcf592 608 if (irq_base != -1 && (id->driver_data & PCA_INT))
89ea8bbe
MZ
609 dev_warn(&client->dev, "interrupt support not compiled in\n");
610
611 return 0;
612}
89ea8bbe
MZ
613#endif
614
1965d303
NC
615/*
616 * Handlers for alternative sources of platform_data
617 */
618#ifdef CONFIG_OF_GPIO
619/*
620 * Translate OpenFirmware node properties into platform_data
a57339b4 621 * WARNING: This is DEPRECATED and will be removed eventually!
1965d303 622 */
404ba2b8 623static void
6a7b36aa 624pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
1965d303 625{
1965d303 626 struct device_node *node;
1648237d
DE
627 const __be32 *val;
628 int size;
1965d303 629
2b1f597f
AS
630 *gpio_base = -1;
631
61c7a080 632 node = client->dev.of_node;
1965d303 633 if (node == NULL)
c6dcf592 634 return;
1965d303 635
1648237d 636 val = of_get_property(node, "linux,gpio-base", &size);
a57339b4 637 WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
1965d303 638 if (val) {
1648237d
DE
639 if (size != sizeof(*val))
640 dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
641 node->full_name);
1965d303 642 else
c6dcf592 643 *gpio_base = be32_to_cpup(val);
1965d303
NC
644 }
645
646 val = of_get_property(node, "polarity", NULL);
a57339b4 647 WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__);
1965d303 648 if (val)
c6dcf592 649 *invert = *val;
1965d303
NC
650}
651#else
404ba2b8 652static void
6a7b36aa 653pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
1965d303 654{
25fcf2b7 655 *gpio_base = -1;
1965d303
NC
656}
657#endif
658
3836309d 659static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
660{
661 int ret;
f5f0b7aa 662 u8 val[MAX_BANK];
33226ffd 663
f5f0b7aa 664 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
665 if (ret)
666 goto out;
667
f5f0b7aa
GC
668 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
669 chip->reg_direction);
33226ffd
HZ
670 if (ret)
671 goto out;
672
673 /* set platform specific polarity inversion */
f5f0b7aa
GC
674 if (invert)
675 memset(val, 0xFF, NBANK(chip));
676 else
677 memset(val, 0, NBANK(chip));
678
679 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
680out:
681 return ret;
682}
683
3836309d 684static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
685{
686 int ret;
f5f0b7aa 687 u8 val[MAX_BANK];
33226ffd 688
f5f0b7aa 689 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
690 if (ret)
691 goto out;
f5f0b7aa 692 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
693 if (ret)
694 goto out;
695
696 /* set platform specific polarity inversion */
f5f0b7aa
GC
697 if (invert)
698 memset(val, 0xFF, NBANK(chip));
699 else
700 memset(val, 0, NBANK(chip));
701 pca953x_write_regs(chip, PCA957X_INVRT, val);
33226ffd
HZ
702
703 /* To enable register 6, 7 to controll pull up and pull down */
f5f0b7aa
GC
704 memset(val, 0x02, NBANK(chip));
705 pca953x_write_regs(chip, PCA957X_BKEN, val);
33226ffd
HZ
706
707 return 0;
708out:
709 return ret;
710}
711
3836309d 712static int pca953x_probe(struct i2c_client *client,
3760f736 713 const struct i2c_device_id *id)
9e60fdcf 714{
f3dc3630
GL
715 struct pca953x_platform_data *pdata;
716 struct pca953x_chip *chip;
6a7b36aa 717 int irq_base = 0;
7ea2aa20 718 int ret;
6a7b36aa 719 u32 invert = 0;
9e60fdcf 720
b42748c9
LW
721 chip = devm_kzalloc(&client->dev,
722 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
723 if (chip == NULL)
724 return -ENOMEM;
725
e56aee18 726 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
727 if (pdata) {
728 irq_base = pdata->irq_base;
729 chip->gpio_start = pdata->gpio_base;
730 invert = pdata->invert;
731 chip->names = pdata->names;
732 } else {
733 pca953x_get_alt_pdata(client, &chip->gpio_start, &invert);
a57339b4
DJ
734#ifdef CONFIG_OF_GPIO
735 /* If I2C node has no interrupts property, disable GPIO interrupts */
736 if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL)
737 irq_base = -1;
738#endif
1965d303 739 }
9e60fdcf 740
741 chip->client = client;
742
33226ffd 743 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
77906a54 744
6e20fb18
RS
745 mutex_init(&chip->i2c_lock);
746
9e60fdcf 747 /* initialize cached registers from their original values.
748 * we can't share this chip with another i2c master.
749 */
33226ffd 750 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
f5e8ff48 751
33226ffd 752 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 753 ret = device_pca953x_init(chip, invert);
33226ffd 754 else
7ea2aa20
WS
755 ret = device_pca957x_init(chip, invert);
756 if (ret)
b42748c9 757 return ret;
9e60fdcf 758
c6dcf592 759 ret = pca953x_irq_setup(chip, id, irq_base);
89ea8bbe 760 if (ret)
b42748c9 761 return ret;
f5e8ff48
GL
762
763 ret = gpiochip_add(&chip->gpio_chip);
9e60fdcf 764 if (ret)
b42748c9 765 return ret;
9e60fdcf 766
c6dcf592 767 if (pdata && pdata->setup) {
9e60fdcf 768 ret = pdata->setup(client, chip->gpio_chip.base,
769 chip->gpio_chip.ngpio, pdata->context);
770 if (ret < 0)
771 dev_warn(&client->dev, "setup failed, %d\n", ret);
772 }
773
774 i2c_set_clientdata(client, chip);
775 return 0;
9e60fdcf 776}
777
f3dc3630 778static int pca953x_remove(struct i2c_client *client)
9e60fdcf 779{
e56aee18 780 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 781 struct pca953x_chip *chip = i2c_get_clientdata(client);
9e60fdcf 782 int ret = 0;
783
c6dcf592 784 if (pdata && pdata->teardown) {
9e60fdcf 785 ret = pdata->teardown(client, chip->gpio_chip.base,
786 chip->gpio_chip.ngpio, pdata->context);
787 if (ret < 0) {
788 dev_err(&client->dev, "%s failed, %d\n",
789 "teardown", ret);
790 return ret;
791 }
792 }
793
794 ret = gpiochip_remove(&chip->gpio_chip);
795 if (ret) {
796 dev_err(&client->dev, "%s failed, %d\n",
797 "gpiochip_remove()", ret);
798 return ret;
799 }
800
9e60fdcf 801 return 0;
802}
803
ed32620e 804static const struct of_device_id pca953x_dt_ids[] = {
89f5df01 805 { .compatible = "nxp,pca9505", },
ed32620e
MR
806 { .compatible = "nxp,pca9534", },
807 { .compatible = "nxp,pca9535", },
808 { .compatible = "nxp,pca9536", },
809 { .compatible = "nxp,pca9537", },
810 { .compatible = "nxp,pca9538", },
811 { .compatible = "nxp,pca9539", },
812 { .compatible = "nxp,pca9554", },
813 { .compatible = "nxp,pca9555", },
814 { .compatible = "nxp,pca9556", },
815 { .compatible = "nxp,pca9557", },
816 { .compatible = "nxp,pca9574", },
817 { .compatible = "nxp,pca9575", },
eb32b5aa 818 { .compatible = "nxp,pca9698", },
ed32620e
MR
819
820 { .compatible = "maxim,max7310", },
821 { .compatible = "maxim,max7312", },
822 { .compatible = "maxim,max7313", },
823 { .compatible = "maxim,max7315", },
824
825 { .compatible = "ti,pca6107", },
826 { .compatible = "ti,tca6408", },
827 { .compatible = "ti,tca6416", },
828 { .compatible = "ti,tca6424", },
e73760a6
AS
829
830 { .compatible = "exar,xra1202", },
ed32620e
MR
831 { }
832};
833
834MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
835
f3dc3630 836static struct i2c_driver pca953x_driver = {
9e60fdcf 837 .driver = {
f3dc3630 838 .name = "pca953x",
ed32620e 839 .of_match_table = pca953x_dt_ids,
9e60fdcf 840 },
f3dc3630
GL
841 .probe = pca953x_probe,
842 .remove = pca953x_remove,
3760f736 843 .id_table = pca953x_id,
9e60fdcf 844};
845
f3dc3630 846static int __init pca953x_init(void)
9e60fdcf 847{
f3dc3630 848 return i2c_add_driver(&pca953x_driver);
9e60fdcf 849}
2f8d1197
DB
850/* register after i2c postcore initcall and before
851 * subsys initcalls that may rely on these GPIOs
852 */
853subsys_initcall(pca953x_init);
9e60fdcf 854
f3dc3630 855static void __exit pca953x_exit(void)
9e60fdcf 856{
f3dc3630 857 i2c_del_driver(&pca953x_driver);
9e60fdcf 858}
f3dc3630 859module_exit(pca953x_exit);
9e60fdcf 860
861MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 862MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 863MODULE_LICENSE("GPL");