Merge tag 'renesas-fixes-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpio / gpio-pca953x.c
CommitLineData
9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe 17#include <linux/interrupt.h>
9e60fdcf 18#include <linux/i2c.h>
5877457a 19#include <linux/platform_data/pca953x.h>
5a0e3ad6 20#include <linux/slab.h>
1965d303 21#include <linux/of_platform.h>
f32517bf 22#include <linux/acpi.h>
9e60fdcf 23
33226ffd
HZ
24#define PCA953X_INPUT 0
25#define PCA953X_OUTPUT 1
26#define PCA953X_INVERT 2
27#define PCA953X_DIRECTION 3
28
ae79c190
AS
29#define REG_ADDR_AI 0x80
30
33226ffd
HZ
31#define PCA957X_IN 0
32#define PCA957X_INVRT 1
33#define PCA957X_BKEN 2
34#define PCA957X_PUPD 3
35#define PCA957X_CFG 4
36#define PCA957X_OUT 5
37#define PCA957X_MSK 6
38#define PCA957X_INTS 7
39
40#define PCA_GPIO_MASK 0x00FF
41#define PCA_INT 0x0100
42#define PCA953X_TYPE 0x1000
43#define PCA957X_TYPE 0x2000
c6664149
AS
44#define PCA_TYPE_MASK 0xF000
45
46#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
89ea8bbe 47
3760f736 48static const struct i2c_device_id pca953x_id[] = {
89f5df01 49 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
50 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
51 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
52 { "pca9536", 4 | PCA953X_TYPE, },
53 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
54 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
55 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
56 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
57 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
58 { "pca9556", 8 | PCA953X_TYPE, },
59 { "pca9557", 8 | PCA953X_TYPE, },
60 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
61 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 62 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd
HZ
63
64 { "max7310", 8 | PCA953X_TYPE, },
65 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
66 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
67 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
68 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
69 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
70 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 71 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 72 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
e73760a6 73 { "xra1202", 8 | PCA953X_TYPE },
3760f736 74 { }
f5e8ff48 75};
3760f736 76MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 77
f32517bf
AS
78static const struct acpi_device_id pca953x_acpi_ids[] = {
79 { "INT3491", 16 | PCA953X_TYPE | PCA_INT, },
80 { }
81};
82MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
83
f5f0b7aa
GC
84#define MAX_BANK 5
85#define BANK_SZ 8
86
87#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
88
f3dc3630 89struct pca953x_chip {
9e60fdcf 90 unsigned gpio_start;
f5f0b7aa
GC
91 u8 reg_output[MAX_BANK];
92 u8 reg_direction[MAX_BANK];
6e20fb18 93 struct mutex i2c_lock;
9e60fdcf 94
89ea8bbe
MZ
95#ifdef CONFIG_GPIO_PCA953X_IRQ
96 struct mutex irq_lock;
f5f0b7aa
GC
97 u8 irq_mask[MAX_BANK];
98 u8 irq_stat[MAX_BANK];
99 u8 irq_trig_raise[MAX_BANK];
100 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
101#endif
102
9e60fdcf 103 struct i2c_client *client;
104 struct gpio_chip gpio_chip;
62154991 105 const char *const *names;
33226ffd 106 int chip_type;
c6664149 107 unsigned long driver_data;
9e60fdcf 108};
109
f5f0b7aa
GC
110static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
111 int off)
112{
113 int ret;
114 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
115 int offset = off / BANK_SZ;
116
117 ret = i2c_smbus_read_byte_data(chip->client,
118 (reg << bank_shift) + offset);
119 *val = ret;
120
121 if (ret < 0) {
122 dev_err(&chip->client->dev, "failed reading register\n");
123 return ret;
124 }
125
126 return 0;
127}
128
129static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
130 int off)
131{
132 int ret = 0;
133 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
134 int offset = off / BANK_SZ;
135
136 ret = i2c_smbus_write_byte_data(chip->client,
137 (reg << bank_shift) + offset, val);
138
139 if (ret < 0) {
140 dev_err(&chip->client->dev, "failed writing register\n");
141 return ret;
142 }
143
144 return 0;
145}
146
147static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 148{
33226ffd 149 int ret = 0;
f5e8ff48
GL
150
151 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
152 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
153 else if (chip->gpio_chip.ngpio >= 24) {
154 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 155 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
156 (reg << bank_shift) | REG_ADDR_AI,
157 NBANK(chip), val);
50e44430 158 } else {
33226ffd
HZ
159 switch (chip->chip_type) {
160 case PCA953X_TYPE:
161 ret = i2c_smbus_write_word_data(chip->client,
f5f0b7aa 162 reg << 1, (u16) *val);
33226ffd
HZ
163 break;
164 case PCA957X_TYPE:
165 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 166 val[0]);
33226ffd
HZ
167 if (ret < 0)
168 break;
169 ret = i2c_smbus_write_byte_data(chip->client,
170 (reg << 1) + 1,
f5f0b7aa 171 val[1]);
33226ffd
HZ
172 break;
173 }
174 }
f5e8ff48
GL
175
176 if (ret < 0) {
177 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 178 return ret;
f5e8ff48
GL
179 }
180
181 return 0;
9e60fdcf 182}
183
f5f0b7aa 184static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 185{
186 int ret;
187
96b70641 188 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 189 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 190 *val = ret;
f5f0b7aa
GC
191 } else if (chip->gpio_chip.ngpio >= 24) {
192 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
193
96b70641 194 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
195 (reg << bank_shift) | REG_ADDR_AI,
196 NBANK(chip), val);
96b70641 197 } else {
f5e8ff48 198 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
199 val[0] = (u16)ret & 0xFF;
200 val[1] = (u16)ret >> 8;
96b70641 201 }
9e60fdcf 202 if (ret < 0) {
203 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 204 return ret;
9e60fdcf 205 }
206
9e60fdcf 207 return 0;
208}
209
f3dc3630 210static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 211{
468e67f6 212 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 213 u8 reg_val;
33226ffd 214 int ret, offset = 0;
9e60fdcf 215
6e20fb18 216 mutex_lock(&chip->i2c_lock);
f5f0b7aa 217 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
218
219 switch (chip->chip_type) {
220 case PCA953X_TYPE:
221 offset = PCA953X_DIRECTION;
222 break;
223 case PCA957X_TYPE:
224 offset = PCA957X_CFG;
225 break;
226 }
f5f0b7aa 227 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 228 if (ret)
6e20fb18 229 goto exit;
9e60fdcf 230
f5f0b7aa 231 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
232 ret = 0;
233exit:
234 mutex_unlock(&chip->i2c_lock);
235 return ret;
9e60fdcf 236}
237
f3dc3630 238static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 239 unsigned off, int val)
240{
468e67f6 241 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 242 u8 reg_val;
33226ffd 243 int ret, offset = 0;
9e60fdcf 244
6e20fb18 245 mutex_lock(&chip->i2c_lock);
9e60fdcf 246 /* set output level */
247 if (val)
f5f0b7aa
GC
248 reg_val = chip->reg_output[off / BANK_SZ]
249 | (1u << (off % BANK_SZ));
9e60fdcf 250 else
f5f0b7aa
GC
251 reg_val = chip->reg_output[off / BANK_SZ]
252 & ~(1u << (off % BANK_SZ));
9e60fdcf 253
33226ffd
HZ
254 switch (chip->chip_type) {
255 case PCA953X_TYPE:
256 offset = PCA953X_OUTPUT;
257 break;
258 case PCA957X_TYPE:
259 offset = PCA957X_OUT;
260 break;
261 }
f5f0b7aa 262 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 263 if (ret)
6e20fb18 264 goto exit;
9e60fdcf 265
f5f0b7aa 266 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 267
268 /* then direction */
f5f0b7aa 269 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
270 switch (chip->chip_type) {
271 case PCA953X_TYPE:
272 offset = PCA953X_DIRECTION;
273 break;
274 case PCA957X_TYPE:
275 offset = PCA957X_CFG;
276 break;
277 }
f5f0b7aa 278 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 279 if (ret)
6e20fb18 280 goto exit;
9e60fdcf 281
f5f0b7aa 282 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
283 ret = 0;
284exit:
285 mutex_unlock(&chip->i2c_lock);
286 return ret;
9e60fdcf 287}
288
f3dc3630 289static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 290{
468e67f6 291 struct pca953x_chip *chip = gpiochip_get_data(gc);
ae79c190 292 u32 reg_val;
33226ffd 293 int ret, offset = 0;
9e60fdcf 294
6e20fb18 295 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
296 switch (chip->chip_type) {
297 case PCA953X_TYPE:
298 offset = PCA953X_INPUT;
299 break;
300 case PCA957X_TYPE:
301 offset = PCA957X_IN;
302 break;
303 }
f5f0b7aa 304 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 305 mutex_unlock(&chip->i2c_lock);
9e60fdcf 306 if (ret < 0) {
307 /* NOTE: diagnostic already emitted; that's all we should
308 * do unless gpio_*_value_cansleep() calls become different
309 * from their nonsleeping siblings (and report faults).
310 */
311 return 0;
312 }
313
40a625da 314 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 315}
316
f3dc3630 317static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 318{
468e67f6 319 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 320 u8 reg_val;
33226ffd 321 int ret, offset = 0;
9e60fdcf 322
6e20fb18 323 mutex_lock(&chip->i2c_lock);
9e60fdcf 324 if (val)
f5f0b7aa
GC
325 reg_val = chip->reg_output[off / BANK_SZ]
326 | (1u << (off % BANK_SZ));
9e60fdcf 327 else
f5f0b7aa
GC
328 reg_val = chip->reg_output[off / BANK_SZ]
329 & ~(1u << (off % BANK_SZ));
9e60fdcf 330
33226ffd
HZ
331 switch (chip->chip_type) {
332 case PCA953X_TYPE:
333 offset = PCA953X_OUTPUT;
334 break;
335 case PCA957X_TYPE:
336 offset = PCA957X_OUT;
337 break;
338 }
f5f0b7aa 339 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 340 if (ret)
6e20fb18 341 goto exit;
9e60fdcf 342
f5f0b7aa 343 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
344exit:
345 mutex_unlock(&chip->i2c_lock);
9e60fdcf 346}
347
b4818afe
PR
348
349static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
350 unsigned long *mask, unsigned long *bits)
351{
468e67f6 352 struct pca953x_chip *chip = gpiochip_get_data(gc);
b4818afe
PR
353 u8 reg_val[MAX_BANK];
354 int ret, offset = 0;
355 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
356 int bank;
357
358 switch (chip->chip_type) {
359 case PCA953X_TYPE:
360 offset = PCA953X_OUTPUT;
361 break;
362 case PCA957X_TYPE:
363 offset = PCA957X_OUT;
364 break;
365 }
366
367 memcpy(reg_val, chip->reg_output, NBANK(chip));
368 mutex_lock(&chip->i2c_lock);
369 for(bank=0; bank<NBANK(chip); bank++) {
e0a8604f
GU
370 unsigned bankmask = mask[bank / sizeof(*mask)] >>
371 ((bank % sizeof(*mask)) * 8);
b4818afe 372 if(bankmask) {
e0a8604f
GU
373 unsigned bankval = bits[bank / sizeof(*bits)] >>
374 ((bank % sizeof(*bits)) * 8);
b4818afe
PR
375 reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
376 }
377 }
378 ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
379 if (ret)
380 goto exit;
381
382 memcpy(chip->reg_output, reg_val, NBANK(chip));
383exit:
384 mutex_unlock(&chip->i2c_lock);
385}
386
f5e8ff48 387static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 388{
389 struct gpio_chip *gc;
390
391 gc = &chip->gpio_chip;
392
f3dc3630
GL
393 gc->direction_input = pca953x_gpio_direction_input;
394 gc->direction_output = pca953x_gpio_direction_output;
395 gc->get = pca953x_gpio_get_value;
396 gc->set = pca953x_gpio_set_value;
b4818afe 397 gc->set_multiple = pca953x_gpio_set_multiple;
9fb1f39e 398 gc->can_sleep = true;
9e60fdcf 399
400 gc->base = chip->gpio_start;
f5e8ff48
GL
401 gc->ngpio = gpios;
402 gc->label = chip->client->name;
58383c78 403 gc->parent = &chip->client->dev;
d72cbed0 404 gc->owner = THIS_MODULE;
77906a54 405 gc->names = chip->names;
9e60fdcf 406}
407
89ea8bbe 408#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 409static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 410{
7bcbce55 411 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 412 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 413
f5f0b7aa 414 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
415}
416
6f5cfc0e 417static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 418{
7bcbce55 419 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 420 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 421
f5f0b7aa 422 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
423}
424
6f5cfc0e 425static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 426{
7bcbce55 427 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 428 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe
MZ
429
430 mutex_lock(&chip->irq_lock);
431}
432
6f5cfc0e 433static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 434{
7bcbce55 435 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 436 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
437 u8 new_irqs;
438 int level, i;
a2cb9aeb
MZ
439
440 /* Look for any newly setup interrupt */
f5f0b7aa
GC
441 for (i = 0; i < NBANK(chip); i++) {
442 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
443 new_irqs &= ~chip->reg_direction[i];
444
445 while (new_irqs) {
446 level = __ffs(new_irqs);
447 pca953x_gpio_direction_input(&chip->gpio_chip,
448 level + (BANK_SZ * i));
449 new_irqs &= ~(1 << level);
450 }
a2cb9aeb 451 }
89ea8bbe
MZ
452
453 mutex_unlock(&chip->irq_lock);
454}
455
6f5cfc0e 456static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 457{
7bcbce55 458 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 459 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
460 int bank_nb = d->hwirq / BANK_SZ;
461 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
462
463 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
464 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 465 d->irq, type);
89ea8bbe
MZ
466 return -EINVAL;
467 }
468
469 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 470 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 471 else
f5f0b7aa 472 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
473
474 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 475 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 476 else
f5f0b7aa 477 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 478
a2cb9aeb 479 return 0;
89ea8bbe
MZ
480}
481
482static struct irq_chip pca953x_irq_chip = {
483 .name = "pca953x",
6f5cfc0e
LB
484 .irq_mask = pca953x_irq_mask,
485 .irq_unmask = pca953x_irq_unmask,
486 .irq_bus_lock = pca953x_irq_bus_lock,
487 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
488 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
489};
490
b6ac1280 491static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 492{
f5f0b7aa
GC
493 u8 cur_stat[MAX_BANK];
494 u8 old_stat[MAX_BANK];
b6ac1280
JS
495 bool pending_seen = false;
496 bool trigger_seen = false;
497 u8 trigger[MAX_BANK];
f5f0b7aa 498 int ret, i, offset = 0;
33226ffd
HZ
499
500 switch (chip->chip_type) {
501 case PCA953X_TYPE:
502 offset = PCA953X_INPUT;
503 break;
504 case PCA957X_TYPE:
505 offset = PCA957X_IN;
506 break;
507 }
f5f0b7aa 508 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe 509 if (ret)
b6ac1280 510 return false;
89ea8bbe
MZ
511
512 /* Remove output pins from the equation */
f5f0b7aa
GC
513 for (i = 0; i < NBANK(chip); i++)
514 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 515
f5f0b7aa 516 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 517
f5f0b7aa
GC
518 for (i = 0; i < NBANK(chip); i++) {
519 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
520 if (trigger[i])
521 trigger_seen = true;
f5f0b7aa
GC
522 }
523
b6ac1280
JS
524 if (!trigger_seen)
525 return false;
89ea8bbe 526
f5f0b7aa 527 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 528
f5f0b7aa
GC
529 for (i = 0; i < NBANK(chip); i++) {
530 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
531 (cur_stat[i] & chip->irq_trig_raise[i]);
532 pending[i] &= trigger[i];
b6ac1280
JS
533 if (pending[i])
534 pending_seen = true;
f5f0b7aa 535 }
89ea8bbe 536
b6ac1280 537 return pending_seen;
89ea8bbe
MZ
538}
539
540static irqreturn_t pca953x_irq_handler(int irq, void *devid)
541{
542 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
543 u8 pending[MAX_BANK];
544 u8 level;
3275d072 545 unsigned nhandled = 0;
f5f0b7aa 546 int i;
89ea8bbe 547
f5f0b7aa 548 if (!pca953x_irq_pending(chip, pending))
3275d072 549 return IRQ_NONE;
89ea8bbe 550
f5f0b7aa
GC
551 for (i = 0; i < NBANK(chip); i++) {
552 while (pending[i]) {
553 level = __ffs(pending[i]);
7bcbce55 554 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
555 level + (BANK_SZ * i)));
556 pending[i] &= ~(1 << level);
3275d072 557 nhandled++;
f5f0b7aa
GC
558 }
559 }
89ea8bbe 560
3275d072 561 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
562}
563
564static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 565 int irq_base)
89ea8bbe
MZ
566{
567 struct i2c_client *client = chip->client;
f5f0b7aa 568 int ret, i, offset = 0;
89ea8bbe 569
4bb93349 570 if (client->irq && irq_base != -1
c6664149 571 && (chip->driver_data & PCA_INT)) {
89ea8bbe 572
33226ffd
HZ
573 switch (chip->chip_type) {
574 case PCA953X_TYPE:
575 offset = PCA953X_INPUT;
576 break;
577 case PCA957X_TYPE:
578 offset = PCA957X_IN;
579 break;
580 }
f5f0b7aa 581 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 582 if (ret)
b42748c9 583 return ret;
89ea8bbe
MZ
584
585 /*
586 * There is no way to know which GPIO line generated the
587 * interrupt. We have to rely on the previous read for
588 * this purpose.
589 */
f5f0b7aa
GC
590 for (i = 0; i < NBANK(chip); i++)
591 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
592 mutex_init(&chip->irq_lock);
593
b42748c9
LW
594 ret = devm_request_threaded_irq(&client->dev,
595 client->irq,
89ea8bbe
MZ
596 NULL,
597 pca953x_irq_handler,
91329132
TS
598 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
599 IRQF_SHARED,
89ea8bbe
MZ
600 dev_name(&client->dev), chip);
601 if (ret) {
602 dev_err(&client->dev, "failed to request irq %d\n",
603 client->irq);
0e8f2fda 604 return ret;
89ea8bbe
MZ
605 }
606
7bcbce55
LW
607 ret = gpiochip_irqchip_add(&chip->gpio_chip,
608 &pca953x_irq_chip,
609 irq_base,
610 handle_simple_irq,
611 IRQ_TYPE_NONE);
612 if (ret) {
613 dev_err(&client->dev,
614 "could not connect irqchip to gpiochip\n");
615 return ret;
616 }
fdd50409
GS
617
618 gpiochip_set_chained_irqchip(&chip->gpio_chip,
619 &pca953x_irq_chip,
620 client->irq, NULL);
89ea8bbe
MZ
621 }
622
623 return 0;
89ea8bbe
MZ
624}
625
89ea8bbe
MZ
626#else /* CONFIG_GPIO_PCA953X_IRQ */
627static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 628 int irq_base)
89ea8bbe
MZ
629{
630 struct i2c_client *client = chip->client;
89ea8bbe 631
c6664149 632 if (irq_base != -1 && (chip->driver_data & PCA_INT))
89ea8bbe
MZ
633 dev_warn(&client->dev, "interrupt support not compiled in\n");
634
635 return 0;
636}
89ea8bbe
MZ
637#endif
638
3836309d 639static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
640{
641 int ret;
f5f0b7aa 642 u8 val[MAX_BANK];
33226ffd 643
f5f0b7aa 644 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
645 if (ret)
646 goto out;
647
f5f0b7aa
GC
648 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
649 chip->reg_direction);
33226ffd
HZ
650 if (ret)
651 goto out;
652
653 /* set platform specific polarity inversion */
f5f0b7aa
GC
654 if (invert)
655 memset(val, 0xFF, NBANK(chip));
656 else
657 memset(val, 0, NBANK(chip));
658
659 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
660out:
661 return ret;
662}
663
3836309d 664static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
665{
666 int ret;
f5f0b7aa 667 u8 val[MAX_BANK];
33226ffd 668
f5f0b7aa 669 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
670 if (ret)
671 goto out;
f5f0b7aa 672 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
673 if (ret)
674 goto out;
675
676 /* set platform specific polarity inversion */
f5f0b7aa
GC
677 if (invert)
678 memset(val, 0xFF, NBANK(chip));
679 else
680 memset(val, 0, NBANK(chip));
c75a3772
NK
681 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
682 if (ret)
683 goto out;
33226ffd 684
20a8a968 685 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 686 memset(val, 0x02, NBANK(chip));
c75a3772
NK
687 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
688 if (ret)
689 goto out;
33226ffd
HZ
690
691 return 0;
692out:
693 return ret;
694}
695
6f29c9af
BD
696static const struct of_device_id pca953x_dt_ids[];
697
3836309d 698static int pca953x_probe(struct i2c_client *client,
3760f736 699 const struct i2c_device_id *id)
9e60fdcf 700{
f3dc3630
GL
701 struct pca953x_platform_data *pdata;
702 struct pca953x_chip *chip;
6a7b36aa 703 int irq_base = 0;
7ea2aa20 704 int ret;
6a7b36aa 705 u32 invert = 0;
9e60fdcf 706
b42748c9
LW
707 chip = devm_kzalloc(&client->dev,
708 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
709 if (chip == NULL)
710 return -ENOMEM;
711
e56aee18 712 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
713 if (pdata) {
714 irq_base = pdata->irq_base;
715 chip->gpio_start = pdata->gpio_base;
716 invert = pdata->invert;
717 chip->names = pdata->names;
718 } else {
4bb93349
MP
719 chip->gpio_start = -1;
720 irq_base = 0;
1965d303 721 }
9e60fdcf 722
723 chip->client = client;
724
f32517bf
AS
725 if (id) {
726 chip->driver_data = id->driver_data;
727 } else {
728 const struct acpi_device_id *id;
6f29c9af 729 const struct of_device_id *match;
f32517bf 730
6f29c9af
BD
731 match = of_match_device(pca953x_dt_ids, &client->dev);
732 if (match) {
733 chip->driver_data = (int)(uintptr_t)match->data;
734 } else {
735 id = acpi_match_device(pca953x_acpi_ids, &client->dev);
736 if (!id)
737 return -ENODEV;
f32517bf 738
6f29c9af
BD
739 chip->driver_data = id->driver_data;
740 }
f32517bf
AS
741 }
742
c6664149 743 chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
77906a54 744
6e20fb18
RS
745 mutex_init(&chip->i2c_lock);
746
9e60fdcf 747 /* initialize cached registers from their original values.
748 * we can't share this chip with another i2c master.
749 */
c6664149 750 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
f5e8ff48 751
33226ffd 752 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 753 ret = device_pca953x_init(chip, invert);
33226ffd 754 else
7ea2aa20
WS
755 ret = device_pca957x_init(chip, invert);
756 if (ret)
b42748c9 757 return ret;
9e60fdcf 758
0ece84f5 759 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
89ea8bbe 760 if (ret)
b42748c9 761 return ret;
f5e8ff48 762
c6664149 763 ret = pca953x_irq_setup(chip, irq_base);
9e60fdcf 764 if (ret)
b42748c9 765 return ret;
9e60fdcf 766
c6dcf592 767 if (pdata && pdata->setup) {
9e60fdcf 768 ret = pdata->setup(client, chip->gpio_chip.base,
769 chip->gpio_chip.ngpio, pdata->context);
770 if (ret < 0)
771 dev_warn(&client->dev, "setup failed, %d\n", ret);
772 }
773
774 i2c_set_clientdata(client, chip);
775 return 0;
9e60fdcf 776}
777
f3dc3630 778static int pca953x_remove(struct i2c_client *client)
9e60fdcf 779{
e56aee18 780 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 781 struct pca953x_chip *chip = i2c_get_clientdata(client);
9e60fdcf 782 int ret = 0;
783
c6dcf592 784 if (pdata && pdata->teardown) {
9e60fdcf 785 ret = pdata->teardown(client, chip->gpio_chip.base,
786 chip->gpio_chip.ngpio, pdata->context);
787 if (ret < 0) {
788 dev_err(&client->dev, "%s failed, %d\n",
789 "teardown", ret);
790 return ret;
791 }
792 }
793
9e60fdcf 794 return 0;
795}
796
6f29c9af
BD
797/* convenience to stop overlong match-table lines */
798#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
799#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
800
ed32620e 801static const struct of_device_id pca953x_dt_ids[] = {
6f29c9af
BD
802 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
803 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
804 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
805 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
806 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
807 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
808 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
809 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
810 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
811 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
812 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
813 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
814 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
815 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
816
817 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
818 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
819 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
820 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
821
822 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
823 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
824 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
825 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
826
827 { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
828
829 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
ed32620e
MR
830 { }
831};
832
833MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
834
f3dc3630 835static struct i2c_driver pca953x_driver = {
9e60fdcf 836 .driver = {
f3dc3630 837 .name = "pca953x",
ed32620e 838 .of_match_table = pca953x_dt_ids,
f32517bf 839 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
9e60fdcf 840 },
f3dc3630
GL
841 .probe = pca953x_probe,
842 .remove = pca953x_remove,
3760f736 843 .id_table = pca953x_id,
9e60fdcf 844};
845
f3dc3630 846static int __init pca953x_init(void)
9e60fdcf 847{
f3dc3630 848 return i2c_add_driver(&pca953x_driver);
9e60fdcf 849}
2f8d1197
DB
850/* register after i2c postcore initcall and before
851 * subsys initcalls that may rely on these GPIOs
852 */
853subsys_initcall(pca953x_init);
9e60fdcf 854
f3dc3630 855static void __exit pca953x_exit(void)
9e60fdcf 856{
f3dc3630 857 i2c_del_driver(&pca953x_driver);
9e60fdcf 858}
f3dc3630 859module_exit(pca953x_exit);
9e60fdcf 860
861MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 862MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 863MODULE_LICENSE("GPL");