Commit | Line | Data |
---|---|---|
9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
b413d7a0 | 14 | #include <linux/acpi.h> |
644f3da0 | 15 | #include <linux/gpio/driver.h> |
054ccdef | 16 | #include <linux/gpio/consumer.h> |
9e60fdcf | 17 | #include <linux/i2c.h> |
b413d7a0 AS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_platform.h> | |
5877457a | 22 | #include <linux/platform_data/pca953x.h> |
b413d7a0 | 23 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
b413d7a0 | 25 | |
9b8e3ec3 | 26 | #include <asm/unaligned.h> |
9e60fdcf | 27 | |
0950c19a NS |
28 | #define PCA953X_INPUT 0x00 |
29 | #define PCA953X_OUTPUT 0x01 | |
30 | #define PCA953X_INVERT 0x02 | |
31 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 32 | |
ae79c190 AS |
33 | #define REG_ADDR_AI 0x80 |
34 | ||
0950c19a NS |
35 | #define PCA957X_IN 0x00 |
36 | #define PCA957X_INVRT 0x01 | |
37 | #define PCA957X_BKEN 0x02 | |
38 | #define PCA957X_PUPD 0x03 | |
39 | #define PCA957X_CFG 0x04 | |
40 | #define PCA957X_OUT 0x05 | |
41 | #define PCA957X_MSK 0x06 | |
42 | #define PCA957X_INTS 0x07 | |
33226ffd | 43 | |
6315d231 | 44 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 45 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
46 | #define PCAL953X_PULL_EN 0x23 |
47 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
48 | #define PCAL953X_INT_MASK 0x25 |
49 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 50 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 51 | |
a0ecbccc NS |
52 | #define PCAL6524_INT_EDGE 0x28 |
53 | #define PCAL6524_INT_CLR 0x2a | |
54 | #define PCAL6524_IN_STATUS 0x2b | |
55 | #define PCAL6524_OUT_INDCONF 0x2c | |
56 | #define PCAL6524_DEBOUNCE 0x2d | |
57 | ||
33226ffd | 58 | #define PCA_GPIO_MASK 0x00FF |
394aeef8 NS |
59 | |
60 | #define PCAL_GPIO_MASK 0x1f | |
61 | #define PCAL_PINCTRL_MASK 0xe0 | |
62 | ||
33226ffd | 63 | #define PCA_INT 0x0100 |
8c7a92da | 64 | #define PCA_PCAL 0x0200 |
0cdf21b3 | 65 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
33226ffd HZ |
66 | #define PCA953X_TYPE 0x1000 |
67 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
68 | #define PCA_TYPE_MASK 0xF000 |
69 | ||
70 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 71 | |
3760f736 | 72 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 73 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
74 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
75 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
76 | { "pca9536", 4 | PCA953X_TYPE, }, | |
77 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
78 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
80 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9556", 8 | PCA953X_TYPE, }, | |
83 | { "pca9557", 8 | PCA953X_TYPE, }, | |
84 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
85 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 86 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 87 | |
3a711e0d | 88 | { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
747e42a1 AS |
89 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
90 | ||
33226ffd HZ |
91 | { "max7310", 8 | PCA953X_TYPE, }, |
92 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
93 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
94 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 95 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
96 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
97 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
98 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 99 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 100 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 101 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 102 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 103 | { } |
f5e8ff48 | 104 | }; |
3760f736 | 105 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 106 | |
f32517bf | 107 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 108 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
109 | { } |
110 | }; | |
111 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
112 | ||
f5f0b7aa GC |
113 | #define MAX_BANK 5 |
114 | #define BANK_SZ 8 | |
115 | ||
a246b819 | 116 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 117 | |
53661f3b BG |
118 | struct pca953x_reg_config { |
119 | int direction; | |
120 | int output; | |
121 | int input; | |
122 | }; | |
123 | ||
124 | static const struct pca953x_reg_config pca953x_regs = { | |
125 | .direction = PCA953X_DIRECTION, | |
126 | .output = PCA953X_OUTPUT, | |
127 | .input = PCA953X_INPUT, | |
128 | }; | |
129 | ||
130 | static const struct pca953x_reg_config pca957x_regs = { | |
131 | .direction = PCA957X_CFG, | |
132 | .output = PCA957X_OUT, | |
133 | .input = PCA957X_IN, | |
134 | }; | |
135 | ||
f3dc3630 | 136 | struct pca953x_chip { |
9e60fdcf | 137 | unsigned gpio_start; |
f5f0b7aa GC |
138 | u8 reg_output[MAX_BANK]; |
139 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 140 | struct mutex i2c_lock; |
9e60fdcf | 141 | |
89ea8bbe MZ |
142 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
143 | struct mutex irq_lock; | |
f5f0b7aa GC |
144 | u8 irq_mask[MAX_BANK]; |
145 | u8 irq_stat[MAX_BANK]; | |
146 | u8 irq_trig_raise[MAX_BANK]; | |
147 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
148 | #endif |
149 | ||
9e60fdcf | 150 | struct i2c_client *client; |
151 | struct gpio_chip gpio_chip; | |
62154991 | 152 | const char *const *names; |
c6664149 | 153 | unsigned long driver_data; |
e23efa31 | 154 | struct regulator *regulator; |
53661f3b BG |
155 | |
156 | const struct pca953x_reg_config *regs; | |
7acc66e3 BG |
157 | |
158 | int (*write_regs)(struct pca953x_chip *, int, u8 *); | |
c6e3cf01 | 159 | int (*read_regs)(struct pca953x_chip *, int, u8 *); |
9e60fdcf | 160 | }; |
161 | ||
f5f0b7aa GC |
162 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
163 | int off) | |
164 | { | |
165 | int ret; | |
166 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
167 | int offset = off / BANK_SZ; | |
168 | ||
169 | ret = i2c_smbus_read_byte_data(chip->client, | |
170 | (reg << bank_shift) + offset); | |
171 | *val = ret; | |
172 | ||
173 | if (ret < 0) { | |
174 | dev_err(&chip->client->dev, "failed reading register\n"); | |
175 | return ret; | |
176 | } | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
182 | int off) | |
183 | { | |
8c7a92da | 184 | int ret; |
f5f0b7aa GC |
185 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
186 | int offset = off / BANK_SZ; | |
187 | ||
188 | ret = i2c_smbus_write_byte_data(chip->client, | |
189 | (reg << bank_shift) + offset, val); | |
190 | ||
191 | if (ret < 0) { | |
192 | dev_err(&chip->client->dev, "failed writing register\n"); | |
193 | return ret; | |
194 | } | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
7acc66e3 | 199 | static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 200 | { |
7acc66e3 BG |
201 | return i2c_smbus_write_byte_data(chip->client, reg, *val); |
202 | } | |
f5e8ff48 | 203 | |
7acc66e3 BG |
204 | static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) |
205 | { | |
b2dc4110 | 206 | u16 word = get_unaligned((u16 *)val); |
c4d1cbd7 | 207 | |
b2dc4110 | 208 | return i2c_smbus_write_word_data(chip->client, reg << 1, word); |
7acc66e3 BG |
209 | } |
210 | ||
211 | static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
212 | { | |
213 | int ret; | |
214 | ||
215 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]); | |
216 | if (ret < 0) | |
217 | return ret; | |
218 | ||
219 | return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]); | |
220 | } | |
f5e8ff48 | 221 | |
7acc66e3 BG |
222 | static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) |
223 | { | |
224 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
d5dbf9c2 NS |
225 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; |
226 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
7acc66e3 BG |
227 | |
228 | return i2c_smbus_write_i2c_block_data(chip->client, | |
d5dbf9c2 | 229 | pinctrl | addr | REG_ADDR_AI, |
7acc66e3 BG |
230 | NBANK(chip), val); |
231 | } | |
232 | ||
233 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
234 | { | |
235 | int ret = 0; | |
236 | ||
237 | ret = chip->write_regs(chip, reg, val); | |
f5e8ff48 GL |
238 | if (ret < 0) { |
239 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 240 | return ret; |
f5e8ff48 GL |
241 | } |
242 | ||
243 | return 0; | |
9e60fdcf | 244 | } |
245 | ||
c6e3cf01 | 246 | static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 247 | { |
248 | int ret; | |
249 | ||
c6e3cf01 BG |
250 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
251 | *val = ret; | |
f5f0b7aa | 252 | |
c6e3cf01 BG |
253 | return ret; |
254 | } | |
255 | ||
256 | static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) | |
257 | { | |
258 | int ret; | |
259 | ||
260 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); | |
b2dc4110 | 261 | put_unaligned(ret, (u16 *)val); |
c6e3cf01 BG |
262 | |
263 | return ret; | |
264 | } | |
265 | ||
266 | static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) | |
267 | { | |
268 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
d5dbf9c2 NS |
269 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; |
270 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
c6e3cf01 BG |
271 | |
272 | return i2c_smbus_read_i2c_block_data(chip->client, | |
d5dbf9c2 | 273 | pinctrl | addr | REG_ADDR_AI, |
c6e3cf01 BG |
274 | NBANK(chip), val); |
275 | } | |
276 | ||
277 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
278 | { | |
279 | int ret; | |
280 | ||
281 | ret = chip->read_regs(chip, reg, val); | |
9e60fdcf | 282 | if (ret < 0) { |
283 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 284 | return ret; |
9e60fdcf | 285 | } |
286 | ||
9e60fdcf | 287 | return 0; |
288 | } | |
289 | ||
f3dc3630 | 290 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 291 | { |
468e67f6 | 292 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 293 | u8 reg_val; |
53661f3b | 294 | int ret; |
9e60fdcf | 295 | |
6e20fb18 | 296 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 297 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd | 298 | |
53661f3b | 299 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 300 | if (ret) |
6e20fb18 | 301 | goto exit; |
9e60fdcf | 302 | |
f5f0b7aa | 303 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
304 | exit: |
305 | mutex_unlock(&chip->i2c_lock); | |
306 | return ret; | |
9e60fdcf | 307 | } |
308 | ||
f3dc3630 | 309 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 310 | unsigned off, int val) |
311 | { | |
468e67f6 | 312 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 313 | u8 reg_val; |
53661f3b | 314 | int ret; |
9e60fdcf | 315 | |
6e20fb18 | 316 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 317 | /* set output level */ |
318 | if (val) | |
f5f0b7aa GC |
319 | reg_val = chip->reg_output[off / BANK_SZ] |
320 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 321 | else |
f5f0b7aa GC |
322 | reg_val = chip->reg_output[off / BANK_SZ] |
323 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 324 | |
53661f3b | 325 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 326 | if (ret) |
6e20fb18 | 327 | goto exit; |
9e60fdcf | 328 | |
f5f0b7aa | 329 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 330 | |
331 | /* then direction */ | |
f5f0b7aa | 332 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
53661f3b | 333 | ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off); |
9e60fdcf | 334 | if (ret) |
6e20fb18 | 335 | goto exit; |
9e60fdcf | 336 | |
f5f0b7aa | 337 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
338 | exit: |
339 | mutex_unlock(&chip->i2c_lock); | |
340 | return ret; | |
9e60fdcf | 341 | } |
342 | ||
f3dc3630 | 343 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 344 | { |
468e67f6 | 345 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 346 | u32 reg_val; |
53661f3b | 347 | int ret; |
9e60fdcf | 348 | |
6e20fb18 | 349 | mutex_lock(&chip->i2c_lock); |
53661f3b | 350 | ret = pca953x_read_single(chip, chip->regs->input, ®_val, off); |
6e20fb18 | 351 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 352 | if (ret < 0) { |
353 | /* NOTE: diagnostic already emitted; that's all we should | |
354 | * do unless gpio_*_value_cansleep() calls become different | |
355 | * from their nonsleeping siblings (and report faults). | |
356 | */ | |
357 | return 0; | |
358 | } | |
359 | ||
40a625da | 360 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 361 | } |
362 | ||
f3dc3630 | 363 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 364 | { |
468e67f6 | 365 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 366 | u8 reg_val; |
53661f3b | 367 | int ret; |
9e60fdcf | 368 | |
6e20fb18 | 369 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 370 | if (val) |
f5f0b7aa GC |
371 | reg_val = chip->reg_output[off / BANK_SZ] |
372 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 373 | else |
f5f0b7aa GC |
374 | reg_val = chip->reg_output[off / BANK_SZ] |
375 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 376 | |
53661f3b | 377 | ret = pca953x_write_single(chip, chip->regs->output, reg_val, off); |
9e60fdcf | 378 | if (ret) |
6e20fb18 | 379 | goto exit; |
9e60fdcf | 380 | |
f5f0b7aa | 381 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
382 | exit: |
383 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 384 | } |
385 | ||
66e57192 AS |
386 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
387 | { | |
388 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
389 | u32 reg_val; | |
390 | int ret; | |
391 | ||
392 | mutex_lock(&chip->i2c_lock); | |
393 | ret = pca953x_read_single(chip, chip->regs->direction, ®_val, off); | |
394 | mutex_unlock(&chip->i2c_lock); | |
395 | if (ret < 0) | |
396 | return ret; | |
397 | ||
398 | return !!(reg_val & (1u << (off % BANK_SZ))); | |
399 | } | |
400 | ||
b4818afe | 401 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 402 | unsigned long *mask, unsigned long *bits) |
b4818afe | 403 | { |
468e67f6 | 404 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d BG |
405 | unsigned int bank_mask, bank_val; |
406 | int bank_shift, bank; | |
b4818afe | 407 | u8 reg_val[MAX_BANK]; |
53661f3b | 408 | int ret; |
ea3d579d BG |
409 | |
410 | bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
b4818afe | 411 | |
b4818afe | 412 | mutex_lock(&chip->i2c_lock); |
386377b5 | 413 | memcpy(reg_val, chip->reg_output, NBANK(chip)); |
ea3d579d BG |
414 | for (bank = 0; bank < NBANK(chip); bank++) { |
415 | bank_mask = mask[bank / sizeof(*mask)] >> | |
416 | ((bank % sizeof(*mask)) * 8); | |
417 | if (bank_mask) { | |
418 | bank_val = bits[bank / sizeof(*bits)] >> | |
419 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 420 | bank_val &= bank_mask; |
ea3d579d | 421 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
422 | } |
423 | } | |
ea3d579d | 424 | |
53661f3b BG |
425 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
426 | chip->regs->output << bank_shift, | |
427 | NBANK(chip), reg_val); | |
b4818afe PR |
428 | if (ret) |
429 | goto exit; | |
430 | ||
431 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
432 | exit: | |
433 | mutex_unlock(&chip->i2c_lock); | |
434 | } | |
435 | ||
f5e8ff48 | 436 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 437 | { |
438 | struct gpio_chip *gc; | |
439 | ||
440 | gc = &chip->gpio_chip; | |
441 | ||
f3dc3630 GL |
442 | gc->direction_input = pca953x_gpio_direction_input; |
443 | gc->direction_output = pca953x_gpio_direction_output; | |
444 | gc->get = pca953x_gpio_get_value; | |
445 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 446 | gc->get_direction = pca953x_gpio_get_direction; |
b4818afe | 447 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 448 | gc->can_sleep = true; |
9e60fdcf | 449 | |
450 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
451 | gc->ngpio = gpios; |
452 | gc->label = chip->client->name; | |
58383c78 | 453 | gc->parent = &chip->client->dev; |
d72cbed0 | 454 | gc->owner = THIS_MODULE; |
77906a54 | 455 | gc->names = chip->names; |
9e60fdcf | 456 | } |
457 | ||
89ea8bbe | 458 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 459 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 460 | { |
7bcbce55 | 461 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 462 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 463 | |
f5f0b7aa | 464 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
465 | } |
466 | ||
6f5cfc0e | 467 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 468 | { |
7bcbce55 | 469 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 470 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 471 | |
f5f0b7aa | 472 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
473 | } |
474 | ||
6f5cfc0e | 475 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 476 | { |
7bcbce55 | 477 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 478 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
479 | |
480 | mutex_lock(&chip->irq_lock); | |
481 | } | |
482 | ||
6f5cfc0e | 483 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 484 | { |
7bcbce55 | 485 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 486 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
487 | u8 new_irqs; |
488 | int level, i; | |
44896bea YL |
489 | u8 invert_irq_mask[MAX_BANK]; |
490 | ||
491 | if (chip->driver_data & PCA_PCAL) { | |
492 | /* Enable latch on interrupt-enabled inputs */ | |
493 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
494 | ||
495 | for (i = 0; i < NBANK(chip); i++) | |
496 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
497 | ||
498 | /* Unmask enabled interrupts */ | |
499 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
500 | } | |
a2cb9aeb MZ |
501 | |
502 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
503 | for (i = 0; i < NBANK(chip); i++) { |
504 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
505 | new_irqs &= ~chip->reg_direction[i]; | |
506 | ||
507 | while (new_irqs) { | |
508 | level = __ffs(new_irqs); | |
509 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
510 | level + (BANK_SZ * i)); | |
511 | new_irqs &= ~(1 << level); | |
512 | } | |
a2cb9aeb | 513 | } |
89ea8bbe MZ |
514 | |
515 | mutex_unlock(&chip->irq_lock); | |
516 | } | |
517 | ||
6f5cfc0e | 518 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 519 | { |
7bcbce55 | 520 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 521 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
522 | int bank_nb = d->hwirq / BANK_SZ; |
523 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
524 | |
525 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
526 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 527 | d->irq, type); |
89ea8bbe MZ |
528 | return -EINVAL; |
529 | } | |
530 | ||
531 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 532 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 533 | else |
f5f0b7aa | 534 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
535 | |
536 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 537 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 538 | else |
f5f0b7aa | 539 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 540 | |
a2cb9aeb | 541 | return 0; |
89ea8bbe MZ |
542 | } |
543 | ||
0a70fe00 GD |
544 | static void pca953x_irq_shutdown(struct irq_data *d) |
545 | { | |
546 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); | |
547 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
548 | ||
549 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | |
550 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | |
551 | } | |
552 | ||
89ea8bbe MZ |
553 | static struct irq_chip pca953x_irq_chip = { |
554 | .name = "pca953x", | |
6f5cfc0e LB |
555 | .irq_mask = pca953x_irq_mask, |
556 | .irq_unmask = pca953x_irq_unmask, | |
557 | .irq_bus_lock = pca953x_irq_bus_lock, | |
558 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
559 | .irq_set_type = pca953x_irq_set_type, | |
0a70fe00 | 560 | .irq_shutdown = pca953x_irq_shutdown, |
89ea8bbe MZ |
561 | }; |
562 | ||
b6ac1280 | 563 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 564 | { |
f5f0b7aa GC |
565 | u8 cur_stat[MAX_BANK]; |
566 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
567 | bool pending_seen = false; |
568 | bool trigger_seen = false; | |
569 | u8 trigger[MAX_BANK]; | |
53661f3b | 570 | int ret, i; |
33226ffd | 571 | |
44896bea YL |
572 | if (chip->driver_data & PCA_PCAL) { |
573 | /* Read the current interrupt status from the device */ | |
574 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
575 | if (ret) | |
576 | return false; | |
577 | ||
578 | /* Check latched inputs and clear interrupt status */ | |
579 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
580 | if (ret) | |
581 | return false; | |
582 | ||
583 | for (i = 0; i < NBANK(chip); i++) { | |
584 | /* Apply filter for rising/falling edge selection */ | |
585 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
586 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
587 | pending[i] &= trigger[i]; | |
588 | if (pending[i]) | |
589 | pending_seen = true; | |
590 | } | |
591 | ||
592 | return pending_seen; | |
593 | } | |
594 | ||
53661f3b | 595 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 596 | if (ret) |
b6ac1280 | 597 | return false; |
89ea8bbe MZ |
598 | |
599 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
600 | for (i = 0; i < NBANK(chip); i++) |
601 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 602 | |
f5f0b7aa | 603 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 604 | |
f5f0b7aa GC |
605 | for (i = 0; i < NBANK(chip); i++) { |
606 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
607 | if (trigger[i]) |
608 | trigger_seen = true; | |
f5f0b7aa GC |
609 | } |
610 | ||
b6ac1280 JS |
611 | if (!trigger_seen) |
612 | return false; | |
89ea8bbe | 613 | |
f5f0b7aa | 614 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 615 | |
f5f0b7aa GC |
616 | for (i = 0; i < NBANK(chip); i++) { |
617 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
618 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
619 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
620 | if (pending[i]) |
621 | pending_seen = true; | |
f5f0b7aa | 622 | } |
89ea8bbe | 623 | |
b6ac1280 | 624 | return pending_seen; |
89ea8bbe MZ |
625 | } |
626 | ||
627 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
628 | { | |
629 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
630 | u8 pending[MAX_BANK]; |
631 | u8 level; | |
3275d072 | 632 | unsigned nhandled = 0; |
f5f0b7aa | 633 | int i; |
89ea8bbe | 634 | |
f5f0b7aa | 635 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 636 | return IRQ_NONE; |
89ea8bbe | 637 | |
f5f0b7aa GC |
638 | for (i = 0; i < NBANK(chip); i++) { |
639 | while (pending[i]) { | |
640 | level = __ffs(pending[i]); | |
f0fbe7bc | 641 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
f5f0b7aa GC |
642 | level + (BANK_SZ * i))); |
643 | pending[i] &= ~(1 << level); | |
3275d072 | 644 | nhandled++; |
f5f0b7aa GC |
645 | } |
646 | } | |
89ea8bbe | 647 | |
3275d072 | 648 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
649 | } |
650 | ||
651 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 652 | int irq_base) |
89ea8bbe MZ |
653 | { |
654 | struct i2c_client *client = chip->client; | |
53661f3b | 655 | int ret, i; |
89ea8bbe | 656 | |
4bb93349 | 657 | if (client->irq && irq_base != -1 |
c6664149 | 658 | && (chip->driver_data & PCA_INT)) { |
53661f3b BG |
659 | ret = pca953x_read_regs(chip, |
660 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 661 | if (ret) |
b42748c9 | 662 | return ret; |
89ea8bbe MZ |
663 | |
664 | /* | |
665 | * There is no way to know which GPIO line generated the | |
666 | * interrupt. We have to rely on the previous read for | |
667 | * this purpose. | |
668 | */ | |
f5f0b7aa GC |
669 | for (i = 0; i < NBANK(chip); i++) |
670 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
671 | mutex_init(&chip->irq_lock); |
672 | ||
b42748c9 LW |
673 | ret = devm_request_threaded_irq(&client->dev, |
674 | client->irq, | |
89ea8bbe MZ |
675 | NULL, |
676 | pca953x_irq_handler, | |
91329132 TS |
677 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
678 | IRQF_SHARED, | |
89ea8bbe MZ |
679 | dev_name(&client->dev), chip); |
680 | if (ret) { | |
681 | dev_err(&client->dev, "failed to request irq %d\n", | |
682 | client->irq); | |
0e8f2fda | 683 | return ret; |
89ea8bbe MZ |
684 | } |
685 | ||
d245b3f9 LW |
686 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, |
687 | &pca953x_irq_chip, | |
688 | irq_base, | |
689 | handle_simple_irq, | |
690 | IRQ_TYPE_NONE); | |
7bcbce55 LW |
691 | if (ret) { |
692 | dev_err(&client->dev, | |
693 | "could not connect irqchip to gpiochip\n"); | |
694 | return ret; | |
695 | } | |
fdd50409 | 696 | |
d245b3f9 LW |
697 | gpiochip_set_nested_irqchip(&chip->gpio_chip, |
698 | &pca953x_irq_chip, | |
699 | client->irq); | |
89ea8bbe MZ |
700 | } |
701 | ||
702 | return 0; | |
89ea8bbe MZ |
703 | } |
704 | ||
89ea8bbe MZ |
705 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
706 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 707 | int irq_base) |
89ea8bbe MZ |
708 | { |
709 | struct i2c_client *client = chip->client; | |
89ea8bbe | 710 | |
c6664149 | 711 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
712 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
713 | ||
714 | return 0; | |
715 | } | |
89ea8bbe MZ |
716 | #endif |
717 | ||
3836309d | 718 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
719 | { |
720 | int ret; | |
f5f0b7aa | 721 | u8 val[MAX_BANK]; |
33226ffd | 722 | |
53661f3b BG |
723 | chip->regs = &pca953x_regs; |
724 | ||
725 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
726 | if (ret) |
727 | goto out; | |
728 | ||
53661f3b BG |
729 | ret = pca953x_read_regs(chip, chip->regs->direction, |
730 | chip->reg_direction); | |
33226ffd HZ |
731 | if (ret) |
732 | goto out; | |
733 | ||
734 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
735 | if (invert) |
736 | memset(val, 0xFF, NBANK(chip)); | |
737 | else | |
738 | memset(val, 0, NBANK(chip)); | |
739 | ||
740 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
741 | out: |
742 | return ret; | |
743 | } | |
744 | ||
3836309d | 745 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
746 | { |
747 | int ret; | |
f5f0b7aa | 748 | u8 val[MAX_BANK]; |
33226ffd | 749 | |
53661f3b BG |
750 | chip->regs = &pca957x_regs; |
751 | ||
752 | ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output); | |
33226ffd HZ |
753 | if (ret) |
754 | goto out; | |
53661f3b BG |
755 | ret = pca953x_read_regs(chip, chip->regs->direction, |
756 | chip->reg_direction); | |
33226ffd HZ |
757 | if (ret) |
758 | goto out; | |
759 | ||
760 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
761 | if (invert) |
762 | memset(val, 0xFF, NBANK(chip)); | |
763 | else | |
764 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
765 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
766 | if (ret) | |
767 | goto out; | |
33226ffd | 768 | |
20a8a968 | 769 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 770 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
771 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
772 | if (ret) | |
773 | goto out; | |
33226ffd HZ |
774 | |
775 | return 0; | |
776 | out: | |
777 | return ret; | |
778 | } | |
779 | ||
6f29c9af BD |
780 | static const struct of_device_id pca953x_dt_ids[]; |
781 | ||
3836309d | 782 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 783 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 784 | { |
f3dc3630 GL |
785 | struct pca953x_platform_data *pdata; |
786 | struct pca953x_chip *chip; | |
6a7b36aa | 787 | int irq_base = 0; |
7ea2aa20 | 788 | int ret; |
6a7b36aa | 789 | u32 invert = 0; |
e23efa31 | 790 | struct regulator *reg; |
9e60fdcf | 791 | |
b42748c9 LW |
792 | chip = devm_kzalloc(&client->dev, |
793 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
794 | if (chip == NULL) |
795 | return -ENOMEM; | |
796 | ||
e56aee18 | 797 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
798 | if (pdata) { |
799 | irq_base = pdata->irq_base; | |
800 | chip->gpio_start = pdata->gpio_base; | |
801 | invert = pdata->invert; | |
802 | chip->names = pdata->names; | |
803 | } else { | |
054ccdef SL |
804 | struct gpio_desc *reset_gpio; |
805 | ||
4bb93349 MP |
806 | chip->gpio_start = -1; |
807 | irq_base = 0; | |
054ccdef | 808 | |
96530b37 AS |
809 | /* |
810 | * See if we need to de-assert a reset pin. | |
811 | * | |
812 | * There is no known ACPI-enabled platforms that are | |
813 | * using "reset" GPIO. Otherwise any of those platform | |
814 | * must use _DSD method with corresponding property. | |
815 | */ | |
054ccdef SL |
816 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
817 | GPIOD_OUT_LOW); | |
818 | if (IS_ERR(reset_gpio)) | |
819 | return PTR_ERR(reset_gpio); | |
1965d303 | 820 | } |
9e60fdcf | 821 | |
822 | chip->client = client; | |
823 | ||
e23efa31 PR |
824 | reg = devm_regulator_get(&client->dev, "vcc"); |
825 | if (IS_ERR(reg)) { | |
826 | ret = PTR_ERR(reg); | |
827 | if (ret != -EPROBE_DEFER) | |
828 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
829 | return ret; | |
830 | } | |
831 | ret = regulator_enable(reg); | |
832 | if (ret) { | |
833 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
834 | return ret; | |
835 | } | |
836 | chip->regulator = reg; | |
837 | ||
6212e1d6 WS |
838 | if (i2c_id) { |
839 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 840 | } else { |
6212e1d6 | 841 | const struct acpi_device_id *acpi_id; |
67bab935 | 842 | struct device *dev = &client->dev; |
f32517bf | 843 | |
67bab935 TR |
844 | chip->driver_data = (uintptr_t)of_device_get_match_data(dev); |
845 | if (!chip->driver_data) { | |
846 | acpi_id = acpi_match_device(pca953x_acpi_ids, dev); | |
87840a2b | 847 | if (!acpi_id) { |
e23efa31 PR |
848 | ret = -ENODEV; |
849 | goto err_exit; | |
850 | } | |
f32517bf | 851 | |
6212e1d6 | 852 | chip->driver_data = acpi_id->driver_data; |
6f29c9af | 853 | } |
f32517bf AS |
854 | } |
855 | ||
6e20fb18 | 856 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
857 | /* |
858 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
859 | * expander using the same driver higher on the device tree, read the | |
860 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
861 | * subclass for chip->i2c_lock. | |
862 | * | |
863 | * REVISIT: This solution is not complete. It protects us from lockdep | |
864 | * false positives when the expander controlling the i2c-mux is on | |
865 | * a different level on the device tree, but not when it's on the same | |
866 | * level on a different branch (in which case the subclass number | |
867 | * would be the same). | |
868 | * | |
869 | * TODO: Once a correct solution is developed, a similar fix should be | |
870 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
871 | * regmap-i2c). | |
872 | */ | |
559b4699 BG |
873 | lockdep_set_subclass(&chip->i2c_lock, |
874 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 875 | |
9e60fdcf | 876 | /* initialize cached registers from their original values. |
877 | * we can't share this chip with another i2c master. | |
878 | */ | |
c6664149 | 879 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 880 | |
7acc66e3 BG |
881 | if (chip->gpio_chip.ngpio <= 8) { |
882 | chip->write_regs = pca953x_write_regs_8; | |
c6e3cf01 | 883 | chip->read_regs = pca953x_read_regs_8; |
7acc66e3 BG |
884 | } else if (chip->gpio_chip.ngpio >= 24) { |
885 | chip->write_regs = pca953x_write_regs_24; | |
c6e3cf01 | 886 | chip->read_regs = pca953x_read_regs_24; |
7acc66e3 BG |
887 | } else { |
888 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) | |
889 | chip->write_regs = pca953x_write_regs_16; | |
890 | else | |
891 | chip->write_regs = pca957x_write_regs_16; | |
c6e3cf01 | 892 | chip->read_regs = pca953x_read_regs_16; |
7acc66e3 BG |
893 | } |
894 | ||
60f547be | 895 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
7ea2aa20 | 896 | ret = device_pca953x_init(chip, invert); |
33226ffd | 897 | else |
7ea2aa20 WS |
898 | ret = device_pca957x_init(chip, invert); |
899 | if (ret) | |
e23efa31 | 900 | goto err_exit; |
9e60fdcf | 901 | |
0ece84f5 | 902 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 903 | if (ret) |
e23efa31 | 904 | goto err_exit; |
f5e8ff48 | 905 | |
c6664149 | 906 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 907 | if (ret) |
e23efa31 | 908 | goto err_exit; |
9e60fdcf | 909 | |
c6dcf592 | 910 | if (pdata && pdata->setup) { |
9e60fdcf | 911 | ret = pdata->setup(client, chip->gpio_chip.base, |
912 | chip->gpio_chip.ngpio, pdata->context); | |
913 | if (ret < 0) | |
914 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
915 | } | |
916 | ||
917 | i2c_set_clientdata(client, chip); | |
918 | return 0; | |
e23efa31 PR |
919 | |
920 | err_exit: | |
921 | regulator_disable(chip->regulator); | |
922 | return ret; | |
9e60fdcf | 923 | } |
924 | ||
f3dc3630 | 925 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 926 | { |
e56aee18 | 927 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 928 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 929 | int ret; |
9e60fdcf | 930 | |
c6dcf592 | 931 | if (pdata && pdata->teardown) { |
9e60fdcf | 932 | ret = pdata->teardown(client, chip->gpio_chip.base, |
933 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 934 | if (ret < 0) |
9e60fdcf | 935 | dev_err(&client->dev, "%s failed, %d\n", |
936 | "teardown", ret); | |
bf62efeb AB |
937 | } else { |
938 | ret = 0; | |
9e60fdcf | 939 | } |
940 | ||
e23efa31 PR |
941 | regulator_disable(chip->regulator); |
942 | ||
943 | return ret; | |
9e60fdcf | 944 | } |
945 | ||
6f29c9af BD |
946 | /* convenience to stop overlong match-table lines */ |
947 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
948 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
949 | ||
ed32620e | 950 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
951 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
952 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
953 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
954 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
955 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
956 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
957 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
958 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
959 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
960 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
961 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
962 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
963 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
964 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
965 | ||
0cdf21b3 NS |
966 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
967 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, | |
3a711e0d | 968 | |
6f29c9af BD |
969 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
970 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
971 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
972 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 973 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
974 | |
975 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 976 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
977 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
978 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
979 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
980 | ||
8a64e557 | 981 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6f29c9af BD |
982 | |
983 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
984 | { } |
985 | }; | |
986 | ||
987 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
988 | ||
f3dc3630 | 989 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 990 | .driver = { |
f3dc3630 | 991 | .name = "pca953x", |
ed32620e | 992 | .of_match_table = pca953x_dt_ids, |
f32517bf | 993 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 994 | }, |
f3dc3630 GL |
995 | .probe = pca953x_probe, |
996 | .remove = pca953x_remove, | |
3760f736 | 997 | .id_table = pca953x_id, |
9e60fdcf | 998 | }; |
999 | ||
f3dc3630 | 1000 | static int __init pca953x_init(void) |
9e60fdcf | 1001 | { |
f3dc3630 | 1002 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 1003 | } |
2f8d1197 DB |
1004 | /* register after i2c postcore initcall and before |
1005 | * subsys initcalls that may rely on these GPIOs | |
1006 | */ | |
1007 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1008 | |
f3dc3630 | 1009 | static void __exit pca953x_exit(void) |
9e60fdcf | 1010 | { |
f3dc3630 | 1011 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1012 | } |
f3dc3630 | 1013 | module_exit(pca953x_exit); |
9e60fdcf | 1014 | |
1015 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1016 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1017 | MODULE_LICENSE("GPL"); |