Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
b413d7a0 | 14 | #include <linux/acpi.h> |
644f3da0 | 15 | #include <linux/gpio/driver.h> |
054ccdef | 16 | #include <linux/gpio/consumer.h> |
9e60fdcf | 17 | #include <linux/i2c.h> |
b413d7a0 AS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_platform.h> | |
5877457a | 22 | #include <linux/platform_data/pca953x.h> |
49427232 | 23 | #include <linux/regmap.h> |
b413d7a0 | 24 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
b413d7a0 | 26 | |
9b8e3ec3 | 27 | #include <asm/unaligned.h> |
9e60fdcf | 28 | |
0950c19a NS |
29 | #define PCA953X_INPUT 0x00 |
30 | #define PCA953X_OUTPUT 0x01 | |
31 | #define PCA953X_INVERT 0x02 | |
32 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 33 | |
49427232 MV |
34 | #define REG_ADDR_MASK 0x3f |
35 | #define REG_ADDR_EXT 0x40 | |
ae79c190 AS |
36 | #define REG_ADDR_AI 0x80 |
37 | ||
0950c19a NS |
38 | #define PCA957X_IN 0x00 |
39 | #define PCA957X_INVRT 0x01 | |
40 | #define PCA957X_BKEN 0x02 | |
41 | #define PCA957X_PUPD 0x03 | |
42 | #define PCA957X_CFG 0x04 | |
43 | #define PCA957X_OUT 0x05 | |
44 | #define PCA957X_MSK 0x06 | |
45 | #define PCA957X_INTS 0x07 | |
33226ffd | 46 | |
6315d231 | 47 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 48 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
49 | #define PCAL953X_PULL_EN 0x23 |
50 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
51 | #define PCAL953X_INT_MASK 0x25 |
52 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 53 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 54 | |
a0ecbccc NS |
55 | #define PCAL6524_INT_EDGE 0x28 |
56 | #define PCAL6524_INT_CLR 0x2a | |
57 | #define PCAL6524_IN_STATUS 0x2b | |
58 | #define PCAL6524_OUT_INDCONF 0x2c | |
59 | #define PCAL6524_DEBOUNCE 0x2d | |
60 | ||
33226ffd | 61 | #define PCA_GPIO_MASK 0x00FF |
394aeef8 NS |
62 | |
63 | #define PCAL_GPIO_MASK 0x1f | |
92f45ebe | 64 | #define PCAL_PINCTRL_MASK 0x60 |
394aeef8 | 65 | |
33226ffd | 66 | #define PCA_INT 0x0100 |
8c7a92da | 67 | #define PCA_PCAL 0x0200 |
0cdf21b3 | 68 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
33226ffd HZ |
69 | #define PCA953X_TYPE 0x1000 |
70 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
71 | #define PCA_TYPE_MASK 0xF000 |
72 | ||
73 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 74 | |
3760f736 | 75 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 76 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
77 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
78 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "pca9536", 4 | PCA953X_TYPE, }, | |
80 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
83 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
84 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
85 | { "pca9556", 8 | PCA953X_TYPE, }, | |
86 | { "pca9557", 8 | PCA953X_TYPE, }, | |
87 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
88 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 89 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 90 | |
3a711e0d | 91 | { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
747e42a1 AS |
92 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
93 | ||
33226ffd HZ |
94 | { "max7310", 8 | PCA953X_TYPE, }, |
95 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
96 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
97 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 98 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
99 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
100 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
101 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 102 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 103 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 104 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 105 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 106 | { } |
f5e8ff48 | 107 | }; |
3760f736 | 108 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 109 | |
f32517bf | 110 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 111 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
112 | { } |
113 | }; | |
114 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
115 | ||
f5f0b7aa GC |
116 | #define MAX_BANK 5 |
117 | #define BANK_SZ 8 | |
118 | ||
a246b819 | 119 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 120 | |
53661f3b BG |
121 | struct pca953x_reg_config { |
122 | int direction; | |
123 | int output; | |
124 | int input; | |
7a04aaa3 | 125 | int invert; |
53661f3b BG |
126 | }; |
127 | ||
128 | static const struct pca953x_reg_config pca953x_regs = { | |
129 | .direction = PCA953X_DIRECTION, | |
130 | .output = PCA953X_OUTPUT, | |
131 | .input = PCA953X_INPUT, | |
7a04aaa3 | 132 | .invert = PCA953X_INVERT, |
53661f3b BG |
133 | }; |
134 | ||
135 | static const struct pca953x_reg_config pca957x_regs = { | |
136 | .direction = PCA957X_CFG, | |
137 | .output = PCA957X_OUT, | |
138 | .input = PCA957X_IN, | |
7a04aaa3 | 139 | .invert = PCA957X_INVRT, |
53661f3b BG |
140 | }; |
141 | ||
f3dc3630 | 142 | struct pca953x_chip { |
9e60fdcf | 143 | unsigned gpio_start; |
6e20fb18 | 144 | struct mutex i2c_lock; |
49427232 | 145 | struct regmap *regmap; |
9e60fdcf | 146 | |
89ea8bbe MZ |
147 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
148 | struct mutex irq_lock; | |
f5f0b7aa GC |
149 | u8 irq_mask[MAX_BANK]; |
150 | u8 irq_stat[MAX_BANK]; | |
151 | u8 irq_trig_raise[MAX_BANK]; | |
152 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
153 | #endif |
154 | ||
9e60fdcf | 155 | struct i2c_client *client; |
156 | struct gpio_chip gpio_chip; | |
62154991 | 157 | const char *const *names; |
c6664149 | 158 | unsigned long driver_data; |
e23efa31 | 159 | struct regulator *regulator; |
53661f3b BG |
160 | |
161 | const struct pca953x_reg_config *regs; | |
9e60fdcf | 162 | }; |
163 | ||
873d1e8e | 164 | static int pca953x_bank_shift(struct pca953x_chip *chip) |
f5f0b7aa | 165 | { |
873d1e8e MV |
166 | return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
167 | } | |
f5f0b7aa | 168 | |
49427232 MV |
169 | #define PCA953x_BANK_INPUT BIT(0) |
170 | #define PCA953x_BANK_OUTPUT BIT(1) | |
171 | #define PCA953x_BANK_POLARITY BIT(2) | |
172 | #define PCA953x_BANK_CONFIG BIT(3) | |
f5f0b7aa | 173 | |
49427232 MV |
174 | #define PCA957x_BANK_INPUT BIT(0) |
175 | #define PCA957x_BANK_POLARITY BIT(1) | |
176 | #define PCA957x_BANK_BUSHOLD BIT(2) | |
177 | #define PCA957x_BANK_CONFIG BIT(4) | |
178 | #define PCA957x_BANK_OUTPUT BIT(5) | |
179 | ||
180 | #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) | |
181 | #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) | |
182 | #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) | |
183 | ||
184 | /* | |
185 | * We care about the following registers: | |
186 | * - Standard set, below 0x40, each port can be replicated up to 8 times | |
187 | * - PCA953x standard | |
188 | * Input port 0x00 + 0 * bank_size R | |
189 | * Output port 0x00 + 1 * bank_size RW | |
190 | * Polarity Inversion port 0x00 + 2 * bank_size RW | |
191 | * Configuration port 0x00 + 3 * bank_size RW | |
192 | * - PCA957x with mixed up registers | |
193 | * Input port 0x00 + 0 * bank_size R | |
194 | * Polarity Inversion port 0x00 + 1 * bank_size RW | |
195 | * Bus hold port 0x00 + 2 * bank_size RW | |
196 | * Configuration port 0x00 + 4 * bank_size RW | |
197 | * Output port 0x00 + 5 * bank_size RW | |
198 | * | |
199 | * - Extended set, above 0x40, often chip specific. | |
200 | * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: | |
201 | * Input latch register 0x40 + 2 * bank_size RW | |
202 | * Interrupt mask register 0x40 + 5 * bank_size RW | |
203 | * Interrupt status register 0x40 + 6 * bank_size R | |
204 | * | |
205 | * - Registers with bit 0x80 set, the AI bit | |
206 | * The bit is cleared and the registers fall into one of the | |
207 | * categories above. | |
208 | */ | |
209 | ||
210 | static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, | |
211 | u32 checkbank) | |
212 | { | |
213 | int bank_shift = pca953x_bank_shift(chip); | |
214 | int bank = (reg & REG_ADDR_MASK) >> bank_shift; | |
215 | int offset = reg & (BIT(bank_shift) - 1); | |
216 | ||
217 | /* Special PCAL extended register check. */ | |
218 | if (reg & REG_ADDR_EXT) { | |
219 | if (!(chip->driver_data & PCA_PCAL)) | |
220 | return false; | |
221 | bank += 8; | |
f5f0b7aa GC |
222 | } |
223 | ||
49427232 MV |
224 | /* Register is not in the matching bank. */ |
225 | if (!(BIT(bank) & checkbank)) | |
226 | return false; | |
227 | ||
228 | /* Register is not within allowed range of bank. */ | |
229 | if (offset >= NBANK(chip)) | |
230 | return false; | |
231 | ||
232 | return true; | |
f5f0b7aa GC |
233 | } |
234 | ||
49427232 | 235 | static bool pca953x_readable_register(struct device *dev, unsigned int reg) |
f5f0b7aa | 236 | { |
49427232 MV |
237 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
238 | u32 bank; | |
f5f0b7aa | 239 | |
49427232 MV |
240 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
241 | bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | | |
242 | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; | |
243 | } else { | |
244 | bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | | |
245 | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | | |
246 | PCA957x_BANK_BUSHOLD; | |
247 | } | |
f5f0b7aa | 248 | |
49427232 MV |
249 | if (chip->driver_data & PCA_PCAL) { |
250 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_IRQ_MASK | | |
251 | PCAL9xxx_BANK_IRQ_STAT; | |
f5f0b7aa GC |
252 | } |
253 | ||
49427232 | 254 | return pca953x_check_register(chip, reg, bank); |
f5f0b7aa GC |
255 | } |
256 | ||
49427232 | 257 | static bool pca953x_writeable_register(struct device *dev, unsigned int reg) |
9e60fdcf | 258 | { |
49427232 MV |
259 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
260 | u32 bank; | |
f5e8ff48 | 261 | |
49427232 MV |
262 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
263 | bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | | |
264 | PCA953x_BANK_CONFIG; | |
265 | } else { | |
266 | bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | | |
267 | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; | |
268 | } | |
c4d1cbd7 | 269 | |
49427232 MV |
270 | if (chip->driver_data & PCA_PCAL) |
271 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_IRQ_MASK; | |
272 | ||
273 | return pca953x_check_register(chip, reg, bank); | |
7acc66e3 BG |
274 | } |
275 | ||
49427232 | 276 | static bool pca953x_volatile_register(struct device *dev, unsigned int reg) |
7acc66e3 | 277 | { |
49427232 MV |
278 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
279 | u32 bank; | |
7acc66e3 | 280 | |
49427232 MV |
281 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
282 | bank = PCA953x_BANK_INPUT; | |
283 | else | |
284 | bank = PCA957x_BANK_INPUT; | |
285 | ||
286 | if (chip->driver_data & PCA_PCAL) | |
287 | bank |= PCAL9xxx_BANK_IRQ_STAT; | |
7acc66e3 | 288 | |
49427232 | 289 | return pca953x_check_register(chip, reg, bank); |
7acc66e3 | 290 | } |
f5e8ff48 | 291 | |
49427232 MV |
292 | const struct regmap_config pca953x_i2c_regmap = { |
293 | .reg_bits = 8, | |
294 | .val_bits = 8, | |
295 | ||
296 | .readable_reg = pca953x_readable_register, | |
297 | .writeable_reg = pca953x_writeable_register, | |
298 | .volatile_reg = pca953x_volatile_register, | |
299 | ||
300 | .cache_type = REGCACHE_RBTREE, | |
301 | .max_register = 0x7f, | |
302 | }; | |
303 | ||
b32cecb4 MV |
304 | static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, |
305 | bool write, bool addrinc) | |
7acc66e3 | 306 | { |
b32cecb4 | 307 | int bank_shift = pca953x_bank_shift(chip); |
d5dbf9c2 NS |
308 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; |
309 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
b32cecb4 MV |
310 | u8 regaddr = pinctrl | addr | (off / BANK_SZ); |
311 | ||
312 | /* Single byte read doesn't need AI bit set. */ | |
313 | if (!addrinc) | |
314 | return regaddr; | |
315 | ||
316 | /* Chips with 24 and more GPIOs always support Auto Increment */ | |
317 | if (write && NBANK(chip) > 2) | |
318 | regaddr |= REG_ADDR_AI; | |
7acc66e3 | 319 | |
b32cecb4 MV |
320 | /* PCA9575 needs address-increment on multi-byte writes */ |
321 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) | |
322 | regaddr |= REG_ADDR_AI; | |
323 | ||
324 | return regaddr; | |
7acc66e3 BG |
325 | } |
326 | ||
327 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
328 | { | |
b32cecb4 | 329 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); |
90adb097 | 330 | int ret; |
7acc66e3 | 331 | |
49427232 | 332 | ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); |
f5e8ff48 GL |
333 | if (ret < 0) { |
334 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 335 | return ret; |
f5e8ff48 GL |
336 | } |
337 | ||
338 | return 0; | |
9e60fdcf | 339 | } |
340 | ||
c6e3cf01 BG |
341 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
342 | { | |
b32cecb4 | 343 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); |
c6e3cf01 BG |
344 | int ret; |
345 | ||
49427232 | 346 | ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); |
9e60fdcf | 347 | if (ret < 0) { |
348 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 349 | return ret; |
9e60fdcf | 350 | } |
351 | ||
9e60fdcf | 352 | return 0; |
353 | } | |
354 | ||
f3dc3630 | 355 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 356 | { |
468e67f6 | 357 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
358 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
359 | true, false); | |
360 | u8 bit = BIT(off % BANK_SZ); | |
53661f3b | 361 | int ret; |
9e60fdcf | 362 | |
6e20fb18 | 363 | mutex_lock(&chip->i2c_lock); |
0f25fda8 | 364 | ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); |
6e20fb18 RS |
365 | mutex_unlock(&chip->i2c_lock); |
366 | return ret; | |
9e60fdcf | 367 | } |
368 | ||
f3dc3630 | 369 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 370 | unsigned off, int val) |
371 | { | |
468e67f6 | 372 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
373 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
374 | true, false); | |
ec82d1eb MV |
375 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
376 | true, false); | |
0f25fda8 | 377 | u8 bit = BIT(off % BANK_SZ); |
53661f3b | 378 | int ret; |
9e60fdcf | 379 | |
6e20fb18 | 380 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 381 | /* set output level */ |
ec82d1eb | 382 | ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
9e60fdcf | 383 | if (ret) |
6e20fb18 | 384 | goto exit; |
9e60fdcf | 385 | |
9e60fdcf | 386 | /* then direction */ |
0f25fda8 | 387 | ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); |
6e20fb18 RS |
388 | exit: |
389 | mutex_unlock(&chip->i2c_lock); | |
390 | return ret; | |
9e60fdcf | 391 | } |
392 | ||
f3dc3630 | 393 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 394 | { |
468e67f6 | 395 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
87813cf3 MV |
396 | u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, |
397 | true, false); | |
398 | u8 bit = BIT(off % BANK_SZ); | |
ae79c190 | 399 | u32 reg_val; |
53661f3b | 400 | int ret; |
9e60fdcf | 401 | |
6e20fb18 | 402 | mutex_lock(&chip->i2c_lock); |
87813cf3 | 403 | ret = regmap_read(chip->regmap, inreg, ®_val); |
6e20fb18 | 404 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 405 | if (ret < 0) { |
406 | /* NOTE: diagnostic already emitted; that's all we should | |
407 | * do unless gpio_*_value_cansleep() calls become different | |
408 | * from their nonsleeping siblings (and report faults). | |
409 | */ | |
410 | return 0; | |
411 | } | |
412 | ||
87813cf3 | 413 | return !!(reg_val & bit); |
9e60fdcf | 414 | } |
415 | ||
f3dc3630 | 416 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 417 | { |
468e67f6 | 418 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ec82d1eb MV |
419 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
420 | true, false); | |
421 | u8 bit = BIT(off % BANK_SZ); | |
9e60fdcf | 422 | |
6e20fb18 | 423 | mutex_lock(&chip->i2c_lock); |
ec82d1eb | 424 | regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
6e20fb18 | 425 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 426 | } |
427 | ||
66e57192 AS |
428 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
429 | { | |
430 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
0f25fda8 MV |
431 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
432 | true, false); | |
433 | u8 bit = BIT(off % BANK_SZ); | |
66e57192 AS |
434 | u32 reg_val; |
435 | int ret; | |
436 | ||
437 | mutex_lock(&chip->i2c_lock); | |
0f25fda8 | 438 | ret = regmap_read(chip->regmap, dirreg, ®_val); |
66e57192 AS |
439 | mutex_unlock(&chip->i2c_lock); |
440 | if (ret < 0) | |
441 | return ret; | |
442 | ||
0f25fda8 | 443 | return !!(reg_val & bit); |
66e57192 AS |
444 | } |
445 | ||
b4818afe | 446 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 447 | unsigned long *mask, unsigned long *bits) |
b4818afe | 448 | { |
468e67f6 | 449 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d | 450 | unsigned int bank_mask, bank_val; |
873d1e8e | 451 | int bank; |
b4818afe | 452 | u8 reg_val[MAX_BANK]; |
53661f3b | 453 | int ret; |
ea3d579d | 454 | |
b4818afe | 455 | mutex_lock(&chip->i2c_lock); |
ec82d1eb MV |
456 | ret = pca953x_read_regs(chip, chip->regs->output, reg_val); |
457 | if (ret) | |
458 | goto exit; | |
459 | ||
ea3d579d BG |
460 | for (bank = 0; bank < NBANK(chip); bank++) { |
461 | bank_mask = mask[bank / sizeof(*mask)] >> | |
462 | ((bank % sizeof(*mask)) * 8); | |
463 | if (bank_mask) { | |
464 | bank_val = bits[bank / sizeof(*bits)] >> | |
465 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 466 | bank_val &= bank_mask; |
ea3d579d | 467 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
468 | } |
469 | } | |
ea3d579d | 470 | |
ec82d1eb | 471 | pca953x_write_regs(chip, chip->regs->output, reg_val); |
b4818afe PR |
472 | exit: |
473 | mutex_unlock(&chip->i2c_lock); | |
474 | } | |
475 | ||
f5e8ff48 | 476 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 477 | { |
478 | struct gpio_chip *gc; | |
479 | ||
480 | gc = &chip->gpio_chip; | |
481 | ||
f3dc3630 GL |
482 | gc->direction_input = pca953x_gpio_direction_input; |
483 | gc->direction_output = pca953x_gpio_direction_output; | |
484 | gc->get = pca953x_gpio_get_value; | |
485 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 486 | gc->get_direction = pca953x_gpio_get_direction; |
b4818afe | 487 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 488 | gc->can_sleep = true; |
9e60fdcf | 489 | |
490 | gc->base = chip->gpio_start; | |
f5e8ff48 | 491 | gc->ngpio = gpios; |
5128f8d4 | 492 | gc->label = dev_name(&chip->client->dev); |
58383c78 | 493 | gc->parent = &chip->client->dev; |
d72cbed0 | 494 | gc->owner = THIS_MODULE; |
77906a54 | 495 | gc->names = chip->names; |
9e60fdcf | 496 | } |
497 | ||
89ea8bbe | 498 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 499 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 500 | { |
7bcbce55 | 501 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 502 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 503 | |
f5f0b7aa | 504 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
505 | } |
506 | ||
6f5cfc0e | 507 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 508 | { |
7bcbce55 | 509 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 510 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 511 | |
f5f0b7aa | 512 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
513 | } |
514 | ||
6f5cfc0e | 515 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 516 | { |
7bcbce55 | 517 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 518 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
519 | |
520 | mutex_lock(&chip->irq_lock); | |
521 | } | |
522 | ||
6f5cfc0e | 523 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 524 | { |
7bcbce55 | 525 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 526 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
527 | u8 new_irqs; |
528 | int level, i; | |
44896bea | 529 | u8 invert_irq_mask[MAX_BANK]; |
0f25fda8 MV |
530 | int reg_direction[MAX_BANK]; |
531 | ||
532 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, | |
533 | NBANK(chip)); | |
44896bea YL |
534 | |
535 | if (chip->driver_data & PCA_PCAL) { | |
536 | /* Enable latch on interrupt-enabled inputs */ | |
537 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
538 | ||
539 | for (i = 0; i < NBANK(chip); i++) | |
540 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
541 | ||
542 | /* Unmask enabled interrupts */ | |
543 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
544 | } | |
a2cb9aeb MZ |
545 | |
546 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
547 | for (i = 0; i < NBANK(chip); i++) { |
548 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
0f25fda8 | 549 | new_irqs &= reg_direction[i]; |
f5f0b7aa GC |
550 | |
551 | while (new_irqs) { | |
552 | level = __ffs(new_irqs); | |
553 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
554 | level + (BANK_SZ * i)); | |
555 | new_irqs &= ~(1 << level); | |
556 | } | |
a2cb9aeb | 557 | } |
89ea8bbe MZ |
558 | |
559 | mutex_unlock(&chip->irq_lock); | |
560 | } | |
561 | ||
6f5cfc0e | 562 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 563 | { |
7bcbce55 | 564 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 565 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
566 | int bank_nb = d->hwirq / BANK_SZ; |
567 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
568 | |
569 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
570 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 571 | d->irq, type); |
89ea8bbe MZ |
572 | return -EINVAL; |
573 | } | |
574 | ||
575 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 576 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 577 | else |
f5f0b7aa | 578 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
579 | |
580 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 581 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 582 | else |
f5f0b7aa | 583 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 584 | |
a2cb9aeb | 585 | return 0; |
89ea8bbe MZ |
586 | } |
587 | ||
0a70fe00 GD |
588 | static void pca953x_irq_shutdown(struct irq_data *d) |
589 | { | |
590 | struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); | |
591 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
592 | ||
593 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | |
594 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | |
595 | } | |
596 | ||
89ea8bbe MZ |
597 | static struct irq_chip pca953x_irq_chip = { |
598 | .name = "pca953x", | |
6f5cfc0e LB |
599 | .irq_mask = pca953x_irq_mask, |
600 | .irq_unmask = pca953x_irq_unmask, | |
601 | .irq_bus_lock = pca953x_irq_bus_lock, | |
602 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
603 | .irq_set_type = pca953x_irq_set_type, | |
0a70fe00 | 604 | .irq_shutdown = pca953x_irq_shutdown, |
89ea8bbe MZ |
605 | }; |
606 | ||
b6ac1280 | 607 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 608 | { |
f5f0b7aa GC |
609 | u8 cur_stat[MAX_BANK]; |
610 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
611 | bool pending_seen = false; |
612 | bool trigger_seen = false; | |
613 | u8 trigger[MAX_BANK]; | |
0f25fda8 | 614 | int reg_direction[MAX_BANK]; |
53661f3b | 615 | int ret, i; |
33226ffd | 616 | |
44896bea YL |
617 | if (chip->driver_data & PCA_PCAL) { |
618 | /* Read the current interrupt status from the device */ | |
619 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
620 | if (ret) | |
621 | return false; | |
622 | ||
623 | /* Check latched inputs and clear interrupt status */ | |
624 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
625 | if (ret) | |
626 | return false; | |
627 | ||
628 | for (i = 0; i < NBANK(chip); i++) { | |
629 | /* Apply filter for rising/falling edge selection */ | |
630 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
631 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
632 | pending[i] &= trigger[i]; | |
633 | if (pending[i]) | |
634 | pending_seen = true; | |
635 | } | |
636 | ||
637 | return pending_seen; | |
638 | } | |
639 | ||
53661f3b | 640 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 641 | if (ret) |
b6ac1280 | 642 | return false; |
89ea8bbe MZ |
643 | |
644 | /* Remove output pins from the equation */ | |
0f25fda8 MV |
645 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, |
646 | NBANK(chip)); | |
f5f0b7aa | 647 | for (i = 0; i < NBANK(chip); i++) |
0f25fda8 | 648 | cur_stat[i] &= reg_direction[i]; |
89ea8bbe | 649 | |
f5f0b7aa | 650 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 651 | |
f5f0b7aa GC |
652 | for (i = 0; i < NBANK(chip); i++) { |
653 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
654 | if (trigger[i]) |
655 | trigger_seen = true; | |
f5f0b7aa GC |
656 | } |
657 | ||
b6ac1280 JS |
658 | if (!trigger_seen) |
659 | return false; | |
89ea8bbe | 660 | |
f5f0b7aa | 661 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 662 | |
f5f0b7aa GC |
663 | for (i = 0; i < NBANK(chip); i++) { |
664 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
665 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
666 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
667 | if (pending[i]) |
668 | pending_seen = true; | |
f5f0b7aa | 669 | } |
89ea8bbe | 670 | |
b6ac1280 | 671 | return pending_seen; |
89ea8bbe MZ |
672 | } |
673 | ||
674 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
675 | { | |
676 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
677 | u8 pending[MAX_BANK]; |
678 | u8 level; | |
3275d072 | 679 | unsigned nhandled = 0; |
f5f0b7aa | 680 | int i; |
89ea8bbe | 681 | |
f5f0b7aa | 682 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 683 | return IRQ_NONE; |
89ea8bbe | 684 | |
f5f0b7aa GC |
685 | for (i = 0; i < NBANK(chip); i++) { |
686 | while (pending[i]) { | |
687 | level = __ffs(pending[i]); | |
f0fbe7bc | 688 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
f5f0b7aa GC |
689 | level + (BANK_SZ * i))); |
690 | pending[i] &= ~(1 << level); | |
3275d072 | 691 | nhandled++; |
f5f0b7aa GC |
692 | } |
693 | } | |
89ea8bbe | 694 | |
3275d072 | 695 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
696 | } |
697 | ||
698 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 699 | int irq_base) |
89ea8bbe MZ |
700 | { |
701 | struct i2c_client *client = chip->client; | |
0f25fda8 | 702 | int reg_direction[MAX_BANK]; |
53661f3b | 703 | int ret, i; |
89ea8bbe | 704 | |
4bb93349 | 705 | if (client->irq && irq_base != -1 |
c6664149 | 706 | && (chip->driver_data & PCA_INT)) { |
53661f3b BG |
707 | ret = pca953x_read_regs(chip, |
708 | chip->regs->input, chip->irq_stat); | |
89ea8bbe | 709 | if (ret) |
b42748c9 | 710 | return ret; |
89ea8bbe MZ |
711 | |
712 | /* | |
713 | * There is no way to know which GPIO line generated the | |
714 | * interrupt. We have to rely on the previous read for | |
715 | * this purpose. | |
716 | */ | |
0f25fda8 MV |
717 | regmap_bulk_read(chip->regmap, chip->regs->direction, |
718 | reg_direction, NBANK(chip)); | |
f5f0b7aa | 719 | for (i = 0; i < NBANK(chip); i++) |
0f25fda8 | 720 | chip->irq_stat[i] &= reg_direction[i]; |
89ea8bbe MZ |
721 | mutex_init(&chip->irq_lock); |
722 | ||
b42748c9 LW |
723 | ret = devm_request_threaded_irq(&client->dev, |
724 | client->irq, | |
89ea8bbe MZ |
725 | NULL, |
726 | pca953x_irq_handler, | |
91329132 TS |
727 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
728 | IRQF_SHARED, | |
89ea8bbe MZ |
729 | dev_name(&client->dev), chip); |
730 | if (ret) { | |
731 | dev_err(&client->dev, "failed to request irq %d\n", | |
732 | client->irq); | |
0e8f2fda | 733 | return ret; |
89ea8bbe MZ |
734 | } |
735 | ||
d245b3f9 LW |
736 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, |
737 | &pca953x_irq_chip, | |
738 | irq_base, | |
739 | handle_simple_irq, | |
740 | IRQ_TYPE_NONE); | |
7bcbce55 LW |
741 | if (ret) { |
742 | dev_err(&client->dev, | |
743 | "could not connect irqchip to gpiochip\n"); | |
744 | return ret; | |
745 | } | |
fdd50409 | 746 | |
d245b3f9 LW |
747 | gpiochip_set_nested_irqchip(&chip->gpio_chip, |
748 | &pca953x_irq_chip, | |
749 | client->irq); | |
89ea8bbe MZ |
750 | } |
751 | ||
752 | return 0; | |
89ea8bbe MZ |
753 | } |
754 | ||
89ea8bbe MZ |
755 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
756 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 757 | int irq_base) |
89ea8bbe MZ |
758 | { |
759 | struct i2c_client *client = chip->client; | |
89ea8bbe | 760 | |
72b38caf | 761 | if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
762 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
763 | ||
764 | return 0; | |
765 | } | |
89ea8bbe MZ |
766 | #endif |
767 | ||
7a04aaa3 | 768 | static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
769 | { |
770 | int ret; | |
f5f0b7aa | 771 | u8 val[MAX_BANK]; |
33226ffd | 772 | |
ec82d1eb MV |
773 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
774 | chip->regs->output + NBANK(chip)); | |
775 | if (ret != 0) | |
33226ffd HZ |
776 | goto out; |
777 | ||
0f25fda8 MV |
778 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
779 | chip->regs->direction + NBANK(chip)); | |
780 | if (ret != 0) | |
33226ffd HZ |
781 | goto out; |
782 | ||
783 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
784 | if (invert) |
785 | memset(val, 0xFF, NBANK(chip)); | |
786 | else | |
787 | memset(val, 0, NBANK(chip)); | |
788 | ||
7a04aaa3 | 789 | ret = pca953x_write_regs(chip, chip->regs->invert, val); |
33226ffd HZ |
790 | out: |
791 | return ret; | |
792 | } | |
793 | ||
3836309d | 794 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
795 | { |
796 | int ret; | |
f5f0b7aa | 797 | u8 val[MAX_BANK]; |
33226ffd | 798 | |
7a04aaa3 | 799 | ret = device_pca95xx_init(chip, invert); |
c75a3772 NK |
800 | if (ret) |
801 | goto out; | |
33226ffd | 802 | |
20a8a968 | 803 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 804 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
805 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
806 | if (ret) | |
807 | goto out; | |
33226ffd HZ |
808 | |
809 | return 0; | |
810 | out: | |
811 | return ret; | |
812 | } | |
813 | ||
6f29c9af BD |
814 | static const struct of_device_id pca953x_dt_ids[]; |
815 | ||
3836309d | 816 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 817 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 818 | { |
f3dc3630 GL |
819 | struct pca953x_platform_data *pdata; |
820 | struct pca953x_chip *chip; | |
6a7b36aa | 821 | int irq_base = 0; |
7ea2aa20 | 822 | int ret; |
6a7b36aa | 823 | u32 invert = 0; |
e23efa31 | 824 | struct regulator *reg; |
9e60fdcf | 825 | |
b42748c9 LW |
826 | chip = devm_kzalloc(&client->dev, |
827 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
828 | if (chip == NULL) |
829 | return -ENOMEM; | |
830 | ||
e56aee18 | 831 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
832 | if (pdata) { |
833 | irq_base = pdata->irq_base; | |
834 | chip->gpio_start = pdata->gpio_base; | |
835 | invert = pdata->invert; | |
836 | chip->names = pdata->names; | |
837 | } else { | |
054ccdef SL |
838 | struct gpio_desc *reset_gpio; |
839 | ||
4bb93349 MP |
840 | chip->gpio_start = -1; |
841 | irq_base = 0; | |
054ccdef | 842 | |
96530b37 AS |
843 | /* |
844 | * See if we need to de-assert a reset pin. | |
845 | * | |
846 | * There is no known ACPI-enabled platforms that are | |
847 | * using "reset" GPIO. Otherwise any of those platform | |
848 | * must use _DSD method with corresponding property. | |
849 | */ | |
054ccdef SL |
850 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
851 | GPIOD_OUT_LOW); | |
852 | if (IS_ERR(reset_gpio)) | |
853 | return PTR_ERR(reset_gpio); | |
1965d303 | 854 | } |
9e60fdcf | 855 | |
856 | chip->client = client; | |
857 | ||
e23efa31 PR |
858 | reg = devm_regulator_get(&client->dev, "vcc"); |
859 | if (IS_ERR(reg)) { | |
860 | ret = PTR_ERR(reg); | |
861 | if (ret != -EPROBE_DEFER) | |
862 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
863 | return ret; | |
864 | } | |
865 | ret = regulator_enable(reg); | |
866 | if (ret) { | |
867 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
868 | return ret; | |
869 | } | |
870 | chip->regulator = reg; | |
871 | ||
6212e1d6 WS |
872 | if (i2c_id) { |
873 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 874 | } else { |
6212e1d6 | 875 | const struct acpi_device_id *acpi_id; |
67bab935 | 876 | struct device *dev = &client->dev; |
f32517bf | 877 | |
67bab935 TR |
878 | chip->driver_data = (uintptr_t)of_device_get_match_data(dev); |
879 | if (!chip->driver_data) { | |
880 | acpi_id = acpi_match_device(pca953x_acpi_ids, dev); | |
87840a2b | 881 | if (!acpi_id) { |
e23efa31 PR |
882 | ret = -ENODEV; |
883 | goto err_exit; | |
884 | } | |
f32517bf | 885 | |
6212e1d6 | 886 | chip->driver_data = acpi_id->driver_data; |
6f29c9af | 887 | } |
f32517bf AS |
888 | } |
889 | ||
49427232 MV |
890 | i2c_set_clientdata(client, chip); |
891 | ||
892 | chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); | |
893 | if (IS_ERR(chip->regmap)) { | |
894 | ret = PTR_ERR(chip->regmap); | |
895 | goto err_exit; | |
896 | } | |
897 | ||
0f25fda8 MV |
898 | regcache_mark_dirty(chip->regmap); |
899 | ||
6e20fb18 | 900 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
901 | /* |
902 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
903 | * expander using the same driver higher on the device tree, read the | |
904 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
905 | * subclass for chip->i2c_lock. | |
906 | * | |
907 | * REVISIT: This solution is not complete. It protects us from lockdep | |
908 | * false positives when the expander controlling the i2c-mux is on | |
909 | * a different level on the device tree, but not when it's on the same | |
910 | * level on a different branch (in which case the subclass number | |
911 | * would be the same). | |
912 | * | |
913 | * TODO: Once a correct solution is developed, a similar fix should be | |
914 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
915 | * regmap-i2c). | |
916 | */ | |
559b4699 BG |
917 | lockdep_set_subclass(&chip->i2c_lock, |
918 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 919 | |
9e60fdcf | 920 | /* initialize cached registers from their original values. |
921 | * we can't share this chip with another i2c master. | |
922 | */ | |
c6664149 | 923 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 924 | |
7a04aaa3 MV |
925 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
926 | chip->regs = &pca953x_regs; | |
927 | ret = device_pca95xx_init(chip, invert); | |
7acc66e3 | 928 | } else { |
7a04aaa3 | 929 | chip->regs = &pca957x_regs; |
7ea2aa20 | 930 | ret = device_pca957x_init(chip, invert); |
7a04aaa3 | 931 | } |
7ea2aa20 | 932 | if (ret) |
e23efa31 | 933 | goto err_exit; |
9e60fdcf | 934 | |
0ece84f5 | 935 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 936 | if (ret) |
e23efa31 | 937 | goto err_exit; |
f5e8ff48 | 938 | |
c6664149 | 939 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 940 | if (ret) |
e23efa31 | 941 | goto err_exit; |
9e60fdcf | 942 | |
c6dcf592 | 943 | if (pdata && pdata->setup) { |
9e60fdcf | 944 | ret = pdata->setup(client, chip->gpio_chip.base, |
945 | chip->gpio_chip.ngpio, pdata->context); | |
946 | if (ret < 0) | |
947 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
948 | } | |
949 | ||
9e60fdcf | 950 | return 0; |
e23efa31 PR |
951 | |
952 | err_exit: | |
953 | regulator_disable(chip->regulator); | |
954 | return ret; | |
9e60fdcf | 955 | } |
956 | ||
f3dc3630 | 957 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 958 | { |
e56aee18 | 959 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 960 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 961 | int ret; |
9e60fdcf | 962 | |
c6dcf592 | 963 | if (pdata && pdata->teardown) { |
9e60fdcf | 964 | ret = pdata->teardown(client, chip->gpio_chip.base, |
965 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 966 | if (ret < 0) |
9e60fdcf | 967 | dev_err(&client->dev, "%s failed, %d\n", |
968 | "teardown", ret); | |
bf62efeb AB |
969 | } else { |
970 | ret = 0; | |
9e60fdcf | 971 | } |
972 | ||
e23efa31 PR |
973 | regulator_disable(chip->regulator); |
974 | ||
975 | return ret; | |
9e60fdcf | 976 | } |
977 | ||
b7657430 MV |
978 | #ifdef CONFIG_PM_SLEEP |
979 | static int pca953x_regcache_sync(struct device *dev) | |
980 | { | |
981 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
982 | int ret; | |
983 | ||
984 | /* | |
985 | * The ordering between direction and output is important, | |
986 | * sync these registers first and only then sync the rest. | |
987 | */ | |
988 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, | |
989 | chip->regs->direction + NBANK(chip)); | |
990 | if (ret != 0) { | |
991 | dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); | |
992 | return ret; | |
993 | } | |
994 | ||
995 | ret = regcache_sync_region(chip->regmap, chip->regs->output, | |
996 | chip->regs->output + NBANK(chip)); | |
997 | if (ret != 0) { | |
998 | dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); | |
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | #ifdef CONFIG_GPIO_PCA953X_IRQ | |
1003 | if (chip->driver_data & PCA_PCAL) { | |
1004 | ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, | |
1005 | PCAL953X_IN_LATCH + NBANK(chip)); | |
1006 | if (ret != 0) { | |
1007 | dev_err(dev, "Failed to sync INT latch registers: %d\n", | |
1008 | ret); | |
1009 | return ret; | |
1010 | } | |
1011 | ||
1012 | ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, | |
1013 | PCAL953X_INT_MASK + NBANK(chip)); | |
1014 | if (ret != 0) { | |
1015 | dev_err(dev, "Failed to sync INT mask registers: %d\n", | |
1016 | ret); | |
1017 | return ret; | |
1018 | } | |
1019 | } | |
1020 | #endif | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | static int pca953x_suspend(struct device *dev) | |
1026 | { | |
1027 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1028 | ||
1029 | regcache_cache_only(chip->regmap, true); | |
1030 | ||
1031 | regulator_disable(chip->regulator); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static int pca953x_resume(struct device *dev) | |
1037 | { | |
1038 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1039 | int ret; | |
1040 | ||
1041 | ret = regulator_enable(chip->regulator); | |
1042 | if (ret != 0) { | |
1043 | dev_err(dev, "Failed to enable regulator: %d\n", ret); | |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | regcache_cache_only(chip->regmap, false); | |
1048 | regcache_mark_dirty(chip->regmap); | |
1049 | ret = pca953x_regcache_sync(dev); | |
1050 | if (ret) | |
1051 | return ret; | |
1052 | ||
1053 | ret = regcache_sync(chip->regmap); | |
1054 | if (ret != 0) { | |
1055 | dev_err(dev, "Failed to restore register map: %d\n", ret); | |
1056 | return ret; | |
1057 | } | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | #endif | |
1062 | ||
6f29c9af BD |
1063 | /* convenience to stop overlong match-table lines */ |
1064 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
1065 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
1066 | ||
ed32620e | 1067 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
1068 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
1069 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
1070 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
1071 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
1072 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
1073 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
1074 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
1075 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
1076 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
1077 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
1078 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
1079 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
1080 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
1081 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
1082 | ||
0cdf21b3 NS |
1083 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
1084 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, | |
3a711e0d | 1085 | |
6f29c9af BD |
1086 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
1087 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
1088 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
1089 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 1090 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1091 | |
1092 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 1093 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
1094 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
1095 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
1096 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
1097 | ||
8a64e557 | 1098 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6f29c9af BD |
1099 | |
1100 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
1101 | { } |
1102 | }; | |
1103 | ||
1104 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
1105 | ||
b7657430 MV |
1106 | static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); |
1107 | ||
f3dc3630 | 1108 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 1109 | .driver = { |
f3dc3630 | 1110 | .name = "pca953x", |
b7657430 | 1111 | .pm = &pca953x_pm_ops, |
ed32620e | 1112 | .of_match_table = pca953x_dt_ids, |
f32517bf | 1113 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 1114 | }, |
f3dc3630 GL |
1115 | .probe = pca953x_probe, |
1116 | .remove = pca953x_remove, | |
3760f736 | 1117 | .id_table = pca953x_id, |
9e60fdcf | 1118 | }; |
1119 | ||
f3dc3630 | 1120 | static int __init pca953x_init(void) |
9e60fdcf | 1121 | { |
f3dc3630 | 1122 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 1123 | } |
2f8d1197 DB |
1124 | /* register after i2c postcore initcall and before |
1125 | * subsys initcalls that may rely on these GPIOs | |
1126 | */ | |
1127 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1128 | |
f3dc3630 | 1129 | static void __exit pca953x_exit(void) |
9e60fdcf | 1130 | { |
f3dc3630 | 1131 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1132 | } |
f3dc3630 | 1133 | module_exit(pca953x_exit); |
9e60fdcf | 1134 | |
1135 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1136 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1137 | MODULE_LICENSE("GPL"); |