Commit | Line | Data |
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b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9e60fdcf | 2 | /* |
1e191695 | 3 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 4 | * |
5 | * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> | |
6 | * Copyright (C) 2007 Marvell International Ltd. | |
7 | * | |
8 | * Derived from drivers/i2c/chips/pca9539.c | |
9e60fdcf | 9 | */ |
10 | ||
b413d7a0 | 11 | #include <linux/acpi.h> |
644f3da0 | 12 | #include <linux/gpio/driver.h> |
054ccdef | 13 | #include <linux/gpio/consumer.h> |
9e60fdcf | 14 | #include <linux/i2c.h> |
b413d7a0 AS |
15 | #include <linux/init.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of_platform.h> | |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
49427232 | 20 | #include <linux/regmap.h> |
b413d7a0 | 21 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
b413d7a0 | 23 | |
9b8e3ec3 | 24 | #include <asm/unaligned.h> |
9e60fdcf | 25 | |
0950c19a NS |
26 | #define PCA953X_INPUT 0x00 |
27 | #define PCA953X_OUTPUT 0x01 | |
28 | #define PCA953X_INVERT 0x02 | |
29 | #define PCA953X_DIRECTION 0x03 | |
33226ffd | 30 | |
49427232 MV |
31 | #define REG_ADDR_MASK 0x3f |
32 | #define REG_ADDR_EXT 0x40 | |
ae79c190 AS |
33 | #define REG_ADDR_AI 0x80 |
34 | ||
0950c19a NS |
35 | #define PCA957X_IN 0x00 |
36 | #define PCA957X_INVRT 0x01 | |
37 | #define PCA957X_BKEN 0x02 | |
38 | #define PCA957X_PUPD 0x03 | |
39 | #define PCA957X_CFG 0x04 | |
40 | #define PCA957X_OUT 0x05 | |
41 | #define PCA957X_MSK 0x06 | |
42 | #define PCA957X_INTS 0x07 | |
33226ffd | 43 | |
6315d231 | 44 | #define PCAL953X_OUT_STRENGTH 0x20 |
0950c19a | 45 | #define PCAL953X_IN_LATCH 0x22 |
6315d231 NS |
46 | #define PCAL953X_PULL_EN 0x23 |
47 | #define PCAL953X_PULL_SEL 0x24 | |
0950c19a NS |
48 | #define PCAL953X_INT_MASK 0x25 |
49 | #define PCAL953X_INT_STAT 0x26 | |
6315d231 | 50 | #define PCAL953X_OUT_CONF 0x27 |
44896bea | 51 | |
a0ecbccc NS |
52 | #define PCAL6524_INT_EDGE 0x28 |
53 | #define PCAL6524_INT_CLR 0x2a | |
54 | #define PCAL6524_IN_STATUS 0x2b | |
55 | #define PCAL6524_OUT_INDCONF 0x2c | |
56 | #define PCAL6524_DEBOUNCE 0x2d | |
57 | ||
33226ffd | 58 | #define PCA_GPIO_MASK 0x00FF |
394aeef8 NS |
59 | |
60 | #define PCAL_GPIO_MASK 0x1f | |
92f45ebe | 61 | #define PCAL_PINCTRL_MASK 0x60 |
394aeef8 | 62 | |
33226ffd | 63 | #define PCA_INT 0x0100 |
8c7a92da | 64 | #define PCA_PCAL 0x0200 |
2870b3c5 | 65 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
33226ffd HZ |
66 | #define PCA953X_TYPE 0x1000 |
67 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
68 | #define PCA_TYPE_MASK 0xF000 |
69 | ||
70 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 71 | |
3760f736 | 72 | static const struct i2c_device_id pca953x_id[] = { |
12c7a4fc | 73 | { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, |
89f5df01 | 74 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
75 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
76 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
77 | { "pca9536", 4 | PCA953X_TYPE, }, | |
78 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
79 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
80 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
81 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
82 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
83 | { "pca9556", 8 | PCA953X_TYPE, }, | |
84 | { "pca9557", 8 | PCA953X_TYPE, }, | |
85 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
86 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 87 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd | 88 | |
2870b3c5 AS |
89 | { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
90 | { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, | |
91 | { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, | |
747e42a1 | 92 | |
33226ffd HZ |
93 | { "max7310", 8 | PCA953X_TYPE, }, |
94 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
95 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
96 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
1208c935 | 97 | { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
98 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, |
99 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
100 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 101 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 102 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
1b9a0c25 | 103 | { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 104 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 105 | { } |
f5e8ff48 | 106 | }; |
3760f736 | 107 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 108 | |
f32517bf | 109 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
2870b3c5 | 110 | { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, |
f32517bf AS |
111 | { } |
112 | }; | |
113 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
114 | ||
f5f0b7aa GC |
115 | #define MAX_BANK 5 |
116 | #define BANK_SZ 8 | |
117 | ||
a246b819 | 118 | #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) |
f5f0b7aa | 119 | |
53661f3b BG |
120 | struct pca953x_reg_config { |
121 | int direction; | |
122 | int output; | |
123 | int input; | |
7a04aaa3 | 124 | int invert; |
53661f3b BG |
125 | }; |
126 | ||
127 | static const struct pca953x_reg_config pca953x_regs = { | |
128 | .direction = PCA953X_DIRECTION, | |
129 | .output = PCA953X_OUTPUT, | |
130 | .input = PCA953X_INPUT, | |
7a04aaa3 | 131 | .invert = PCA953X_INVERT, |
53661f3b BG |
132 | }; |
133 | ||
134 | static const struct pca953x_reg_config pca957x_regs = { | |
135 | .direction = PCA957X_CFG, | |
136 | .output = PCA957X_OUT, | |
137 | .input = PCA957X_IN, | |
7a04aaa3 | 138 | .invert = PCA957X_INVRT, |
53661f3b BG |
139 | }; |
140 | ||
f3dc3630 | 141 | struct pca953x_chip { |
9e60fdcf | 142 | unsigned gpio_start; |
6e20fb18 | 143 | struct mutex i2c_lock; |
49427232 | 144 | struct regmap *regmap; |
9e60fdcf | 145 | |
89ea8bbe MZ |
146 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
147 | struct mutex irq_lock; | |
f5f0b7aa GC |
148 | u8 irq_mask[MAX_BANK]; |
149 | u8 irq_stat[MAX_BANK]; | |
150 | u8 irq_trig_raise[MAX_BANK]; | |
151 | u8 irq_trig_fall[MAX_BANK]; | |
5c4fee63 | 152 | struct irq_chip irq_chip; |
89ea8bbe | 153 | #endif |
f70fbc15 | 154 | atomic_t wakeup_path; |
89ea8bbe | 155 | |
9e60fdcf | 156 | struct i2c_client *client; |
157 | struct gpio_chip gpio_chip; | |
62154991 | 158 | const char *const *names; |
c6664149 | 159 | unsigned long driver_data; |
e23efa31 | 160 | struct regulator *regulator; |
53661f3b BG |
161 | |
162 | const struct pca953x_reg_config *regs; | |
9e60fdcf | 163 | }; |
164 | ||
873d1e8e | 165 | static int pca953x_bank_shift(struct pca953x_chip *chip) |
f5f0b7aa | 166 | { |
873d1e8e MV |
167 | return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); |
168 | } | |
f5f0b7aa | 169 | |
49427232 MV |
170 | #define PCA953x_BANK_INPUT BIT(0) |
171 | #define PCA953x_BANK_OUTPUT BIT(1) | |
172 | #define PCA953x_BANK_POLARITY BIT(2) | |
173 | #define PCA953x_BANK_CONFIG BIT(3) | |
f5f0b7aa | 174 | |
49427232 MV |
175 | #define PCA957x_BANK_INPUT BIT(0) |
176 | #define PCA957x_BANK_POLARITY BIT(1) | |
177 | #define PCA957x_BANK_BUSHOLD BIT(2) | |
178 | #define PCA957x_BANK_CONFIG BIT(4) | |
179 | #define PCA957x_BANK_OUTPUT BIT(5) | |
180 | ||
181 | #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) | |
15add068 TP |
182 | #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) |
183 | #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) | |
49427232 MV |
184 | #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) |
185 | #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) | |
186 | ||
187 | /* | |
188 | * We care about the following registers: | |
189 | * - Standard set, below 0x40, each port can be replicated up to 8 times | |
190 | * - PCA953x standard | |
191 | * Input port 0x00 + 0 * bank_size R | |
192 | * Output port 0x00 + 1 * bank_size RW | |
193 | * Polarity Inversion port 0x00 + 2 * bank_size RW | |
194 | * Configuration port 0x00 + 3 * bank_size RW | |
195 | * - PCA957x with mixed up registers | |
196 | * Input port 0x00 + 0 * bank_size R | |
197 | * Polarity Inversion port 0x00 + 1 * bank_size RW | |
198 | * Bus hold port 0x00 + 2 * bank_size RW | |
199 | * Configuration port 0x00 + 4 * bank_size RW | |
200 | * Output port 0x00 + 5 * bank_size RW | |
201 | * | |
202 | * - Extended set, above 0x40, often chip specific. | |
203 | * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: | |
204 | * Input latch register 0x40 + 2 * bank_size RW | |
15add068 TP |
205 | * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW |
206 | * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW | |
49427232 MV |
207 | * Interrupt mask register 0x40 + 5 * bank_size RW |
208 | * Interrupt status register 0x40 + 6 * bank_size R | |
209 | * | |
210 | * - Registers with bit 0x80 set, the AI bit | |
211 | * The bit is cleared and the registers fall into one of the | |
212 | * categories above. | |
213 | */ | |
214 | ||
215 | static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, | |
216 | u32 checkbank) | |
217 | { | |
218 | int bank_shift = pca953x_bank_shift(chip); | |
219 | int bank = (reg & REG_ADDR_MASK) >> bank_shift; | |
220 | int offset = reg & (BIT(bank_shift) - 1); | |
221 | ||
222 | /* Special PCAL extended register check. */ | |
223 | if (reg & REG_ADDR_EXT) { | |
224 | if (!(chip->driver_data & PCA_PCAL)) | |
225 | return false; | |
226 | bank += 8; | |
f5f0b7aa GC |
227 | } |
228 | ||
49427232 MV |
229 | /* Register is not in the matching bank. */ |
230 | if (!(BIT(bank) & checkbank)) | |
231 | return false; | |
232 | ||
233 | /* Register is not within allowed range of bank. */ | |
234 | if (offset >= NBANK(chip)) | |
235 | return false; | |
236 | ||
237 | return true; | |
f5f0b7aa GC |
238 | } |
239 | ||
49427232 | 240 | static bool pca953x_readable_register(struct device *dev, unsigned int reg) |
f5f0b7aa | 241 | { |
49427232 MV |
242 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
243 | u32 bank; | |
f5f0b7aa | 244 | |
49427232 MV |
245 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
246 | bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | | |
247 | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; | |
248 | } else { | |
249 | bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | | |
250 | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | | |
251 | PCA957x_BANK_BUSHOLD; | |
252 | } | |
f5f0b7aa | 253 | |
49427232 | 254 | if (chip->driver_data & PCA_PCAL) { |
15add068 TP |
255 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | |
256 | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | | |
49427232 | 257 | PCAL9xxx_BANK_IRQ_STAT; |
f5f0b7aa GC |
258 | } |
259 | ||
49427232 | 260 | return pca953x_check_register(chip, reg, bank); |
f5f0b7aa GC |
261 | } |
262 | ||
49427232 | 263 | static bool pca953x_writeable_register(struct device *dev, unsigned int reg) |
9e60fdcf | 264 | { |
49427232 MV |
265 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
266 | u32 bank; | |
f5e8ff48 | 267 | |
49427232 MV |
268 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
269 | bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | | |
270 | PCA953x_BANK_CONFIG; | |
271 | } else { | |
272 | bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | | |
273 | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; | |
274 | } | |
c4d1cbd7 | 275 | |
49427232 | 276 | if (chip->driver_data & PCA_PCAL) |
15add068 TP |
277 | bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | |
278 | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; | |
49427232 MV |
279 | |
280 | return pca953x_check_register(chip, reg, bank); | |
7acc66e3 BG |
281 | } |
282 | ||
49427232 | 283 | static bool pca953x_volatile_register(struct device *dev, unsigned int reg) |
7acc66e3 | 284 | { |
49427232 MV |
285 | struct pca953x_chip *chip = dev_get_drvdata(dev); |
286 | u32 bank; | |
7acc66e3 | 287 | |
49427232 MV |
288 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) |
289 | bank = PCA953x_BANK_INPUT; | |
290 | else | |
291 | bank = PCA957x_BANK_INPUT; | |
292 | ||
293 | if (chip->driver_data & PCA_PCAL) | |
294 | bank |= PCAL9xxx_BANK_IRQ_STAT; | |
7acc66e3 | 295 | |
49427232 | 296 | return pca953x_check_register(chip, reg, bank); |
7acc66e3 | 297 | } |
f5e8ff48 | 298 | |
d04e779f | 299 | static const struct regmap_config pca953x_i2c_regmap = { |
49427232 MV |
300 | .reg_bits = 8, |
301 | .val_bits = 8, | |
302 | ||
303 | .readable_reg = pca953x_readable_register, | |
304 | .writeable_reg = pca953x_writeable_register, | |
305 | .volatile_reg = pca953x_volatile_register, | |
306 | ||
307 | .cache_type = REGCACHE_RBTREE, | |
3b00691c NS |
308 | /* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */ |
309 | .max_register = 0xff, | |
49427232 MV |
310 | }; |
311 | ||
b32cecb4 MV |
312 | static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, |
313 | bool write, bool addrinc) | |
7acc66e3 | 314 | { |
b32cecb4 | 315 | int bank_shift = pca953x_bank_shift(chip); |
d5dbf9c2 NS |
316 | int addr = (reg & PCAL_GPIO_MASK) << bank_shift; |
317 | int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; | |
b32cecb4 MV |
318 | u8 regaddr = pinctrl | addr | (off / BANK_SZ); |
319 | ||
320 | /* Single byte read doesn't need AI bit set. */ | |
321 | if (!addrinc) | |
322 | return regaddr; | |
323 | ||
324 | /* Chips with 24 and more GPIOs always support Auto Increment */ | |
325 | if (write && NBANK(chip) > 2) | |
326 | regaddr |= REG_ADDR_AI; | |
7acc66e3 | 327 | |
b32cecb4 MV |
328 | /* PCA9575 needs address-increment on multi-byte writes */ |
329 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) | |
330 | regaddr |= REG_ADDR_AI; | |
331 | ||
332 | return regaddr; | |
7acc66e3 BG |
333 | } |
334 | ||
335 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
336 | { | |
b32cecb4 | 337 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); |
90adb097 | 338 | int ret; |
7acc66e3 | 339 | |
49427232 | 340 | ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); |
f5e8ff48 GL |
341 | if (ret < 0) { |
342 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 343 | return ret; |
f5e8ff48 GL |
344 | } |
345 | ||
346 | return 0; | |
9e60fdcf | 347 | } |
348 | ||
c6e3cf01 BG |
349 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
350 | { | |
b32cecb4 | 351 | u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); |
c6e3cf01 BG |
352 | int ret; |
353 | ||
49427232 | 354 | ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); |
9e60fdcf | 355 | if (ret < 0) { |
356 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 357 | return ret; |
9e60fdcf | 358 | } |
359 | ||
9e60fdcf | 360 | return 0; |
361 | } | |
362 | ||
f3dc3630 | 363 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 364 | { |
468e67f6 | 365 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
366 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
367 | true, false); | |
368 | u8 bit = BIT(off % BANK_SZ); | |
53661f3b | 369 | int ret; |
9e60fdcf | 370 | |
6e20fb18 | 371 | mutex_lock(&chip->i2c_lock); |
0f25fda8 | 372 | ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); |
6e20fb18 RS |
373 | mutex_unlock(&chip->i2c_lock); |
374 | return ret; | |
9e60fdcf | 375 | } |
376 | ||
f3dc3630 | 377 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 378 | unsigned off, int val) |
379 | { | |
468e67f6 | 380 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
0f25fda8 MV |
381 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
382 | true, false); | |
ec82d1eb MV |
383 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
384 | true, false); | |
0f25fda8 | 385 | u8 bit = BIT(off % BANK_SZ); |
53661f3b | 386 | int ret; |
9e60fdcf | 387 | |
6e20fb18 | 388 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 389 | /* set output level */ |
ec82d1eb | 390 | ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
9e60fdcf | 391 | if (ret) |
6e20fb18 | 392 | goto exit; |
9e60fdcf | 393 | |
9e60fdcf | 394 | /* then direction */ |
0f25fda8 | 395 | ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); |
6e20fb18 RS |
396 | exit: |
397 | mutex_unlock(&chip->i2c_lock); | |
398 | return ret; | |
9e60fdcf | 399 | } |
400 | ||
f3dc3630 | 401 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 402 | { |
468e67f6 | 403 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
87813cf3 MV |
404 | u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, |
405 | true, false); | |
406 | u8 bit = BIT(off % BANK_SZ); | |
ae79c190 | 407 | u32 reg_val; |
53661f3b | 408 | int ret; |
9e60fdcf | 409 | |
6e20fb18 | 410 | mutex_lock(&chip->i2c_lock); |
87813cf3 | 411 | ret = regmap_read(chip->regmap, inreg, ®_val); |
6e20fb18 | 412 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 413 | if (ret < 0) { |
414 | /* NOTE: diagnostic already emitted; that's all we should | |
415 | * do unless gpio_*_value_cansleep() calls become different | |
416 | * from their nonsleeping siblings (and report faults). | |
417 | */ | |
418 | return 0; | |
419 | } | |
420 | ||
87813cf3 | 421 | return !!(reg_val & bit); |
9e60fdcf | 422 | } |
423 | ||
f3dc3630 | 424 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 425 | { |
468e67f6 | 426 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ec82d1eb MV |
427 | u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, |
428 | true, false); | |
429 | u8 bit = BIT(off % BANK_SZ); | |
9e60fdcf | 430 | |
6e20fb18 | 431 | mutex_lock(&chip->i2c_lock); |
ec82d1eb | 432 | regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); |
6e20fb18 | 433 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 434 | } |
435 | ||
66e57192 AS |
436 | static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) |
437 | { | |
438 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
0f25fda8 MV |
439 | u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, |
440 | true, false); | |
441 | u8 bit = BIT(off % BANK_SZ); | |
66e57192 AS |
442 | u32 reg_val; |
443 | int ret; | |
444 | ||
445 | mutex_lock(&chip->i2c_lock); | |
0f25fda8 | 446 | ret = regmap_read(chip->regmap, dirreg, ®_val); |
66e57192 AS |
447 | mutex_unlock(&chip->i2c_lock); |
448 | if (ret < 0) | |
449 | return ret; | |
450 | ||
0f25fda8 | 451 | return !!(reg_val & bit); |
66e57192 AS |
452 | } |
453 | ||
b4818afe | 454 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, |
ea3d579d | 455 | unsigned long *mask, unsigned long *bits) |
b4818afe | 456 | { |
468e67f6 | 457 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ea3d579d | 458 | unsigned int bank_mask, bank_val; |
873d1e8e | 459 | int bank; |
b4818afe | 460 | u8 reg_val[MAX_BANK]; |
53661f3b | 461 | int ret; |
ea3d579d | 462 | |
b4818afe | 463 | mutex_lock(&chip->i2c_lock); |
ec82d1eb MV |
464 | ret = pca953x_read_regs(chip, chip->regs->output, reg_val); |
465 | if (ret) | |
466 | goto exit; | |
467 | ||
ea3d579d BG |
468 | for (bank = 0; bank < NBANK(chip); bank++) { |
469 | bank_mask = mask[bank / sizeof(*mask)] >> | |
470 | ((bank % sizeof(*mask)) * 8); | |
471 | if (bank_mask) { | |
472 | bank_val = bits[bank / sizeof(*bits)] >> | |
473 | ((bank % sizeof(*bits)) * 8); | |
53f8d322 | 474 | bank_val &= bank_mask; |
ea3d579d | 475 | reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; |
b4818afe PR |
476 | } |
477 | } | |
ea3d579d | 478 | |
ec82d1eb | 479 | pca953x_write_regs(chip, chip->regs->output, reg_val); |
b4818afe PR |
480 | exit: |
481 | mutex_unlock(&chip->i2c_lock); | |
482 | } | |
483 | ||
15add068 TP |
484 | static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, |
485 | unsigned int offset, | |
486 | unsigned long config) | |
487 | { | |
488 | u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset, | |
489 | true, false); | |
490 | u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset, | |
491 | true, false); | |
492 | u8 bit = BIT(offset % BANK_SZ); | |
493 | int ret; | |
494 | ||
495 | /* | |
496 | * pull-up/pull-down configuration requires PCAL extended | |
497 | * registers | |
498 | */ | |
499 | if (!(chip->driver_data & PCA_PCAL)) | |
500 | return -ENOTSUPP; | |
501 | ||
502 | mutex_lock(&chip->i2c_lock); | |
503 | ||
504 | /* Disable pull-up/pull-down */ | |
505 | ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); | |
506 | if (ret) | |
507 | goto exit; | |
508 | ||
509 | /* Configure pull-up/pull-down */ | |
510 | if (config == PIN_CONFIG_BIAS_PULL_UP) | |
511 | ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); | |
512 | else if (config == PIN_CONFIG_BIAS_PULL_DOWN) | |
513 | ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); | |
514 | if (ret) | |
515 | goto exit; | |
516 | ||
517 | /* Enable pull-up/pull-down */ | |
518 | ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); | |
519 | ||
520 | exit: | |
521 | mutex_unlock(&chip->i2c_lock); | |
522 | return ret; | |
523 | } | |
524 | ||
525 | static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, | |
526 | unsigned long config) | |
527 | { | |
528 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
529 | ||
530 | switch (config) { | |
531 | case PIN_CONFIG_BIAS_PULL_UP: | |
532 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
533 | return pca953x_gpio_set_pull_up_down(chip, offset, config); | |
534 | default: | |
535 | return -ENOTSUPP; | |
536 | } | |
537 | } | |
538 | ||
f5e8ff48 | 539 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 540 | { |
541 | struct gpio_chip *gc; | |
542 | ||
543 | gc = &chip->gpio_chip; | |
544 | ||
f3dc3630 GL |
545 | gc->direction_input = pca953x_gpio_direction_input; |
546 | gc->direction_output = pca953x_gpio_direction_output; | |
547 | gc->get = pca953x_gpio_get_value; | |
548 | gc->set = pca953x_gpio_set_value; | |
66e57192 | 549 | gc->get_direction = pca953x_gpio_get_direction; |
b4818afe | 550 | gc->set_multiple = pca953x_gpio_set_multiple; |
15add068 | 551 | gc->set_config = pca953x_gpio_set_config; |
9fb1f39e | 552 | gc->can_sleep = true; |
9e60fdcf | 553 | |
554 | gc->base = chip->gpio_start; | |
f5e8ff48 | 555 | gc->ngpio = gpios; |
5128f8d4 | 556 | gc->label = dev_name(&chip->client->dev); |
58383c78 | 557 | gc->parent = &chip->client->dev; |
d72cbed0 | 558 | gc->owner = THIS_MODULE; |
77906a54 | 559 | gc->names = chip->names; |
9e60fdcf | 560 | } |
561 | ||
89ea8bbe | 562 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 563 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 564 | { |
7bcbce55 | 565 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 566 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 567 | |
f5f0b7aa | 568 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
569 | } |
570 | ||
6f5cfc0e | 571 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 572 | { |
7bcbce55 | 573 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 574 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 575 | |
f5f0b7aa | 576 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
577 | } |
578 | ||
2a9a2f27 GU |
579 | static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) |
580 | { | |
581 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
582 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
583 | ||
f70fbc15 GU |
584 | if (on) |
585 | atomic_inc(&chip->wakeup_path); | |
586 | else | |
587 | atomic_dec(&chip->wakeup_path); | |
588 | ||
2a9a2f27 GU |
589 | return irq_set_irq_wake(chip->client->irq, on); |
590 | } | |
591 | ||
6f5cfc0e | 592 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 593 | { |
7bcbce55 | 594 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 595 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
596 | |
597 | mutex_lock(&chip->irq_lock); | |
598 | } | |
599 | ||
6f5cfc0e | 600 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 601 | { |
7bcbce55 | 602 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 603 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
604 | u8 new_irqs; |
605 | int level, i; | |
44896bea | 606 | u8 invert_irq_mask[MAX_BANK]; |
0f25fda8 MV |
607 | int reg_direction[MAX_BANK]; |
608 | ||
609 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, | |
610 | NBANK(chip)); | |
44896bea YL |
611 | |
612 | if (chip->driver_data & PCA_PCAL) { | |
613 | /* Enable latch on interrupt-enabled inputs */ | |
614 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
615 | ||
616 | for (i = 0; i < NBANK(chip); i++) | |
617 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
618 | ||
619 | /* Unmask enabled interrupts */ | |
620 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
621 | } | |
a2cb9aeb MZ |
622 | |
623 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
624 | for (i = 0; i < NBANK(chip); i++) { |
625 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
0f25fda8 | 626 | new_irqs &= reg_direction[i]; |
f5f0b7aa GC |
627 | |
628 | while (new_irqs) { | |
629 | level = __ffs(new_irqs); | |
630 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
631 | level + (BANK_SZ * i)); | |
632 | new_irqs &= ~(1 << level); | |
633 | } | |
a2cb9aeb | 634 | } |
89ea8bbe MZ |
635 | |
636 | mutex_unlock(&chip->irq_lock); | |
637 | } | |
638 | ||
6f5cfc0e | 639 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 640 | { |
7bcbce55 | 641 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 642 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
643 | int bank_nb = d->hwirq / BANK_SZ; |
644 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
645 | |
646 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
647 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 648 | d->irq, type); |
89ea8bbe MZ |
649 | return -EINVAL; |
650 | } | |
651 | ||
652 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 653 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 654 | else |
f5f0b7aa | 655 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
656 | |
657 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 658 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 659 | else |
f5f0b7aa | 660 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 661 | |
a2cb9aeb | 662 | return 0; |
89ea8bbe MZ |
663 | } |
664 | ||
0a70fe00 GD |
665 | static void pca953x_irq_shutdown(struct irq_data *d) |
666 | { | |
c378b3aa MW |
667 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
668 | struct pca953x_chip *chip = gpiochip_get_data(gc); | |
0a70fe00 GD |
669 | u8 mask = 1 << (d->hwirq % BANK_SZ); |
670 | ||
671 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | |
672 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | |
673 | } | |
674 | ||
b6ac1280 | 675 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 676 | { |
f5f0b7aa GC |
677 | u8 cur_stat[MAX_BANK]; |
678 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
679 | bool pending_seen = false; |
680 | bool trigger_seen = false; | |
681 | u8 trigger[MAX_BANK]; | |
0f25fda8 | 682 | int reg_direction[MAX_BANK]; |
53661f3b | 683 | int ret, i; |
33226ffd | 684 | |
44896bea YL |
685 | if (chip->driver_data & PCA_PCAL) { |
686 | /* Read the current interrupt status from the device */ | |
687 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
688 | if (ret) | |
689 | return false; | |
690 | ||
691 | /* Check latched inputs and clear interrupt status */ | |
692 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
693 | if (ret) | |
694 | return false; | |
695 | ||
696 | for (i = 0; i < NBANK(chip); i++) { | |
697 | /* Apply filter for rising/falling edge selection */ | |
698 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
699 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
700 | pending[i] &= trigger[i]; | |
701 | if (pending[i]) | |
702 | pending_seen = true; | |
703 | } | |
704 | ||
705 | return pending_seen; | |
706 | } | |
707 | ||
53661f3b | 708 | ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); |
89ea8bbe | 709 | if (ret) |
b6ac1280 | 710 | return false; |
89ea8bbe MZ |
711 | |
712 | /* Remove output pins from the equation */ | |
0f25fda8 MV |
713 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, |
714 | NBANK(chip)); | |
f5f0b7aa | 715 | for (i = 0; i < NBANK(chip); i++) |
0f25fda8 | 716 | cur_stat[i] &= reg_direction[i]; |
89ea8bbe | 717 | |
f5f0b7aa | 718 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 719 | |
f5f0b7aa GC |
720 | for (i = 0; i < NBANK(chip); i++) { |
721 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
722 | if (trigger[i]) |
723 | trigger_seen = true; | |
f5f0b7aa GC |
724 | } |
725 | ||
b6ac1280 JS |
726 | if (!trigger_seen) |
727 | return false; | |
89ea8bbe | 728 | |
f5f0b7aa | 729 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 730 | |
f5f0b7aa GC |
731 | for (i = 0; i < NBANK(chip); i++) { |
732 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
733 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
734 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
735 | if (pending[i]) |
736 | pending_seen = true; | |
f5f0b7aa | 737 | } |
89ea8bbe | 738 | |
b6ac1280 | 739 | return pending_seen; |
89ea8bbe MZ |
740 | } |
741 | ||
742 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
743 | { | |
744 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
745 | u8 pending[MAX_BANK]; |
746 | u8 level; | |
3275d072 | 747 | unsigned nhandled = 0; |
f5f0b7aa | 748 | int i; |
89ea8bbe | 749 | |
f5f0b7aa | 750 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 751 | return IRQ_NONE; |
89ea8bbe | 752 | |
f5f0b7aa GC |
753 | for (i = 0; i < NBANK(chip); i++) { |
754 | while (pending[i]) { | |
755 | level = __ffs(pending[i]); | |
f0fbe7bc | 756 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
f5f0b7aa GC |
757 | level + (BANK_SZ * i))); |
758 | pending[i] &= ~(1 << level); | |
3275d072 | 759 | nhandled++; |
f5f0b7aa GC |
760 | } |
761 | } | |
89ea8bbe | 762 | |
3275d072 | 763 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
764 | } |
765 | ||
766 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 767 | int irq_base) |
89ea8bbe MZ |
768 | { |
769 | struct i2c_client *client = chip->client; | |
5c4fee63 | 770 | struct irq_chip *irq_chip = &chip->irq_chip; |
0f25fda8 | 771 | int reg_direction[MAX_BANK]; |
53661f3b | 772 | int ret, i; |
89ea8bbe | 773 | |
7341fa7a TP |
774 | if (!client->irq) |
775 | return 0; | |
89ea8bbe | 776 | |
7341fa7a TP |
777 | if (irq_base == -1) |
778 | return 0; | |
89ea8bbe | 779 | |
7341fa7a TP |
780 | if (!(chip->driver_data & PCA_INT)) |
781 | return 0; | |
fdd50409 | 782 | |
7341fa7a TP |
783 | ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat); |
784 | if (ret) | |
785 | return ret; | |
786 | ||
787 | /* | |
788 | * There is no way to know which GPIO line generated the | |
789 | * interrupt. We have to rely on the previous read for | |
790 | * this purpose. | |
791 | */ | |
792 | regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, | |
793 | NBANK(chip)); | |
794 | for (i = 0; i < NBANK(chip); i++) | |
795 | chip->irq_stat[i] &= reg_direction[i]; | |
796 | mutex_init(&chip->irq_lock); | |
797 | ||
798 | ret = devm_request_threaded_irq(&client->dev, client->irq, | |
799 | NULL, pca953x_irq_handler, | |
800 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | | |
801 | IRQF_SHARED, | |
802 | dev_name(&client->dev), chip); | |
803 | if (ret) { | |
804 | dev_err(&client->dev, "failed to request irq %d\n", | |
805 | client->irq); | |
806 | return ret; | |
89ea8bbe MZ |
807 | } |
808 | ||
5c4fee63 TP |
809 | irq_chip->name = dev_name(&chip->client->dev); |
810 | irq_chip->irq_mask = pca953x_irq_mask; | |
811 | irq_chip->irq_unmask = pca953x_irq_unmask; | |
2a9a2f27 | 812 | irq_chip->irq_set_wake = pca953x_irq_set_wake; |
5c4fee63 TP |
813 | irq_chip->irq_bus_lock = pca953x_irq_bus_lock; |
814 | irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; | |
815 | irq_chip->irq_set_type = pca953x_irq_set_type; | |
816 | irq_chip->irq_shutdown = pca953x_irq_shutdown; | |
817 | ||
818 | ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip, | |
7341fa7a TP |
819 | irq_base, handle_simple_irq, |
820 | IRQ_TYPE_NONE); | |
821 | if (ret) { | |
822 | dev_err(&client->dev, | |
823 | "could not connect irqchip to gpiochip\n"); | |
824 | return ret; | |
825 | } | |
826 | ||
5c4fee63 | 827 | gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq); |
7341fa7a | 828 | |
89ea8bbe | 829 | return 0; |
89ea8bbe MZ |
830 | } |
831 | ||
89ea8bbe MZ |
832 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
833 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 834 | int irq_base) |
89ea8bbe MZ |
835 | { |
836 | struct i2c_client *client = chip->client; | |
89ea8bbe | 837 | |
72b38caf | 838 | if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
839 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
840 | ||
841 | return 0; | |
842 | } | |
89ea8bbe MZ |
843 | #endif |
844 | ||
7a04aaa3 | 845 | static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
846 | { |
847 | int ret; | |
f5f0b7aa | 848 | u8 val[MAX_BANK]; |
33226ffd | 849 | |
ec82d1eb MV |
850 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
851 | chip->regs->output + NBANK(chip)); | |
852 | if (ret != 0) | |
33226ffd HZ |
853 | goto out; |
854 | ||
0f25fda8 MV |
855 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
856 | chip->regs->direction + NBANK(chip)); | |
857 | if (ret != 0) | |
33226ffd HZ |
858 | goto out; |
859 | ||
860 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
861 | if (invert) |
862 | memset(val, 0xFF, NBANK(chip)); | |
863 | else | |
864 | memset(val, 0, NBANK(chip)); | |
865 | ||
7a04aaa3 | 866 | ret = pca953x_write_regs(chip, chip->regs->invert, val); |
33226ffd HZ |
867 | out: |
868 | return ret; | |
869 | } | |
870 | ||
3836309d | 871 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
872 | { |
873 | int ret; | |
f5f0b7aa | 874 | u8 val[MAX_BANK]; |
33226ffd | 875 | |
7a04aaa3 | 876 | ret = device_pca95xx_init(chip, invert); |
c75a3772 NK |
877 | if (ret) |
878 | goto out; | |
33226ffd | 879 | |
20a8a968 | 880 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 881 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
882 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
883 | if (ret) | |
884 | goto out; | |
33226ffd HZ |
885 | |
886 | return 0; | |
887 | out: | |
888 | return ret; | |
889 | } | |
890 | ||
6f29c9af BD |
891 | static const struct of_device_id pca953x_dt_ids[]; |
892 | ||
3836309d | 893 | static int pca953x_probe(struct i2c_client *client, |
6212e1d6 | 894 | const struct i2c_device_id *i2c_id) |
9e60fdcf | 895 | { |
f3dc3630 GL |
896 | struct pca953x_platform_data *pdata; |
897 | struct pca953x_chip *chip; | |
6a7b36aa | 898 | int irq_base = 0; |
7ea2aa20 | 899 | int ret; |
6a7b36aa | 900 | u32 invert = 0; |
e23efa31 | 901 | struct regulator *reg; |
9e60fdcf | 902 | |
b42748c9 LW |
903 | chip = devm_kzalloc(&client->dev, |
904 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
905 | if (chip == NULL) |
906 | return -ENOMEM; | |
907 | ||
e56aee18 | 908 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
909 | if (pdata) { |
910 | irq_base = pdata->irq_base; | |
911 | chip->gpio_start = pdata->gpio_base; | |
912 | invert = pdata->invert; | |
913 | chip->names = pdata->names; | |
914 | } else { | |
054ccdef SL |
915 | struct gpio_desc *reset_gpio; |
916 | ||
4bb93349 MP |
917 | chip->gpio_start = -1; |
918 | irq_base = 0; | |
054ccdef | 919 | |
96530b37 AS |
920 | /* |
921 | * See if we need to de-assert a reset pin. | |
922 | * | |
923 | * There is no known ACPI-enabled platforms that are | |
924 | * using "reset" GPIO. Otherwise any of those platform | |
925 | * must use _DSD method with corresponding property. | |
926 | */ | |
054ccdef SL |
927 | reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", |
928 | GPIOD_OUT_LOW); | |
929 | if (IS_ERR(reset_gpio)) | |
930 | return PTR_ERR(reset_gpio); | |
1965d303 | 931 | } |
9e60fdcf | 932 | |
933 | chip->client = client; | |
934 | ||
e23efa31 PR |
935 | reg = devm_regulator_get(&client->dev, "vcc"); |
936 | if (IS_ERR(reg)) { | |
937 | ret = PTR_ERR(reg); | |
938 | if (ret != -EPROBE_DEFER) | |
939 | dev_err(&client->dev, "reg get err: %d\n", ret); | |
940 | return ret; | |
941 | } | |
942 | ret = regulator_enable(reg); | |
943 | if (ret) { | |
944 | dev_err(&client->dev, "reg en err: %d\n", ret); | |
945 | return ret; | |
946 | } | |
947 | chip->regulator = reg; | |
948 | ||
6212e1d6 WS |
949 | if (i2c_id) { |
950 | chip->driver_data = i2c_id->driver_data; | |
f32517bf | 951 | } else { |
6212e1d6 | 952 | const struct acpi_device_id *acpi_id; |
67bab935 | 953 | struct device *dev = &client->dev; |
f32517bf | 954 | |
67bab935 TR |
955 | chip->driver_data = (uintptr_t)of_device_get_match_data(dev); |
956 | if (!chip->driver_data) { | |
957 | acpi_id = acpi_match_device(pca953x_acpi_ids, dev); | |
87840a2b | 958 | if (!acpi_id) { |
e23efa31 PR |
959 | ret = -ENODEV; |
960 | goto err_exit; | |
961 | } | |
f32517bf | 962 | |
6212e1d6 | 963 | chip->driver_data = acpi_id->driver_data; |
6f29c9af | 964 | } |
f32517bf AS |
965 | } |
966 | ||
49427232 MV |
967 | i2c_set_clientdata(client, chip); |
968 | ||
969 | chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); | |
970 | if (IS_ERR(chip->regmap)) { | |
971 | ret = PTR_ERR(chip->regmap); | |
972 | goto err_exit; | |
973 | } | |
974 | ||
0f25fda8 MV |
975 | regcache_mark_dirty(chip->regmap); |
976 | ||
6e20fb18 | 977 | mutex_init(&chip->i2c_lock); |
74f47f07 BG |
978 | /* |
979 | * In case we have an i2c-mux controlled by a GPIO provided by an | |
980 | * expander using the same driver higher on the device tree, read the | |
981 | * i2c adapter nesting depth and use the retrieved value as lockdep | |
982 | * subclass for chip->i2c_lock. | |
983 | * | |
984 | * REVISIT: This solution is not complete. It protects us from lockdep | |
985 | * false positives when the expander controlling the i2c-mux is on | |
986 | * a different level on the device tree, but not when it's on the same | |
987 | * level on a different branch (in which case the subclass number | |
988 | * would be the same). | |
989 | * | |
990 | * TODO: Once a correct solution is developed, a similar fix should be | |
991 | * applied to all other i2c-controlled GPIO expanders (and potentially | |
992 | * regmap-i2c). | |
993 | */ | |
559b4699 BG |
994 | lockdep_set_subclass(&chip->i2c_lock, |
995 | i2c_adapter_depth(client->adapter)); | |
6e20fb18 | 996 | |
9e60fdcf | 997 | /* initialize cached registers from their original values. |
998 | * we can't share this chip with another i2c master. | |
999 | */ | |
c6664149 | 1000 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 1001 | |
7a04aaa3 MV |
1002 | if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { |
1003 | chip->regs = &pca953x_regs; | |
1004 | ret = device_pca95xx_init(chip, invert); | |
7acc66e3 | 1005 | } else { |
7a04aaa3 | 1006 | chip->regs = &pca957x_regs; |
7ea2aa20 | 1007 | ret = device_pca957x_init(chip, invert); |
7a04aaa3 | 1008 | } |
7ea2aa20 | 1009 | if (ret) |
e23efa31 | 1010 | goto err_exit; |
9e60fdcf | 1011 | |
0ece84f5 | 1012 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 1013 | if (ret) |
e23efa31 | 1014 | goto err_exit; |
f5e8ff48 | 1015 | |
c6664149 | 1016 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 1017 | if (ret) |
e23efa31 | 1018 | goto err_exit; |
9e60fdcf | 1019 | |
c6dcf592 | 1020 | if (pdata && pdata->setup) { |
9e60fdcf | 1021 | ret = pdata->setup(client, chip->gpio_chip.base, |
1022 | chip->gpio_chip.ngpio, pdata->context); | |
1023 | if (ret < 0) | |
1024 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
1025 | } | |
1026 | ||
9e60fdcf | 1027 | return 0; |
e23efa31 PR |
1028 | |
1029 | err_exit: | |
1030 | regulator_disable(chip->regulator); | |
1031 | return ret; | |
9e60fdcf | 1032 | } |
1033 | ||
f3dc3630 | 1034 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 1035 | { |
e56aee18 | 1036 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 1037 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
d147d548 | 1038 | int ret; |
9e60fdcf | 1039 | |
c6dcf592 | 1040 | if (pdata && pdata->teardown) { |
9e60fdcf | 1041 | ret = pdata->teardown(client, chip->gpio_chip.base, |
1042 | chip->gpio_chip.ngpio, pdata->context); | |
e23efa31 | 1043 | if (ret < 0) |
9e60fdcf | 1044 | dev_err(&client->dev, "%s failed, %d\n", |
1045 | "teardown", ret); | |
bf62efeb AB |
1046 | } else { |
1047 | ret = 0; | |
9e60fdcf | 1048 | } |
1049 | ||
e23efa31 PR |
1050 | regulator_disable(chip->regulator); |
1051 | ||
1052 | return ret; | |
9e60fdcf | 1053 | } |
1054 | ||
b7657430 MV |
1055 | #ifdef CONFIG_PM_SLEEP |
1056 | static int pca953x_regcache_sync(struct device *dev) | |
1057 | { | |
1058 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1059 | int ret; | |
1060 | ||
1061 | /* | |
1062 | * The ordering between direction and output is important, | |
1063 | * sync these registers first and only then sync the rest. | |
1064 | */ | |
1065 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, | |
1066 | chip->regs->direction + NBANK(chip)); | |
1067 | if (ret != 0) { | |
1068 | dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); | |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | ret = regcache_sync_region(chip->regmap, chip->regs->output, | |
1073 | chip->regs->output + NBANK(chip)); | |
1074 | if (ret != 0) { | |
1075 | dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); | |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | #ifdef CONFIG_GPIO_PCA953X_IRQ | |
1080 | if (chip->driver_data & PCA_PCAL) { | |
1081 | ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, | |
1082 | PCAL953X_IN_LATCH + NBANK(chip)); | |
1083 | if (ret != 0) { | |
1084 | dev_err(dev, "Failed to sync INT latch registers: %d\n", | |
1085 | ret); | |
1086 | return ret; | |
1087 | } | |
1088 | ||
1089 | ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, | |
1090 | PCAL953X_INT_MASK + NBANK(chip)); | |
1091 | if (ret != 0) { | |
1092 | dev_err(dev, "Failed to sync INT mask registers: %d\n", | |
1093 | ret); | |
1094 | return ret; | |
1095 | } | |
1096 | } | |
1097 | #endif | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int pca953x_suspend(struct device *dev) | |
1103 | { | |
1104 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1105 | ||
1106 | regcache_cache_only(chip->regmap, true); | |
1107 | ||
f70fbc15 GU |
1108 | if (atomic_read(&chip->wakeup_path)) |
1109 | device_set_wakeup_path(dev); | |
1110 | else | |
1111 | regulator_disable(chip->regulator); | |
b7657430 MV |
1112 | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | static int pca953x_resume(struct device *dev) | |
1117 | { | |
1118 | struct pca953x_chip *chip = dev_get_drvdata(dev); | |
1119 | int ret; | |
1120 | ||
f70fbc15 GU |
1121 | if (!atomic_read(&chip->wakeup_path)) { |
1122 | ret = regulator_enable(chip->regulator); | |
1123 | if (ret != 0) { | |
1124 | dev_err(dev, "Failed to enable regulator: %d\n", ret); | |
1125 | return 0; | |
1126 | } | |
b7657430 MV |
1127 | } |
1128 | ||
1129 | regcache_cache_only(chip->regmap, false); | |
1130 | regcache_mark_dirty(chip->regmap); | |
1131 | ret = pca953x_regcache_sync(dev); | |
1132 | if (ret) | |
1133 | return ret; | |
1134 | ||
1135 | ret = regcache_sync(chip->regmap); | |
1136 | if (ret != 0) { | |
1137 | dev_err(dev, "Failed to restore register map: %d\n", ret); | |
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | #endif | |
1144 | ||
6f29c9af BD |
1145 | /* convenience to stop overlong match-table lines */ |
1146 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
1147 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
1148 | ||
ed32620e | 1149 | static const struct of_device_id pca953x_dt_ids[] = { |
12c7a4fc | 1150 | { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1151 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
1152 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
1153 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
1154 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
1155 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
1156 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
1157 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
1158 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
1159 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
1160 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
1161 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
1162 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
1163 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
1164 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
1165 | ||
01769c47 | 1166 | { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, |
0cdf21b3 NS |
1167 | { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, |
1168 | { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, | |
3a711e0d | 1169 | |
6f29c9af BD |
1170 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, |
1171 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
1172 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
1173 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
1208c935 | 1174 | { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, |
6f29c9af BD |
1175 | |
1176 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
353661df | 1177 | { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, |
6f29c9af BD |
1178 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, |
1179 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
1180 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
8b74ae41 | 1181 | { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, |
6f29c9af | 1182 | |
932002f0 | 1183 | { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, |
8a64e557 | 1184 | { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, |
6f29c9af BD |
1185 | |
1186 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
1187 | { } |
1188 | }; | |
1189 | ||
1190 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
1191 | ||
b7657430 MV |
1192 | static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); |
1193 | ||
f3dc3630 | 1194 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 1195 | .driver = { |
f3dc3630 | 1196 | .name = "pca953x", |
b7657430 | 1197 | .pm = &pca953x_pm_ops, |
ed32620e | 1198 | .of_match_table = pca953x_dt_ids, |
f32517bf | 1199 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 1200 | }, |
f3dc3630 GL |
1201 | .probe = pca953x_probe, |
1202 | .remove = pca953x_remove, | |
3760f736 | 1203 | .id_table = pca953x_id, |
9e60fdcf | 1204 | }; |
1205 | ||
f3dc3630 | 1206 | static int __init pca953x_init(void) |
9e60fdcf | 1207 | { |
f3dc3630 | 1208 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 1209 | } |
2f8d1197 DB |
1210 | /* register after i2c postcore initcall and before |
1211 | * subsys initcalls that may rely on these GPIOs | |
1212 | */ | |
1213 | subsys_initcall(pca953x_init); | |
9e60fdcf | 1214 | |
f3dc3630 | 1215 | static void __exit pca953x_exit(void) |
9e60fdcf | 1216 | { |
f3dc3630 | 1217 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 1218 | } |
f3dc3630 | 1219 | module_exit(pca953x_exit); |
9e60fdcf | 1220 | |
1221 | MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); | |
f3dc3630 | 1222 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 1223 | MODULE_LICENSE("GPL"); |