Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/irqdomain.h> | |
de88cbb7 | 28 | #include <linux/irqchip/chained_irq.h> |
4b25408f TL |
29 | #include <linux/gpio.h> |
30 | #include <linux/platform_data/gpio-omap.h> | |
5e1c5ff4 | 31 | |
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
5e1c5ff4 | 54 | u16 irq; |
384ebe1c | 55 | struct irq_domain *domain; |
3ac4fa99 JY |
56 | u32 non_wakeup_gpios; |
57 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 58 | struct gpio_regs context; |
3ac4fa99 | 59 | u32 saved_datain; |
b144ff6f | 60 | u32 level_mask; |
4318f36b | 61 | u32 toggle_mask; |
5e1c5ff4 | 62 | spinlock_t lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
72f83af9 | 67 | bool dbck_enabled; |
77640aab | 68 | struct device *dev; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
2dc983c5 TKD |
75 | int power_mode; |
76 | bool workaround_enabled; | |
fa87931a KH |
77 | |
78 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 79 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
80 | |
81 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
82 | }; |
83 | ||
129fd223 KH |
84 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
85 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 86 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 87 | |
25db711d BC |
88 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
89 | { | |
ede4d7a5 JH |
90 | return bank->chip.base + gpio_irq; |
91 | } | |
92 | ||
93 | static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
94 | { | |
95 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); | |
96 | ||
97 | return irq_find_mapping(bank->domain, offset); | |
25db711d BC |
98 | } |
99 | ||
5e1c5ff4 TL |
100 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
101 | { | |
92105bb7 | 102 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
103 | u32 l; |
104 | ||
fa87931a | 105 | reg += bank->regs->direction; |
5e1c5ff4 TL |
106 | l = __raw_readl(reg); |
107 | if (is_input) | |
108 | l |= 1 << gpio; | |
109 | else | |
110 | l &= ~(1 << gpio); | |
111 | __raw_writel(l, reg); | |
41d87cbd | 112 | bank->context.oe = l; |
5e1c5ff4 TL |
113 | } |
114 | ||
fa87931a KH |
115 | |
116 | /* set data out value using dedicate set/clear register */ | |
117 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 118 | { |
92105bb7 | 119 | void __iomem *reg = bank->base; |
fa87931a | 120 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 121 | |
2c836f7e | 122 | if (enable) { |
fa87931a | 123 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
124 | bank->context.dataout |= l; |
125 | } else { | |
fa87931a | 126 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
127 | bank->context.dataout &= ~l; |
128 | } | |
5e1c5ff4 | 129 | |
5e1c5ff4 TL |
130 | __raw_writel(l, reg); |
131 | } | |
132 | ||
fa87931a KH |
133 | /* set data out value using mask register */ |
134 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 135 | { |
fa87931a KH |
136 | void __iomem *reg = bank->base + bank->regs->dataout; |
137 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
138 | u32 l; | |
5e1c5ff4 | 139 | |
fa87931a KH |
140 | l = __raw_readl(reg); |
141 | if (enable) | |
142 | l |= gpio_bit; | |
143 | else | |
144 | l &= ~gpio_bit; | |
5e1c5ff4 | 145 | __raw_writel(l, reg); |
41d87cbd | 146 | bank->context.dataout = l; |
5e1c5ff4 TL |
147 | } |
148 | ||
7fcca715 | 149 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 150 | { |
fa87931a | 151 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 152 | |
7fcca715 | 153 | return (__raw_readl(reg) & (1 << offset)) != 0; |
5e1c5ff4 | 154 | } |
b37c45b8 | 155 | |
7fcca715 | 156 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 157 | { |
fa87931a | 158 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 159 | |
7fcca715 | 160 | return (__raw_readl(reg) & (1 << offset)) != 0; |
b37c45b8 RQ |
161 | } |
162 | ||
ece9528e KH |
163 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
164 | { | |
165 | int l = __raw_readl(base + reg); | |
166 | ||
862ff640 | 167 | if (set) |
ece9528e KH |
168 | l |= mask; |
169 | else | |
170 | l &= ~mask; | |
171 | ||
172 | __raw_writel(l, base + reg); | |
173 | } | |
92105bb7 | 174 | |
72f83af9 TKD |
175 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
176 | { | |
177 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
178 | clk_enable(bank->dbck); | |
179 | bank->dbck_enabled = true; | |
9e303f22 GI |
180 | |
181 | __raw_writel(bank->dbck_enable_mask, | |
182 | bank->base + bank->regs->debounce_en); | |
72f83af9 TKD |
183 | } |
184 | } | |
185 | ||
186 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
187 | { | |
188 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
189 | /* |
190 | * Disable debounce before cutting it's clock. If debounce is | |
191 | * enabled but the clock is not, GPIO module seems to be unable | |
192 | * to detect events and generate interrupts at least on OMAP3. | |
193 | */ | |
194 | __raw_writel(0, bank->base + bank->regs->debounce_en); | |
195 | ||
72f83af9 TKD |
196 | clk_disable(bank->dbck); |
197 | bank->dbck_enabled = false; | |
198 | } | |
199 | } | |
200 | ||
168ef3d9 FB |
201 | /** |
202 | * _set_gpio_debounce - low level gpio debounce time | |
203 | * @bank: the gpio bank we're acting upon | |
204 | * @gpio: the gpio number on this @gpio | |
205 | * @debounce: debounce time to use | |
206 | * | |
207 | * OMAP's debounce time is in 31us steps so we need | |
208 | * to convert and round up to the closest unit. | |
209 | */ | |
210 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
211 | unsigned debounce) | |
212 | { | |
9942da0e | 213 | void __iomem *reg; |
168ef3d9 FB |
214 | u32 val; |
215 | u32 l; | |
216 | ||
77640aab VC |
217 | if (!bank->dbck_flag) |
218 | return; | |
219 | ||
168ef3d9 FB |
220 | if (debounce < 32) |
221 | debounce = 0x01; | |
222 | else if (debounce > 7936) | |
223 | debounce = 0xff; | |
224 | else | |
225 | debounce = (debounce / 0x1f) - 1; | |
226 | ||
129fd223 | 227 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 228 | |
6fd9c421 | 229 | clk_enable(bank->dbck); |
9942da0e | 230 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
231 | __raw_writel(debounce, reg); |
232 | ||
9942da0e | 233 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
234 | val = __raw_readl(reg); |
235 | ||
6fd9c421 | 236 | if (debounce) |
168ef3d9 | 237 | val |= l; |
6fd9c421 | 238 | else |
168ef3d9 | 239 | val &= ~l; |
f7ec0b0b | 240 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
241 | |
242 | __raw_writel(val, reg); | |
6fd9c421 TKD |
243 | clk_disable(bank->dbck); |
244 | /* | |
245 | * Enable debounce clock per module. | |
246 | * This call is mandatory because in omap_gpio_request() when | |
247 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
248 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
249 | * used within _gpio_dbck_enable() is still not initialized at | |
250 | * that point. Therefore we have to enable dbck here. | |
251 | */ | |
252 | _gpio_dbck_enable(bank); | |
ae547354 NM |
253 | if (bank->dbck_enable_mask) { |
254 | bank->context.debounce = debounce; | |
255 | bank->context.debounce_en = val; | |
256 | } | |
168ef3d9 FB |
257 | } |
258 | ||
c9c55d92 JH |
259 | /** |
260 | * _clear_gpio_debounce - clear debounce settings for a gpio | |
261 | * @bank: the gpio bank we're acting upon | |
262 | * @gpio: the gpio number on this @gpio | |
263 | * | |
264 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
265 | * this is the only gpio in this bank using debounce, then clear the debounce | |
266 | * time too. The debounce clock will also be disabled when calling this function | |
267 | * if this is the only gpio in the bank using debounce. | |
268 | */ | |
269 | static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | |
270 | { | |
271 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
272 | ||
273 | if (!bank->dbck_flag) | |
274 | return; | |
275 | ||
276 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
277 | return; | |
278 | ||
279 | bank->dbck_enable_mask &= ~gpio_bit; | |
280 | bank->context.debounce_en &= ~gpio_bit; | |
281 | __raw_writel(bank->context.debounce_en, | |
282 | bank->base + bank->regs->debounce_en); | |
283 | ||
284 | if (!bank->dbck_enable_mask) { | |
285 | bank->context.debounce = 0; | |
286 | __raw_writel(bank->context.debounce, bank->base + | |
287 | bank->regs->debounce); | |
288 | clk_disable(bank->dbck); | |
289 | bank->dbck_enabled = false; | |
290 | } | |
291 | } | |
292 | ||
5e571f38 | 293 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 294 | unsigned trigger) |
5e1c5ff4 | 295 | { |
3ac4fa99 | 296 | void __iomem *base = bank->base; |
92105bb7 TL |
297 | u32 gpio_bit = 1 << gpio; |
298 | ||
5e571f38 TKD |
299 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
300 | trigger & IRQ_TYPE_LEVEL_LOW); | |
301 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
302 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
303 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
304 | trigger & IRQ_TYPE_EDGE_RISING); | |
305 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
306 | trigger & IRQ_TYPE_EDGE_FALLING); | |
307 | ||
41d87cbd TKD |
308 | bank->context.leveldetect0 = |
309 | __raw_readl(bank->base + bank->regs->leveldetect0); | |
310 | bank->context.leveldetect1 = | |
311 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
312 | bank->context.risingdetect = | |
313 | __raw_readl(bank->base + bank->regs->risingdetect); | |
314 | bank->context.fallingdetect = | |
315 | __raw_readl(bank->base + bank->regs->fallingdetect); | |
316 | ||
317 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 318 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd TKD |
319 | bank->context.wake_en = |
320 | __raw_readl(bank->base + bank->regs->wkup_en); | |
321 | } | |
5e571f38 | 322 | |
55b220ca | 323 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
324 | if (!bank->regs->irqctrl) { |
325 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
326 | if (bank->non_wakeup_gpios) { | |
327 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
328 | goto exit; | |
329 | } | |
330 | ||
699117a6 CW |
331 | /* |
332 | * Log the edge gpio and manually trigger the IRQ | |
333 | * after resume if the input level changes | |
334 | * to avoid irq lost during PER RET/OFF mode | |
335 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
336 | */ | |
337 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
338 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
339 | else | |
340 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
341 | } | |
5eb3bb9c | 342 | |
5e571f38 | 343 | exit: |
9ea14d8c TKD |
344 | bank->level_mask = |
345 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
346 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
347 | } |
348 | ||
9198bcd3 | 349 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
350 | /* |
351 | * This only applies to chips that can't do both rising and falling edge | |
352 | * detection at once. For all other chips, this function is a noop. | |
353 | */ | |
354 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
355 | { | |
356 | void __iomem *reg = bank->base; | |
357 | u32 l = 0; | |
358 | ||
5e571f38 | 359 | if (!bank->regs->irqctrl) |
4318f36b | 360 | return; |
5e571f38 TKD |
361 | |
362 | reg += bank->regs->irqctrl; | |
4318f36b CM |
363 | |
364 | l = __raw_readl(reg); | |
365 | if ((l >> gpio) & 1) | |
366 | l &= ~(1 << gpio); | |
367 | else | |
368 | l |= 1 << gpio; | |
369 | ||
370 | __raw_writel(l, reg); | |
371 | } | |
5e571f38 TKD |
372 | #else |
373 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 374 | #endif |
4318f36b | 375 | |
00ece7e4 TKD |
376 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, |
377 | unsigned trigger) | |
92105bb7 TL |
378 | { |
379 | void __iomem *reg = bank->base; | |
5e571f38 | 380 | void __iomem *base = bank->base; |
92105bb7 | 381 | u32 l = 0; |
5e1c5ff4 | 382 | |
5e571f38 TKD |
383 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
384 | set_gpio_trigger(bank, gpio, trigger); | |
385 | } else if (bank->regs->irqctrl) { | |
386 | reg += bank->regs->irqctrl; | |
387 | ||
5e1c5ff4 | 388 | l = __raw_readl(reg); |
29501577 | 389 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 390 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 391 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 392 | l |= 1 << gpio; |
6cab4860 | 393 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 394 | l &= ~(1 << gpio); |
92105bb7 | 395 | else |
5e571f38 TKD |
396 | return -EINVAL; |
397 | ||
398 | __raw_writel(l, reg); | |
399 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 400 | if (gpio & 0x08) |
5e571f38 | 401 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 402 | else |
5e571f38 TKD |
403 | reg += bank->regs->edgectrl1; |
404 | ||
5e1c5ff4 TL |
405 | gpio &= 0x07; |
406 | l = __raw_readl(reg); | |
407 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 408 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 409 | l |= 2 << (gpio << 1); |
6cab4860 | 410 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 411 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
412 | |
413 | /* Enable wake-up during idle for dynamic tick */ | |
414 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd TKD |
415 | bank->context.wake_en = |
416 | __raw_readl(bank->base + bank->regs->wkup_en); | |
5e571f38 | 417 | __raw_writel(l, reg); |
5e1c5ff4 | 418 | } |
92105bb7 | 419 | return 0; |
5e1c5ff4 TL |
420 | } |
421 | ||
e9191028 | 422 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 423 | { |
25db711d | 424 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
4b25408f | 425 | unsigned gpio = 0; |
92105bb7 | 426 | int retval; |
a6472533 | 427 | unsigned long flags; |
92105bb7 | 428 | |
8d4c277e JH |
429 | if (WARN_ON(!bank->mod_usage)) |
430 | return -EINVAL; | |
431 | ||
4b25408f TL |
432 | #ifdef CONFIG_ARCH_OMAP1 |
433 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 434 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
435 | #endif |
436 | ||
437 | if (!gpio) | |
ede4d7a5 | 438 | gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 | 439 | |
e5c56ed3 | 440 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 441 | return -EINVAL; |
e5c56ed3 | 442 | |
9ea14d8c TKD |
443 | if (!bank->regs->leveldetect0 && |
444 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
445 | return -EINVAL; |
446 | ||
a6472533 | 447 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 448 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 449 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
450 | |
451 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 452 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 453 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 454 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 455 | |
92105bb7 | 456 | return retval; |
5e1c5ff4 TL |
457 | } |
458 | ||
459 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
460 | { | |
92105bb7 | 461 | void __iomem *reg = bank->base; |
5e1c5ff4 | 462 | |
eef4bec7 | 463 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 464 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
465 | |
466 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
467 | if (bank->regs->irqstatus2) { |
468 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 469 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 470 | } |
bedfd154 RQ |
471 | |
472 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
473 | __raw_readl(reg); | |
5e1c5ff4 TL |
474 | } |
475 | ||
476 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
477 | { | |
129fd223 | 478 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
479 | } |
480 | ||
ea6dedd7 ID |
481 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
482 | { | |
483 | void __iomem *reg = bank->base; | |
99c47707 | 484 | u32 l; |
c390aad0 | 485 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 486 | |
28f3b5a0 | 487 | reg += bank->regs->irqenable; |
99c47707 | 488 | l = __raw_readl(reg); |
28f3b5a0 | 489 | if (bank->regs->irqenable_inv) |
99c47707 ID |
490 | l = ~l; |
491 | l &= mask; | |
492 | return l; | |
ea6dedd7 ID |
493 | } |
494 | ||
28f3b5a0 | 495 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 496 | { |
92105bb7 | 497 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
498 | u32 l; |
499 | ||
28f3b5a0 KH |
500 | if (bank->regs->set_irqenable) { |
501 | reg += bank->regs->set_irqenable; | |
502 | l = gpio_mask; | |
2a900eb7 | 503 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
504 | } else { |
505 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 506 | l = __raw_readl(reg); |
28f3b5a0 KH |
507 | if (bank->regs->irqenable_inv) |
508 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
509 | else |
510 | l |= gpio_mask; | |
2a900eb7 | 511 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
512 | } |
513 | ||
514 | __raw_writel(l, reg); | |
515 | } | |
516 | ||
517 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
518 | { | |
519 | void __iomem *reg = bank->base; | |
520 | u32 l; | |
521 | ||
522 | if (bank->regs->clr_irqenable) { | |
523 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 524 | l = gpio_mask; |
2a900eb7 | 525 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
526 | } else { |
527 | reg += bank->regs->irqenable; | |
56739a69 | 528 | l = __raw_readl(reg); |
28f3b5a0 | 529 | if (bank->regs->irqenable_inv) |
56739a69 | 530 | l |= gpio_mask; |
92105bb7 | 531 | else |
28f3b5a0 | 532 | l &= ~gpio_mask; |
2a900eb7 | 533 | bank->context.irqenable1 = l; |
5e1c5ff4 | 534 | } |
28f3b5a0 | 535 | |
5e1c5ff4 TL |
536 | __raw_writel(l, reg); |
537 | } | |
538 | ||
539 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
540 | { | |
8276536c TKD |
541 | if (enable) |
542 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
543 | else | |
544 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
5e1c5ff4 TL |
545 | } |
546 | ||
92105bb7 TL |
547 | /* |
548 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
549 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
550 | * to the target, system will wake up always on GPIO events. While | |
551 | * system is running all registered GPIO interrupts need to have wake-up | |
552 | * enabled. When system is suspended, only selected GPIO interrupts need | |
553 | * to have wake-up enabled. | |
554 | */ | |
555 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
556 | { | |
f64ad1a0 KH |
557 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
558 | unsigned long flags; | |
a6472533 | 559 | |
f64ad1a0 | 560 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 561 | dev_err(bank->dev, |
f64ad1a0 | 562 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
563 | return -EINVAL; |
564 | } | |
f64ad1a0 KH |
565 | |
566 | spin_lock_irqsave(&bank->lock, flags); | |
567 | if (enable) | |
0aa27273 | 568 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 569 | else |
0aa27273 | 570 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 571 | |
0aa27273 | 572 | __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
573 | spin_unlock_irqrestore(&bank->lock, flags); |
574 | ||
575 | return 0; | |
92105bb7 TL |
576 | } |
577 | ||
4196dd6b TL |
578 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
579 | { | |
129fd223 | 580 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
581 | _set_gpio_irqenable(bank, gpio, 0); |
582 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 583 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
c9c55d92 | 584 | _clear_gpio_debounce(bank, gpio); |
4196dd6b TL |
585 | } |
586 | ||
92105bb7 | 587 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 588 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 589 | { |
25db711d | 590 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 591 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
92105bb7 | 592 | |
25db711d | 593 | return _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
594 | } |
595 | ||
3ff164e1 | 596 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 597 | { |
3ff164e1 | 598 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 599 | unsigned long flags; |
52e31344 | 600 | |
55b93c32 TKD |
601 | /* |
602 | * If this is the first gpio_request for the bank, | |
603 | * enable the bank module. | |
604 | */ | |
605 | if (!bank->mod_usage) | |
606 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 607 | |
55b93c32 | 608 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
609 | /* Set trigger to none. You need to enable the desired trigger with |
610 | * request_irq() or set_irq_type(). | |
611 | */ | |
3ff164e1 | 612 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 613 | |
fad96ea8 C |
614 | if (bank->regs->pinctrl) { |
615 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 616 | |
92105bb7 | 617 | /* Claim the pin for MPU */ |
3ff164e1 | 618 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 619 | } |
fad96ea8 | 620 | |
c8eef65a C |
621 | if (bank->regs->ctrl && !bank->mod_usage) { |
622 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
623 | u32 ctrl; | |
624 | ||
625 | ctrl = __raw_readl(reg); | |
626 | /* Module is enabled, clocks are not gated */ | |
627 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
628 | __raw_writel(ctrl, reg); | |
41d87cbd | 629 | bank->context.ctrl = ctrl; |
058af1ea | 630 | } |
c8eef65a C |
631 | |
632 | bank->mod_usage |= 1 << offset; | |
633 | ||
a6472533 | 634 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
635 | |
636 | return 0; | |
637 | } | |
638 | ||
3ff164e1 | 639 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 640 | { |
3ff164e1 | 641 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 642 | void __iomem *base = bank->base; |
a6472533 | 643 | unsigned long flags; |
5e1c5ff4 | 644 | |
a6472533 | 645 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b | 646 | |
41d87cbd | 647 | if (bank->regs->wkup_en) { |
9f096868 | 648 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b | 649 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
41d87cbd TKD |
650 | bank->context.wake_en = |
651 | __raw_readl(bank->base + bank->regs->wkup_en); | |
652 | } | |
6ed87c5b | 653 | |
c8eef65a C |
654 | bank->mod_usage &= ~(1 << offset); |
655 | ||
656 | if (bank->regs->ctrl && !bank->mod_usage) { | |
657 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
658 | u32 ctrl; | |
659 | ||
660 | ctrl = __raw_readl(reg); | |
661 | /* Module is disabled, clocks are gated */ | |
662 | ctrl |= GPIO_MOD_CTRL_BIT; | |
663 | __raw_writel(ctrl, reg); | |
41d87cbd | 664 | bank->context.ctrl = ctrl; |
058af1ea | 665 | } |
c8eef65a | 666 | |
3ff164e1 | 667 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 668 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
669 | |
670 | /* | |
671 | * If this is the last gpio to be freed in the bank, | |
672 | * disable the bank module. | |
673 | */ | |
674 | if (!bank->mod_usage) | |
675 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
676 | } |
677 | ||
678 | /* | |
679 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
680 | * avoid missing GPIO interrupts for other lines in the bank. | |
681 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
682 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
683 | * If we wait to unmask individual GPIO lines in the bank after the | |
684 | * line's interrupt handler has been run, we may miss some nested | |
685 | * interrupts. | |
686 | */ | |
10dd5ce2 | 687 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 688 | { |
92105bb7 | 689 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 690 | u32 isr; |
3513cdec | 691 | unsigned int bit; |
5e1c5ff4 | 692 | struct gpio_bank *bank; |
ea6dedd7 | 693 | int unmasked = 0; |
ee144182 | 694 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 695 | |
ee144182 | 696 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 697 | |
6845664a | 698 | bank = irq_get_handler_data(irq); |
eef4bec7 | 699 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 700 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
701 | |
702 | if (WARN_ON(!isr_reg)) | |
703 | goto exit; | |
704 | ||
e83507b7 | 705 | while (1) { |
6e60e79a | 706 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 707 | u32 enabled; |
6e60e79a | 708 | |
ea6dedd7 ID |
709 | enabled = _get_gpio_irqbank_mask(bank); |
710 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 711 | |
9ea14d8c | 712 | if (bank->level_mask) |
b144ff6f | 713 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
714 | |
715 | /* clear edge sensitive interrupts before handler(s) are | |
716 | called so that we don't miss any interrupt occurred while | |
717 | executing them */ | |
28f3b5a0 | 718 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 719 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 720 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
721 | |
722 | /* if there is only edge sensitive GPIO pin interrupts | |
723 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
724 | if (!level_mask && !unmasked) { |
725 | unmasked = 1; | |
ee144182 | 726 | chained_irq_exit(chip, desc); |
ea6dedd7 | 727 | } |
92105bb7 TL |
728 | |
729 | if (!isr) | |
730 | break; | |
731 | ||
3513cdec JH |
732 | while (isr) { |
733 | bit = __ffs(isr); | |
734 | isr &= ~(1 << bit); | |
25db711d | 735 | |
4318f36b CM |
736 | /* |
737 | * Some chips can't respond to both rising and falling | |
738 | * at the same time. If this irq was requested with | |
739 | * both flags, we need to flip the ICR data for the IRQ | |
740 | * to respond to the IRQ for the opposite direction. | |
741 | * This will be indicated in the bank toggle_mask. | |
742 | */ | |
3513cdec JH |
743 | if (bank->toggle_mask & (1 << bit)) |
744 | _toggle_gpio_edge_triggering(bank, bit); | |
4318f36b | 745 | |
3513cdec | 746 | generic_handle_irq(irq_find_mapping(bank->domain, bit)); |
92105bb7 | 747 | } |
1a8bfa1e | 748 | } |
ea6dedd7 ID |
749 | /* if bank has any level sensitive GPIO pin interrupt |
750 | configured, we must unmask the bank interrupt only after | |
751 | handler(s) are executed in order to avoid spurious bank | |
752 | interrupt */ | |
b1cc4c55 | 753 | exit: |
ea6dedd7 | 754 | if (!unmasked) |
ee144182 | 755 | chained_irq_exit(chip, desc); |
55b93c32 | 756 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
757 | } |
758 | ||
e9191028 | 759 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 760 | { |
e9191028 | 761 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 762 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 763 | unsigned long flags; |
4196dd6b | 764 | |
85ec7b97 | 765 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 766 | _reset_gpio(bank, gpio); |
85ec7b97 | 767 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
768 | } |
769 | ||
e9191028 | 770 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 771 | { |
e9191028 | 772 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 773 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 TL |
774 | |
775 | _clear_gpio_irqstatus(bank, gpio); | |
776 | } | |
777 | ||
e9191028 | 778 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 779 | { |
e9191028 | 780 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 781 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 782 | unsigned long flags; |
5e1c5ff4 | 783 | |
85ec7b97 | 784 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 785 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 786 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 787 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
788 | } |
789 | ||
e9191028 | 790 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 791 | { |
e9191028 | 792 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 793 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
129fd223 | 794 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 795 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 796 | unsigned long flags; |
55b6019a | 797 | |
85ec7b97 | 798 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 799 | if (trigger) |
129fd223 | 800 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
801 | |
802 | /* For level-triggered GPIOs, the clearing must be done after | |
803 | * the HW source is cleared, thus after the handler has run */ | |
804 | if (bank->level_mask & irq_mask) { | |
805 | _set_gpio_irqenable(bank, gpio, 0); | |
806 | _clear_gpio_irqstatus(bank, gpio); | |
807 | } | |
5e1c5ff4 | 808 | |
4de8c75b | 809 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 810 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
811 | } |
812 | ||
e5c56ed3 DB |
813 | static struct irq_chip gpio_irq_chip = { |
814 | .name = "GPIO", | |
e9191028 LB |
815 | .irq_shutdown = gpio_irq_shutdown, |
816 | .irq_ack = gpio_ack_irq, | |
817 | .irq_mask = gpio_mask_irq, | |
818 | .irq_unmask = gpio_unmask_irq, | |
819 | .irq_set_type = gpio_irq_type, | |
820 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
821 | }; |
822 | ||
823 | /*---------------------------------------------------------------------*/ | |
824 | ||
79ee031f | 825 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 826 | { |
79ee031f | 827 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 828 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
829 | void __iomem *mask_reg = bank->base + |
830 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 831 | unsigned long flags; |
11a78b79 | 832 | |
a6472533 | 833 | spin_lock_irqsave(&bank->lock, flags); |
0aa27273 | 834 | __raw_writel(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 835 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
836 | |
837 | return 0; | |
838 | } | |
839 | ||
79ee031f | 840 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 841 | { |
79ee031f | 842 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 843 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
844 | void __iomem *mask_reg = bank->base + |
845 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 846 | unsigned long flags; |
11a78b79 | 847 | |
a6472533 | 848 | spin_lock_irqsave(&bank->lock, flags); |
499fa287 | 849 | __raw_writel(bank->context.wake_en, mask_reg); |
a6472533 | 850 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
47145210 | 855 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
856 | .suspend_noirq = omap_mpuio_suspend_noirq, |
857 | .resume_noirq = omap_mpuio_resume_noirq, | |
858 | }; | |
859 | ||
3c437ffd | 860 | /* use platform_driver for this. */ |
11a78b79 | 861 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
862 | .driver = { |
863 | .name = "mpuio", | |
79ee031f | 864 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
865 | }, |
866 | }; | |
867 | ||
868 | static struct platform_device omap_mpuio_device = { | |
869 | .name = "mpuio", | |
870 | .id = -1, | |
871 | .dev = { | |
872 | .driver = &omap_mpuio_driver.driver, | |
873 | } | |
874 | /* could list the /proc/iomem resources */ | |
875 | }; | |
876 | ||
03e128ca | 877 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 878 | { |
77640aab | 879 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 880 | |
11a78b79 DB |
881 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
882 | (void) platform_device_register(&omap_mpuio_device); | |
883 | } | |
884 | ||
e5c56ed3 | 885 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 886 | |
52e31344 DB |
887 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
888 | { | |
889 | struct gpio_bank *bank; | |
890 | unsigned long flags; | |
891 | ||
892 | bank = container_of(chip, struct gpio_bank, chip); | |
893 | spin_lock_irqsave(&bank->lock, flags); | |
894 | _set_gpio_direction(bank, offset, 1); | |
895 | spin_unlock_irqrestore(&bank->lock, flags); | |
896 | return 0; | |
897 | } | |
898 | ||
b37c45b8 RQ |
899 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
900 | { | |
fa87931a | 901 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 902 | |
b37c45b8 RQ |
903 | return __raw_readl(reg) & mask; |
904 | } | |
905 | ||
52e31344 DB |
906 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
907 | { | |
b37c45b8 | 908 | struct gpio_bank *bank; |
b37c45b8 RQ |
909 | u32 mask; |
910 | ||
a8be8daf | 911 | bank = container_of(chip, struct gpio_bank, chip); |
7fcca715 | 912 | mask = (1 << offset); |
b37c45b8 RQ |
913 | |
914 | if (gpio_is_input(bank, mask)) | |
7fcca715 | 915 | return _get_gpio_datain(bank, offset); |
b37c45b8 | 916 | else |
7fcca715 | 917 | return _get_gpio_dataout(bank, offset); |
52e31344 DB |
918 | } |
919 | ||
920 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
921 | { | |
922 | struct gpio_bank *bank; | |
923 | unsigned long flags; | |
924 | ||
925 | bank = container_of(chip, struct gpio_bank, chip); | |
926 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 927 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
928 | _set_gpio_direction(bank, offset, 0); |
929 | spin_unlock_irqrestore(&bank->lock, flags); | |
930 | return 0; | |
931 | } | |
932 | ||
168ef3d9 FB |
933 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
934 | unsigned debounce) | |
935 | { | |
936 | struct gpio_bank *bank; | |
937 | unsigned long flags; | |
938 | ||
939 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 940 | |
168ef3d9 FB |
941 | spin_lock_irqsave(&bank->lock, flags); |
942 | _set_gpio_debounce(bank, offset, debounce); | |
943 | spin_unlock_irqrestore(&bank->lock, flags); | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
52e31344 DB |
948 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
949 | { | |
950 | struct gpio_bank *bank; | |
951 | unsigned long flags; | |
952 | ||
953 | bank = container_of(chip, struct gpio_bank, chip); | |
954 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 955 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
956 | spin_unlock_irqrestore(&bank->lock, flags); |
957 | } | |
958 | ||
959 | /*---------------------------------------------------------------------*/ | |
960 | ||
9a748053 | 961 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 962 | { |
e5ff4440 | 963 | static bool called; |
9f7065da TL |
964 | u32 rev; |
965 | ||
e5ff4440 | 966 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
967 | return; |
968 | ||
e5ff4440 KH |
969 | rev = __raw_readw(bank->base + bank->regs->revision); |
970 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 971 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
972 | |
973 | called = true; | |
9f7065da TL |
974 | } |
975 | ||
8ba55c5c DB |
976 | /* This lock class tells lockdep that GPIO irqs are in a different |
977 | * category than their parents, so it won't report false recursion. | |
978 | */ | |
979 | static struct lock_class_key gpio_lock_class; | |
980 | ||
03e128ca | 981 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 982 | { |
ab985f0f TKD |
983 | void __iomem *base = bank->base; |
984 | u32 l = 0xffffffff; | |
2fae7fbe | 985 | |
ab985f0f TKD |
986 | if (bank->width == 16) |
987 | l = 0xffff; | |
988 | ||
d0d665a8 | 989 | if (bank->is_mpuio) { |
ab985f0f TKD |
990 | __raw_writel(l, bank->base + bank->regs->irqenable); |
991 | return; | |
2fae7fbe | 992 | } |
ab985f0f TKD |
993 | |
994 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
6edd94db | 995 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); |
ab985f0f | 996 | if (bank->regs->debounce_en) |
6edd94db | 997 | __raw_writel(0, base + bank->regs->debounce_en); |
ab985f0f | 998 | |
2dc983c5 TKD |
999 | /* Save OE default value (0xffffffff) in the context */ |
1000 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
1001 | /* Initialize interface clk ungated, module enabled */ |
1002 | if (bank->regs->ctrl) | |
6edd94db | 1003 | __raw_writel(0, base + bank->regs->ctrl); |
34672013 TKD |
1004 | |
1005 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1006 | if (IS_ERR(bank->dbck)) | |
1007 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1008 | } |
1009 | ||
3836309d | 1010 | static void |
f8b46b58 KH |
1011 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1012 | unsigned int num) | |
1013 | { | |
1014 | struct irq_chip_generic *gc; | |
1015 | struct irq_chip_type *ct; | |
1016 | ||
1017 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1018 | handle_simple_irq); | |
83233749 TP |
1019 | if (!gc) { |
1020 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1021 | return; | |
1022 | } | |
1023 | ||
f8b46b58 KH |
1024 | ct = gc->chip_types; |
1025 | ||
1026 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1027 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1028 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
1029 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
1030 | |
1031 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
1032 | ct->chip.irq_set_wake = gpio_wake_enable, |
1033 | ||
1034 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1035 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1036 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1037 | } | |
1038 | ||
3836309d | 1039 | static void omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1040 | { |
77640aab | 1041 | int j; |
2fae7fbe VC |
1042 | static int gpio; |
1043 | ||
2fae7fbe VC |
1044 | /* |
1045 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1046 | * over to the generic ones | |
1047 | */ | |
1048 | bank->chip.request = omap_gpio_request; | |
1049 | bank->chip.free = omap_gpio_free; | |
1050 | bank->chip.direction_input = gpio_input; | |
1051 | bank->chip.get = gpio_get; | |
1052 | bank->chip.direction_output = gpio_output; | |
1053 | bank->chip.set_debounce = gpio_debounce; | |
1054 | bank->chip.set = gpio_set; | |
ede4d7a5 | 1055 | bank->chip.to_irq = omap_gpio_to_irq; |
d0d665a8 | 1056 | if (bank->is_mpuio) { |
2fae7fbe | 1057 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1058 | if (bank->regs->wkup_en) |
1059 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1060 | bank->chip.base = OMAP_MPUIO(0); |
1061 | } else { | |
1062 | bank->chip.label = "gpio"; | |
1063 | bank->chip.base = gpio; | |
d5f46247 | 1064 | gpio += bank->width; |
2fae7fbe | 1065 | } |
d5f46247 | 1066 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1067 | |
1068 | gpiochip_add(&bank->chip); | |
1069 | ||
ede4d7a5 JH |
1070 | for (j = 0; j < bank->width; j++) { |
1071 | int irq = irq_create_mapping(bank->domain, j); | |
1072 | irq_set_lockdep_class(irq, &gpio_lock_class); | |
1073 | irq_set_chip_data(irq, bank); | |
d0d665a8 | 1074 | if (bank->is_mpuio) { |
ede4d7a5 | 1075 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
f8b46b58 | 1076 | } else { |
ede4d7a5 JH |
1077 | irq_set_chip_and_handler(irq, &gpio_irq_chip, |
1078 | handle_simple_irq); | |
1079 | set_irq_flags(irq, IRQF_VALID); | |
f8b46b58 | 1080 | } |
2fae7fbe | 1081 | } |
6845664a TG |
1082 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1083 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1084 | } |
1085 | ||
384ebe1c BC |
1086 | static const struct of_device_id omap_gpio_match[]; |
1087 | ||
3836309d | 1088 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1089 | { |
862ff640 | 1090 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1091 | struct device_node *node = dev->of_node; |
1092 | const struct of_device_id *match; | |
f6817a2c | 1093 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1094 | struct resource *res; |
5e1c5ff4 TL |
1095 | struct gpio_bank *bank; |
1096 | ||
384ebe1c BC |
1097 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1098 | ||
1099 | pdata = match ? match->data : dev->platform_data; | |
1100 | if (!pdata) | |
96751fcb | 1101 | return -EINVAL; |
5492fb1a | 1102 | |
086d585f | 1103 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1104 | if (!bank) { |
862ff640 | 1105 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1106 | return -ENOMEM; |
03e128ca | 1107 | } |
92105bb7 | 1108 | |
77640aab VC |
1109 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1110 | if (unlikely(!res)) { | |
862ff640 | 1111 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1112 | return -ENODEV; |
44169075 | 1113 | } |
5e1c5ff4 | 1114 | |
77640aab | 1115 | bank->irq = res->start; |
862ff640 | 1116 | bank->dev = dev; |
77640aab | 1117 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1118 | bank->stride = pdata->bank_stride; |
d5f46247 | 1119 | bank->width = pdata->bank_width; |
d0d665a8 | 1120 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1121 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1122 | bank->regs = pdata->regs; |
384ebe1c BC |
1123 | #ifdef CONFIG_OF_GPIO |
1124 | bank->chip.of_node = of_node_get(node); | |
1125 | #endif | |
a2797bea JH |
1126 | if (node) { |
1127 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1128 | bank->loses_context = true; | |
1129 | } else { | |
1130 | bank->loses_context = pdata->loses_context; | |
384ebe1c BC |
1131 | } |
1132 | ||
384ebe1c | 1133 | |
ede4d7a5 JH |
1134 | bank->domain = irq_domain_add_linear(node, bank->width, |
1135 | &irq_domain_simple_ops, NULL); | |
1136 | if (!bank->domain) | |
384ebe1c | 1137 | return -ENODEV; |
fa87931a KH |
1138 | |
1139 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1140 | bank->set_dataout = _set_gpio_dataout_reg; | |
1141 | else | |
1142 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1143 | |
77640aab | 1144 | spin_lock_init(&bank->lock); |
9f7065da | 1145 | |
77640aab VC |
1146 | /* Static mapping, never released */ |
1147 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1148 | if (unlikely(!res)) { | |
862ff640 | 1149 | dev_err(dev, "Invalid mem resource\n"); |
879fe324 | 1150 | irq_domain_remove(bank->domain); |
96751fcb BC |
1151 | return -ENODEV; |
1152 | } | |
1153 | ||
1154 | if (!devm_request_mem_region(dev, res->start, resource_size(res), | |
1155 | pdev->name)) { | |
1156 | dev_err(dev, "Region already claimed\n"); | |
879fe324 | 1157 | irq_domain_remove(bank->domain); |
96751fcb | 1158 | return -EBUSY; |
77640aab | 1159 | } |
89db9482 | 1160 | |
96751fcb | 1161 | bank->base = devm_ioremap(dev, res->start, resource_size(res)); |
77640aab | 1162 | if (!bank->base) { |
862ff640 | 1163 | dev_err(dev, "Could not ioremap\n"); |
879fe324 | 1164 | irq_domain_remove(bank->domain); |
96751fcb | 1165 | return -ENOMEM; |
5e1c5ff4 TL |
1166 | } |
1167 | ||
065cd795 TKD |
1168 | platform_set_drvdata(pdev, bank); |
1169 | ||
77640aab | 1170 | pm_runtime_enable(bank->dev); |
55b93c32 | 1171 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1172 | pm_runtime_get_sync(bank->dev); |
1173 | ||
d0d665a8 | 1174 | if (bank->is_mpuio) |
ab985f0f TKD |
1175 | mpuio_init(bank); |
1176 | ||
03e128ca | 1177 | omap_gpio_mod_init(bank); |
77640aab | 1178 | omap_gpio_chip_init(bank); |
9a748053 | 1179 | omap_gpio_show_rev(bank); |
9f7065da | 1180 | |
7b86cef3 JH |
1181 | if (bank->loses_context) |
1182 | bank->get_context_loss_count = pdata->get_context_loss_count; | |
1183 | ||
55b93c32 TKD |
1184 | pm_runtime_put(bank->dev); |
1185 | ||
03e128ca | 1186 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1187 | |
879fe324 | 1188 | return 0; |
5e1c5ff4 TL |
1189 | } |
1190 | ||
55b93c32 TKD |
1191 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1192 | ||
2dc983c5 | 1193 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1194 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1195 | |
2dc983c5 | 1196 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1197 | { |
2dc983c5 TKD |
1198 | struct platform_device *pdev = to_platform_device(dev); |
1199 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1200 | u32 l1 = 0, l2 = 0; | |
1201 | unsigned long flags; | |
68942edb | 1202 | u32 wake_low, wake_hi; |
8865b9b6 | 1203 | |
2dc983c5 | 1204 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1205 | |
1206 | /* | |
1207 | * Only edges can generate a wakeup event to the PRCM. | |
1208 | * | |
1209 | * Therefore, ensure any wake-up capable GPIOs have | |
1210 | * edge-detection enabled before going idle to ensure a wakeup | |
1211 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1212 | * NDA TRM 25.5.3.1) | |
1213 | * | |
1214 | * The normal values will be restored upon ->runtime_resume() | |
1215 | * by writing back the values saved in bank->context. | |
1216 | */ | |
1217 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1218 | if (wake_low) | |
1219 | __raw_writel(wake_low | bank->context.fallingdetect, | |
1220 | bank->base + bank->regs->fallingdetect); | |
1221 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1222 | if (wake_hi) | |
1223 | __raw_writel(wake_hi | bank->context.risingdetect, | |
1224 | bank->base + bank->regs->risingdetect); | |
1225 | ||
b3c64bc3 KH |
1226 | if (!bank->enabled_non_wakeup_gpios) |
1227 | goto update_gpio_context_count; | |
1228 | ||
2dc983c5 TKD |
1229 | if (bank->power_mode != OFF_MODE) { |
1230 | bank->power_mode = 0; | |
41d87cbd | 1231 | goto update_gpio_context_count; |
2dc983c5 TKD |
1232 | } |
1233 | /* | |
1234 | * If going to OFF, remove triggering for all | |
1235 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1236 | * generated. See OMAP2420 Errata item 1.101. | |
1237 | */ | |
2dc983c5 TKD |
1238 | bank->saved_datain = __raw_readl(bank->base + |
1239 | bank->regs->datain); | |
c6f31c9e TKD |
1240 | l1 = bank->context.fallingdetect; |
1241 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1242 | |
2dc983c5 TKD |
1243 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1244 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1245 | |
2dc983c5 TKD |
1246 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1247 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1248 | |
2dc983c5 | 1249 | bank->workaround_enabled = true; |
3f1686a9 | 1250 | |
41d87cbd | 1251 | update_gpio_context_count: |
2dc983c5 TKD |
1252 | if (bank->get_context_loss_count) |
1253 | bank->context_loss_count = | |
60a3437d TKD |
1254 | bank->get_context_loss_count(bank->dev); |
1255 | ||
72f83af9 | 1256 | _gpio_dbck_disable(bank); |
2dc983c5 | 1257 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1258 | |
2dc983c5 | 1259 | return 0; |
3ac4fa99 JY |
1260 | } |
1261 | ||
2dc983c5 | 1262 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1263 | { |
2dc983c5 TKD |
1264 | struct platform_device *pdev = to_platform_device(dev); |
1265 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1266 | u32 l = 0, gen, gen0, gen1; |
1267 | unsigned long flags; | |
a2797bea | 1268 | int c; |
8865b9b6 | 1269 | |
2dc983c5 | 1270 | spin_lock_irqsave(&bank->lock, flags); |
72f83af9 | 1271 | _gpio_dbck_enable(bank); |
68942edb KH |
1272 | |
1273 | /* | |
1274 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1275 | * GPIOs were set to edge trigger also in order to be able to | |
1276 | * generate a PRCM wakeup. Here we restore the | |
1277 | * pre-runtime_suspend() values for edge triggering. | |
1278 | */ | |
1279 | __raw_writel(bank->context.fallingdetect, | |
1280 | bank->base + bank->regs->fallingdetect); | |
1281 | __raw_writel(bank->context.risingdetect, | |
1282 | bank->base + bank->regs->risingdetect); | |
1283 | ||
a2797bea JH |
1284 | if (bank->loses_context) { |
1285 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1286 | omap_gpio_restore_context(bank); |
1287 | } else { | |
a2797bea JH |
1288 | c = bank->get_context_loss_count(bank->dev); |
1289 | if (c != bank->context_loss_count) { | |
1290 | omap_gpio_restore_context(bank); | |
1291 | } else { | |
1292 | spin_unlock_irqrestore(&bank->lock, flags); | |
1293 | return 0; | |
1294 | } | |
60a3437d | 1295 | } |
2dc983c5 | 1296 | } |
43ffcd9a | 1297 | |
1b128703 TKD |
1298 | if (!bank->workaround_enabled) { |
1299 | spin_unlock_irqrestore(&bank->lock, flags); | |
1300 | return 0; | |
1301 | } | |
1302 | ||
2dc983c5 | 1303 | l = __raw_readl(bank->base + bank->regs->datain); |
3f1686a9 | 1304 | |
2dc983c5 TKD |
1305 | /* |
1306 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1307 | * state. If so, generate an IRQ by software. This is | |
1308 | * horribly racy, but it's the best we can do to work around | |
1309 | * this silicon bug. | |
1310 | */ | |
1311 | l ^= bank->saved_datain; | |
1312 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1313 | |
2dc983c5 TKD |
1314 | /* |
1315 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1316 | * configured with falling edge only; and vice versa. | |
1317 | */ | |
c6f31c9e | 1318 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1319 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1320 | |
c6f31c9e | 1321 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1322 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1323 | |
2dc983c5 | 1324 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1325 | gen = l & (~(bank->context.fallingdetect) & |
1326 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1327 | /* Consider all GPIO IRQs needed to be updated */ |
1328 | gen |= gen0 | gen1; | |
82dbb9d3 | 1329 | |
2dc983c5 TKD |
1330 | if (gen) { |
1331 | u32 old0, old1; | |
82dbb9d3 | 1332 | |
2dc983c5 TKD |
1333 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1334 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1335 | |
4e962e89 | 1336 | if (!bank->regs->irqstatus_raw0) { |
2dc983c5 | 1337 | __raw_writel(old0 | gen, bank->base + |
9ea14d8c | 1338 | bank->regs->leveldetect0); |
2dc983c5 | 1339 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1340 | bank->regs->leveldetect1); |
2dc983c5 | 1341 | } |
9ea14d8c | 1342 | |
4e962e89 | 1343 | if (bank->regs->irqstatus_raw0) { |
2dc983c5 | 1344 | __raw_writel(old0 | l, bank->base + |
9ea14d8c | 1345 | bank->regs->leveldetect0); |
2dc983c5 | 1346 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1347 | bank->regs->leveldetect1); |
3ac4fa99 | 1348 | } |
2dc983c5 TKD |
1349 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1350 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1351 | } | |
1352 | ||
1353 | bank->workaround_enabled = false; | |
1354 | spin_unlock_irqrestore(&bank->lock, flags); | |
1355 | ||
1356 | return 0; | |
1357 | } | |
1358 | #endif /* CONFIG_PM_RUNTIME */ | |
1359 | ||
1360 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1361 | { | |
1362 | struct gpio_bank *bank; | |
1363 | ||
1364 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1365 | if (!bank->mod_usage || !bank->loses_context) |
1366 | continue; | |
1367 | ||
1368 | bank->power_mode = pwr_mode; | |
1369 | ||
2dc983c5 TKD |
1370 | pm_runtime_put_sync_suspend(bank->dev); |
1371 | } | |
1372 | } | |
1373 | ||
1374 | void omap2_gpio_resume_after_idle(void) | |
1375 | { | |
1376 | struct gpio_bank *bank; | |
1377 | ||
1378 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1379 | if (!bank->mod_usage || !bank->loses_context) |
1380 | continue; | |
1381 | ||
2dc983c5 | 1382 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1383 | } |
3ac4fa99 JY |
1384 | } |
1385 | ||
2dc983c5 | 1386 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1387 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1388 | { |
60a3437d | 1389 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1390 | bank->base + bank->regs->wkup_en); |
1391 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
60a3437d | 1392 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1393 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1394 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1395 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1396 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1397 | bank->base + bank->regs->risingdetect); |
60a3437d | 1398 | __raw_writel(bank->context.fallingdetect, |
ae10f233 | 1399 | bank->base + bank->regs->fallingdetect); |
f86bcc30 NM |
1400 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1401 | __raw_writel(bank->context.dataout, | |
1402 | bank->base + bank->regs->set_dataout); | |
1403 | else | |
1404 | __raw_writel(bank->context.dataout, | |
1405 | bank->base + bank->regs->dataout); | |
6d13eaaf NM |
1406 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); |
1407 | ||
ae547354 NM |
1408 | if (bank->dbck_enable_mask) { |
1409 | __raw_writel(bank->context.debounce, bank->base + | |
1410 | bank->regs->debounce); | |
1411 | __raw_writel(bank->context.debounce_en, | |
1412 | bank->base + bank->regs->debounce_en); | |
1413 | } | |
ba805be5 NM |
1414 | |
1415 | __raw_writel(bank->context.irqenable1, | |
1416 | bank->base + bank->regs->irqenable); | |
1417 | __raw_writel(bank->context.irqenable2, | |
1418 | bank->base + bank->regs->irqenable2); | |
40c670f0 | 1419 | } |
2dc983c5 | 1420 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 | 1421 | #else |
2dc983c5 TKD |
1422 | #define omap_gpio_runtime_suspend NULL |
1423 | #define omap_gpio_runtime_resume NULL | |
40c670f0 RN |
1424 | #endif |
1425 | ||
55b93c32 | 1426 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1427 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1428 | NULL) | |
55b93c32 TKD |
1429 | }; |
1430 | ||
384ebe1c BC |
1431 | #if defined(CONFIG_OF) |
1432 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1433 | .revision = OMAP24XX_GPIO_REVISION, | |
1434 | .direction = OMAP24XX_GPIO_OE, | |
1435 | .datain = OMAP24XX_GPIO_DATAIN, | |
1436 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1437 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1438 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1439 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1440 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1441 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1442 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1443 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1444 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1445 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1446 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1447 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1448 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1449 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1450 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1451 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1452 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1453 | }; | |
1454 | ||
1455 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1456 | .revision = OMAP4_GPIO_REVISION, | |
1457 | .direction = OMAP4_GPIO_OE, | |
1458 | .datain = OMAP4_GPIO_DATAIN, | |
1459 | .dataout = OMAP4_GPIO_DATAOUT, | |
1460 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1461 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1462 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1463 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1464 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1465 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1466 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1467 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1468 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1469 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1470 | .ctrl = OMAP4_GPIO_CTRL, | |
1471 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1472 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1473 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1474 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1475 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1476 | }; | |
1477 | ||
e9a65bb6 | 1478 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1479 | .regs = &omap2_gpio_regs, |
1480 | .bank_width = 32, | |
1481 | .dbck_flag = false, | |
1482 | }; | |
1483 | ||
e9a65bb6 | 1484 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1485 | .regs = &omap2_gpio_regs, |
1486 | .bank_width = 32, | |
1487 | .dbck_flag = true, | |
1488 | }; | |
1489 | ||
e9a65bb6 | 1490 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1491 | .regs = &omap4_gpio_regs, |
1492 | .bank_width = 32, | |
1493 | .dbck_flag = true, | |
1494 | }; | |
1495 | ||
1496 | static const struct of_device_id omap_gpio_match[] = { | |
1497 | { | |
1498 | .compatible = "ti,omap4-gpio", | |
1499 | .data = &omap4_pdata, | |
1500 | }, | |
1501 | { | |
1502 | .compatible = "ti,omap3-gpio", | |
1503 | .data = &omap3_pdata, | |
1504 | }, | |
1505 | { | |
1506 | .compatible = "ti,omap2-gpio", | |
1507 | .data = &omap2_pdata, | |
1508 | }, | |
1509 | { }, | |
1510 | }; | |
1511 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1512 | #endif | |
1513 | ||
77640aab VC |
1514 | static struct platform_driver omap_gpio_driver = { |
1515 | .probe = omap_gpio_probe, | |
1516 | .driver = { | |
1517 | .name = "omap_gpio", | |
55b93c32 | 1518 | .pm = &gpio_pm_ops, |
384ebe1c | 1519 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1520 | }, |
1521 | }; | |
1522 | ||
5e1c5ff4 | 1523 | /* |
77640aab VC |
1524 | * gpio driver register needs to be done before |
1525 | * machine_init functions access gpio APIs. | |
1526 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1527 | */ |
77640aab | 1528 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1529 | { |
77640aab | 1530 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1531 | } |
77640aab | 1532 | postcore_initcall(omap_gpio_drv_reg); |