Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
b764a586 | 22 | #include <linux/cpu_pm.h> |
96751fcb | 23 | #include <linux/device.h> |
77640aab | 24 | #include <linux/pm_runtime.h> |
55b93c32 | 25 | #include <linux/pm.h> |
384ebe1c BC |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
b7351b07 | 28 | #include <linux/gpio/driver.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
6d62e216 C |
34 | struct gpio_regs { |
35 | u32 irqenable1; | |
36 | u32 irqenable2; | |
37 | u32 wake_en; | |
38 | u32 ctrl; | |
39 | u32 oe; | |
40 | u32 leveldetect0; | |
41 | u32 leveldetect1; | |
42 | u32 risingdetect; | |
43 | u32 fallingdetect; | |
44 | u32 dataout; | |
ae547354 NM |
45 | u32 debounce; |
46 | u32 debounce_en; | |
6d62e216 C |
47 | }; |
48 | ||
5e1c5ff4 | 49 | struct gpio_bank { |
92105bb7 | 50 | void __iomem *base; |
30cefeac | 51 | int irq; |
3ac4fa99 JY |
52 | u32 non_wakeup_gpios; |
53 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 54 | struct gpio_regs context; |
3ac4fa99 | 55 | u32 saved_datain; |
b144ff6f | 56 | u32 level_mask; |
4318f36b | 57 | u32 toggle_mask; |
4dbada2b | 58 | raw_spinlock_t lock; |
450fa54c | 59 | raw_spinlock_t wa_lock; |
52e31344 | 60 | struct gpio_chip chip; |
89db9482 | 61 | struct clk *dbck; |
b764a586 TL |
62 | struct notifier_block nb; |
63 | unsigned int is_suspended:1; | |
058af1ea | 64 | u32 mod_usage; |
fa365e4d | 65 | u32 irq_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
72f83af9 | 67 | bool dbck_enabled; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
fa87931a | 75 | |
04ebcbd8 | 76 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 77 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
78 | |
79 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
80 | }; |
81 | ||
c8eef65a | 82 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 83 | |
fa365e4d | 84 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 85 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 86 | |
3d009c8c TL |
87 | static void omap_gpio_unmask_irq(struct irq_data *d); |
88 | ||
a0e827c6 | 89 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 90 | { |
fb655f57 | 91 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 92 | return gpiochip_get_data(chip); |
25db711d BC |
93 | } |
94 | ||
8ee1de65 | 95 | static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) |
5e1c5ff4 | 96 | { |
8ee1de65 | 97 | u32 val = readl_relaxed(reg); |
5e1c5ff4 | 98 | |
8ee1de65 RK |
99 | if (set) |
100 | val |= mask; | |
5e1c5ff4 | 101 | else |
8ee1de65 RK |
102 | val &= ~mask; |
103 | ||
104 | writel_relaxed(val, reg); | |
105 | ||
106 | return val; | |
107 | } | |
108 | ||
109 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, | |
110 | int is_input) | |
111 | { | |
112 | bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, | |
113 | BIT(gpio), is_input); | |
5e1c5ff4 TL |
114 | } |
115 | ||
fa87931a KH |
116 | |
117 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 118 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 119 | int enable) |
5e1c5ff4 | 120 | { |
92105bb7 | 121 | void __iomem *reg = bank->base; |
04ebcbd8 | 122 | u32 l = BIT(offset); |
5e1c5ff4 | 123 | |
2c836f7e | 124 | if (enable) { |
fa87931a | 125 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
126 | bank->context.dataout |= l; |
127 | } else { | |
fa87931a | 128 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
129 | bank->context.dataout &= ~l; |
130 | } | |
5e1c5ff4 | 131 | |
661553b9 | 132 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
133 | } |
134 | ||
fa87931a | 135 | /* set data out value using mask register */ |
04ebcbd8 | 136 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 137 | int enable) |
5e1c5ff4 | 138 | { |
8ee1de65 RK |
139 | bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, |
140 | BIT(offset), enable); | |
ece9528e | 141 | } |
92105bb7 | 142 | |
a0e827c6 | 143 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
144 | { |
145 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 146 | clk_enable(bank->dbck); |
72f83af9 | 147 | bank->dbck_enabled = true; |
9e303f22 | 148 | |
661553b9 | 149 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 150 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
151 | } |
152 | } | |
153 | ||
a0e827c6 | 154 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
155 | { |
156 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
157 | /* |
158 | * Disable debounce before cutting it's clock. If debounce is | |
159 | * enabled but the clock is not, GPIO module seems to be unable | |
160 | * to detect events and generate interrupts at least on OMAP3. | |
161 | */ | |
661553b9 | 162 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 163 | |
5d9452e7 | 164 | clk_disable(bank->dbck); |
72f83af9 TKD |
165 | bank->dbck_enabled = false; |
166 | } | |
167 | } | |
168 | ||
168ef3d9 | 169 | /** |
a0e827c6 | 170 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 171 | * @bank: the gpio bank we're acting upon |
4a58d229 | 172 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
173 | * @debounce: debounce time to use |
174 | * | |
e85ec6c3 GS |
175 | * OMAP's debounce time is in 31us steps |
176 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
177 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
178 | * |
179 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 180 | */ |
83977443 DR |
181 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
182 | unsigned debounce) | |
168ef3d9 | 183 | { |
9942da0e | 184 | void __iomem *reg; |
168ef3d9 FB |
185 | u32 val; |
186 | u32 l; | |
e85ec6c3 | 187 | bool enable = !!debounce; |
168ef3d9 | 188 | |
77640aab | 189 | if (!bank->dbck_flag) |
83977443 | 190 | return -ENOTSUPP; |
77640aab | 191 | |
e85ec6c3 GS |
192 | if (enable) { |
193 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
194 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
195 | return -EINVAL; | |
e85ec6c3 | 196 | } |
168ef3d9 | 197 | |
4a58d229 | 198 | l = BIT(offset); |
168ef3d9 | 199 | |
5d9452e7 | 200 | clk_enable(bank->dbck); |
9942da0e | 201 | reg = bank->base + bank->regs->debounce; |
661553b9 | 202 | writel_relaxed(debounce, reg); |
168ef3d9 | 203 | |
8ee1de65 | 204 | val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); |
f7ec0b0b | 205 | bank->dbck_enable_mask = val; |
168ef3d9 | 206 | |
5d9452e7 | 207 | clk_disable(bank->dbck); |
6fd9c421 TKD |
208 | /* |
209 | * Enable debounce clock per module. | |
210 | * This call is mandatory because in omap_gpio_request() when | |
211 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
212 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
213 | * used within _gpio_dbck_enable() is still not initialized at | |
214 | * that point. Therefore we have to enable dbck here. | |
215 | */ | |
a0e827c6 | 216 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
217 | if (bank->dbck_enable_mask) { |
218 | bank->context.debounce = debounce; | |
219 | bank->context.debounce_en = val; | |
220 | } | |
83977443 DR |
221 | |
222 | return 0; | |
168ef3d9 FB |
223 | } |
224 | ||
c9c55d92 | 225 | /** |
a0e827c6 | 226 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 227 | * @bank: the gpio bank we're acting upon |
4a58d229 | 228 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
229 | * |
230 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
231 | * this is the only gpio in this bank using debounce, then clear the debounce | |
232 | * time too. The debounce clock will also be disabled when calling this function | |
233 | * if this is the only gpio in the bank using debounce. | |
234 | */ | |
4a58d229 | 235 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 236 | { |
4a58d229 | 237 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
238 | |
239 | if (!bank->dbck_flag) | |
240 | return; | |
241 | ||
242 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
243 | return; | |
244 | ||
245 | bank->dbck_enable_mask &= ~gpio_bit; | |
246 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 247 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
248 | bank->base + bank->regs->debounce_en); |
249 | ||
250 | if (!bank->dbck_enable_mask) { | |
251 | bank->context.debounce = 0; | |
661553b9 | 252 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 253 | bank->regs->debounce); |
5d9452e7 | 254 | clk_disable(bank->dbck); |
c9c55d92 JH |
255 | bank->dbck_enabled = false; |
256 | } | |
257 | } | |
258 | ||
da38ef3e TL |
259 | /* |
260 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
261 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
262 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
263 | * are capable waking up the system from off mode. | |
264 | */ | |
265 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
266 | { | |
267 | u32 no_wake = bank->non_wakeup_gpios; | |
268 | ||
269 | if (no_wake) | |
270 | return !!(~no_wake & gpio_mask); | |
271 | ||
272 | return false; | |
273 | } | |
274 | ||
a0e827c6 | 275 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 276 | unsigned trigger) |
5e1c5ff4 | 277 | { |
3ac4fa99 | 278 | void __iomem *base = bank->base; |
b1e9fec2 | 279 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 280 | |
8ee1de65 | 281 | omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, |
a0e827c6 | 282 | trigger & IRQ_TYPE_LEVEL_LOW); |
8ee1de65 | 283 | omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, |
a0e827c6 | 284 | trigger & IRQ_TYPE_LEVEL_HIGH); |
e6818d29 RK |
285 | |
286 | /* | |
287 | * We need the edge detection enabled for to allow the GPIO block | |
288 | * to be woken from idle state. Set the appropriate edge detection | |
289 | * in addition to the level detection. | |
290 | */ | |
8ee1de65 | 291 | omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, |
e6818d29 | 292 | trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); |
8ee1de65 | 293 | omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, |
e6818d29 | 294 | trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); |
5e571f38 | 295 | |
41d87cbd | 296 | bank->context.leveldetect0 = |
661553b9 | 297 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 298 | bank->context.leveldetect1 = |
661553b9 | 299 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 300 | bank->context.risingdetect = |
661553b9 | 301 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 302 | bank->context.fallingdetect = |
661553b9 | 303 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd | 304 | |
a0e881e2 RK |
305 | bank->level_mask = bank->context.leveldetect0 | |
306 | bank->context.leveldetect1; | |
307 | ||
41d87cbd | 308 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
8ee1de65 | 309 | omap_gpio_rmw(base + bank->regs->wkup_en, gpio_bit, trigger != 0); |
00ded24c TL |
310 | bank->context.wake_en = |
311 | readl_relaxed(bank->base + bank->regs->wkup_en); | |
41d87cbd | 312 | } |
5e571f38 | 313 | |
55b220ca | 314 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 315 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
316 | /* |
317 | * Log the edge gpio and manually trigger the IRQ | |
318 | * after resume if the input level changes | |
319 | * to avoid irq lost during PER RET/OFF mode | |
320 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
321 | */ | |
322 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
323 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
324 | else | |
325 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
326 | } | |
92105bb7 TL |
327 | } |
328 | ||
4318f36b CM |
329 | /* |
330 | * This only applies to chips that can't do both rising and falling edge | |
331 | * detection at once. For all other chips, this function is a noop. | |
332 | */ | |
a0e827c6 | 333 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b | 334 | { |
a47b9158 RK |
335 | if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { |
336 | void __iomem *reg = bank->base + bank->regs->irqctrl; | |
4318f36b | 337 | |
a47b9158 RK |
338 | writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); |
339 | } | |
4318f36b CM |
340 | } |
341 | ||
a0e827c6 JMC |
342 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
343 | unsigned trigger) | |
92105bb7 TL |
344 | { |
345 | void __iomem *reg = bank->base; | |
5e571f38 | 346 | void __iomem *base = bank->base; |
92105bb7 | 347 | u32 l = 0; |
5e1c5ff4 | 348 | |
5e571f38 | 349 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 350 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
351 | } else if (bank->regs->irqctrl) { |
352 | reg += bank->regs->irqctrl; | |
353 | ||
661553b9 | 354 | l = readl_relaxed(reg); |
29501577 | 355 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 356 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 357 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 358 | l |= BIT(gpio); |
6cab4860 | 359 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 360 | l &= ~(BIT(gpio)); |
92105bb7 | 361 | else |
5e571f38 TKD |
362 | return -EINVAL; |
363 | ||
661553b9 | 364 | writel_relaxed(l, reg); |
5e571f38 | 365 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 366 | if (gpio & 0x08) |
5e571f38 | 367 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 368 | else |
5e571f38 TKD |
369 | reg += bank->regs->edgectrl1; |
370 | ||
5e1c5ff4 | 371 | gpio &= 0x07; |
661553b9 | 372 | l = readl_relaxed(reg); |
5e1c5ff4 | 373 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 374 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 375 | l |= 2 << (gpio << 1); |
6cab4860 | 376 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 377 | l |= BIT(gpio << 1); |
5e571f38 TKD |
378 | |
379 | /* Enable wake-up during idle for dynamic tick */ | |
8ee1de65 | 380 | omap_gpio_rmw(base + bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 381 | bank->context.wake_en = |
661553b9 VK |
382 | readl_relaxed(bank->base + bank->regs->wkup_en); |
383 | writel_relaxed(l, reg); | |
5e1c5ff4 | 384 | } |
92105bb7 | 385 | return 0; |
5e1c5ff4 TL |
386 | } |
387 | ||
a0e827c6 | 388 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
389 | { |
390 | if (bank->regs->pinctrl) { | |
391 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
392 | ||
393 | /* Claim the pin for MPU */ | |
b1e9fec2 | 394 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
395 | } |
396 | ||
397 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
398 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
399 | u32 ctrl; | |
400 | ||
661553b9 | 401 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
402 | /* Module is enabled, clocks are not gated */ |
403 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 404 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
405 | bank->context.ctrl = ctrl; |
406 | } | |
407 | } | |
408 | ||
a0e827c6 | 409 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
410 | { |
411 | void __iomem *base = bank->base; | |
412 | ||
413 | if (bank->regs->wkup_en && | |
414 | !LINE_USED(bank->mod_usage, offset) && | |
415 | !LINE_USED(bank->irq_usage, offset)) { | |
416 | /* Disable wake-up during idle for dynamic tick */ | |
8ee1de65 | 417 | omap_gpio_rmw(base + bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 418 | bank->context.wake_en = |
661553b9 | 419 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
420 | } |
421 | ||
422 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
423 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
424 | u32 ctrl; | |
425 | ||
661553b9 | 426 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
427 | /* Module is disabled, clocks are gated */ |
428 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 429 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
430 | bank->context.ctrl = ctrl; |
431 | } | |
432 | } | |
433 | ||
b2b20045 | 434 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
435 | { |
436 | void __iomem *reg = bank->base + bank->regs->direction; | |
437 | ||
b2b20045 | 438 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
439 | } |
440 | ||
37e14ecf | 441 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
442 | { |
443 | if (!LINE_USED(bank->mod_usage, offset)) { | |
444 | omap_enable_gpio_module(bank, offset); | |
445 | omap_set_gpio_direction(bank, offset, 1); | |
446 | } | |
37e14ecf | 447 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
448 | } |
449 | ||
a0e827c6 | 450 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 451 | { |
a0e827c6 | 452 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 453 | int retval; |
a6472533 | 454 | unsigned long flags; |
ea5fbe8d | 455 | unsigned offset = d->hwirq; |
92105bb7 | 456 | |
e5c56ed3 | 457 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 458 | return -EINVAL; |
e5c56ed3 | 459 | |
9ea14d8c TKD |
460 | if (!bank->regs->leveldetect0 && |
461 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
462 | return -EINVAL; |
463 | ||
4dbada2b | 464 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 465 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 466 | if (retval) { |
627c89b4 | 467 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 468 | goto error; |
977bd8a9 | 469 | } |
37e14ecf | 470 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 471 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 472 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
473 | retval = -EINVAL; |
474 | goto error; | |
fac7fa16 | 475 | } |
4dbada2b | 476 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
477 | |
478 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 479 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 480 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
481 | /* |
482 | * Edge IRQs are already cleared/acked in irq_handler and | |
483 | * not need to be masked, as result handle_edge_irq() | |
484 | * logic is excessed here and may cause lose of interrupts. | |
485 | * So just use handle_simple_irq. | |
486 | */ | |
487 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 488 | |
1562e461 GS |
489 | return 0; |
490 | ||
491 | error: | |
92105bb7 | 492 | return retval; |
5e1c5ff4 TL |
493 | } |
494 | ||
a0e827c6 | 495 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 496 | { |
92105bb7 | 497 | void __iomem *reg = bank->base; |
5e1c5ff4 | 498 | |
eef4bec7 | 499 | reg += bank->regs->irqstatus; |
661553b9 | 500 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
501 | |
502 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
503 | if (bank->regs->irqstatus2) { |
504 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 505 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 506 | } |
bedfd154 RQ |
507 | |
508 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 509 | readl_relaxed(reg); |
5e1c5ff4 TL |
510 | } |
511 | ||
9943f261 GS |
512 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
513 | unsigned offset) | |
5e1c5ff4 | 514 | { |
9943f261 | 515 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
516 | } |
517 | ||
a0e827c6 | 518 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
519 | { |
520 | void __iomem *reg = bank->base; | |
99c47707 | 521 | u32 l; |
b1e9fec2 | 522 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 523 | |
28f3b5a0 | 524 | reg += bank->regs->irqenable; |
661553b9 | 525 | l = readl_relaxed(reg); |
28f3b5a0 | 526 | if (bank->regs->irqenable_inv) |
99c47707 ID |
527 | l = ~l; |
528 | l &= mask; | |
529 | return l; | |
ea6dedd7 ID |
530 | } |
531 | ||
31b2d7f7 RK |
532 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
533 | unsigned offset, int enable) | |
28f3b5a0 KH |
534 | { |
535 | void __iomem *reg = bank->base; | |
31b2d7f7 RK |
536 | u32 gpio_mask = BIT(offset); |
537 | ||
538 | if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { | |
539 | if (enable) { | |
540 | reg += bank->regs->set_irqenable; | |
541 | bank->context.irqenable1 |= gpio_mask; | |
542 | } else { | |
543 | reg += bank->regs->clr_irqenable; | |
544 | bank->context.irqenable1 &= ~gpio_mask; | |
545 | } | |
546 | writel_relaxed(gpio_mask, reg); | |
28f3b5a0 | 547 | } else { |
31b2d7f7 RK |
548 | bank->context.irqenable1 = |
549 | omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, | |
550 | enable ^ bank->regs->irqenable_inv); | |
5e1c5ff4 | 551 | } |
5e1c5ff4 TL |
552 | } |
553 | ||
92105bb7 | 554 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 555 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 556 | { |
a0e827c6 | 557 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 558 | |
0c0451e7 | 559 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
560 | } |
561 | ||
5e1c5ff4 TL |
562 | /* |
563 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
564 | * avoid missing GPIO interrupts for other lines in the bank. | |
565 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
566 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
567 | * If we wait to unmask individual GPIO lines in the bank after the | |
568 | * line's interrupt handler has been run, we may miss some nested | |
569 | * interrupts. | |
570 | */ | |
450fa54c | 571 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 572 | { |
92105bb7 | 573 | void __iomem *isr_reg = NULL; |
395373c7 | 574 | u32 enabled, isr, edge; |
3513cdec | 575 | unsigned int bit; |
450fa54c GS |
576 | struct gpio_bank *bank = gpiobank; |
577 | unsigned long wa_lock_flags; | |
235f1eb1 | 578 | unsigned long lock_flags; |
5e1c5ff4 | 579 | |
eef4bec7 | 580 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
581 | if (WARN_ON(!isr_reg)) |
582 | goto exit; | |
583 | ||
5284521a TL |
584 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
585 | "gpio irq%i while runtime suspended?\n", irq)) | |
586 | return IRQ_NONE; | |
450fa54c | 587 | |
e83507b7 | 588 | while (1) { |
235f1eb1 GS |
589 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
590 | ||
a0e827c6 | 591 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 592 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 593 | |
395373c7 RK |
594 | /* |
595 | * Clear edge sensitive interrupts before calling handler(s) | |
596 | * so subsequent edge transitions are not missed while the | |
597 | * handlers are running. | |
598 | */ | |
599 | edge = isr & ~bank->level_mask; | |
600 | if (edge) | |
601 | omap_clear_gpio_irqbank(bank, edge); | |
6e60e79a | 602 | |
235f1eb1 GS |
603 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
604 | ||
92105bb7 TL |
605 | if (!isr) |
606 | break; | |
607 | ||
3513cdec JH |
608 | while (isr) { |
609 | bit = __ffs(isr); | |
b1e9fec2 | 610 | isr &= ~(BIT(bit)); |
25db711d | 611 | |
235f1eb1 | 612 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
613 | /* |
614 | * Some chips can't respond to both rising and falling | |
615 | * at the same time. If this irq was requested with | |
616 | * both flags, we need to flip the ICR data for the IRQ | |
617 | * to respond to the IRQ for the opposite direction. | |
618 | * This will be indicated in the bank toggle_mask. | |
619 | */ | |
b1e9fec2 | 620 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 621 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 622 | |
235f1eb1 GS |
623 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
624 | ||
450fa54c GS |
625 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
626 | ||
f0fbe7bc | 627 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 628 | bit)); |
450fa54c GS |
629 | |
630 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
631 | wa_lock_flags); | |
92105bb7 | 632 | } |
1a8bfa1e | 633 | } |
b1cc4c55 | 634 | exit: |
450fa54c | 635 | return IRQ_HANDLED; |
5e1c5ff4 TL |
636 | } |
637 | ||
3d009c8c TL |
638 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
639 | { | |
640 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 641 | unsigned long flags; |
37e14ecf | 642 | unsigned offset = d->hwirq; |
3d009c8c | 643 | |
4dbada2b | 644 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
645 | |
646 | if (!LINE_USED(bank->mod_usage, offset)) | |
647 | omap_set_gpio_direction(bank, offset, 1); | |
648 | else if (!omap_gpio_is_input(bank, offset)) | |
649 | goto err; | |
650 | omap_enable_gpio_module(bank, offset); | |
651 | bank->irq_usage |= BIT(offset); | |
652 | ||
4dbada2b | 653 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
654 | omap_gpio_unmask_irq(d); |
655 | ||
656 | return 0; | |
121dcb76 | 657 | err: |
4dbada2b | 658 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 659 | return -EINVAL; |
3d009c8c TL |
660 | } |
661 | ||
a0e827c6 | 662 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 663 | { |
a0e827c6 | 664 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 665 | unsigned long flags; |
9943f261 | 666 | unsigned offset = d->hwirq; |
4196dd6b | 667 | |
4dbada2b | 668 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 669 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 | 670 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 RK |
671 | omap_clear_gpio_irqstatus(bank, offset); |
672 | omap_set_gpio_irqenable(bank, offset, 0); | |
6e96c1b5 GS |
673 | if (!LINE_USED(bank->mod_usage, offset)) |
674 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 675 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 676 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
677 | } |
678 | ||
679 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
680 | { | |
681 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
682 | ||
46748073 | 683 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
684 | } |
685 | ||
686 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
687 | { | |
688 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 689 | |
46748073 | 690 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
691 | } |
692 | ||
a0e827c6 | 693 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 694 | { |
a0e827c6 | 695 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 696 | unsigned offset = d->hwirq; |
85ec7b97 | 697 | unsigned long flags; |
5e1c5ff4 | 698 | |
4dbada2b | 699 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 | 700 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 | 701 | omap_set_gpio_irqenable(bank, offset, 0); |
4dbada2b | 702 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
703 | } |
704 | ||
a0e827c6 | 705 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 706 | { |
a0e827c6 | 707 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 708 | unsigned offset = d->hwirq; |
8c04a176 | 709 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 710 | unsigned long flags; |
55b6019a | 711 | |
4dbada2b | 712 | raw_spin_lock_irqsave(&bank->lock, flags); |
d01849f7 RK |
713 | omap_set_gpio_irqenable(bank, offset, 1); |
714 | ||
715 | /* | |
716 | * For level-triggered GPIOs, clearing must be done after the source | |
717 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
718 | * after enabing the interrupt to clear the wakeup status. | |
719 | */ | |
c859e0d4 RK |
720 | if (bank->regs->leveldetect0 && bank->regs->wkup_en && |
721 | trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
9943f261 | 722 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 723 | |
c859e0d4 RK |
724 | if (trigger) |
725 | omap_set_gpio_triggering(bank, offset, trigger); | |
726 | ||
4dbada2b | 727 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
728 | } |
729 | ||
e5c56ed3 DB |
730 | /*---------------------------------------------------------------------*/ |
731 | ||
79ee031f | 732 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 733 | { |
a3f4f728 | 734 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
735 | void __iomem *mask_reg = bank->base + |
736 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 737 | unsigned long flags; |
11a78b79 | 738 | |
4dbada2b | 739 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 740 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 741 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
742 | |
743 | return 0; | |
744 | } | |
745 | ||
79ee031f | 746 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 747 | { |
a3f4f728 | 748 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
749 | void __iomem *mask_reg = bank->base + |
750 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 751 | unsigned long flags; |
11a78b79 | 752 | |
4dbada2b | 753 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 754 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 755 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
756 | |
757 | return 0; | |
758 | } | |
759 | ||
47145210 | 760 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
761 | .suspend_noirq = omap_mpuio_suspend_noirq, |
762 | .resume_noirq = omap_mpuio_resume_noirq, | |
763 | }; | |
764 | ||
3c437ffd | 765 | /* use platform_driver for this. */ |
11a78b79 | 766 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
767 | .driver = { |
768 | .name = "mpuio", | |
79ee031f | 769 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
770 | }, |
771 | }; | |
772 | ||
773 | static struct platform_device omap_mpuio_device = { | |
774 | .name = "mpuio", | |
775 | .id = -1, | |
776 | .dev = { | |
777 | .driver = &omap_mpuio_driver.driver, | |
778 | } | |
779 | /* could list the /proc/iomem resources */ | |
780 | }; | |
781 | ||
a0e827c6 | 782 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 783 | { |
77640aab | 784 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 785 | |
11a78b79 DB |
786 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
787 | (void) platform_device_register(&omap_mpuio_device); | |
788 | } | |
789 | ||
e5c56ed3 | 790 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 791 | |
dfbc6c7a RK |
792 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
793 | { | |
794 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
795 | unsigned long flags; | |
796 | ||
797 | pm_runtime_get_sync(chip->parent); | |
798 | ||
799 | raw_spin_lock_irqsave(&bank->lock, flags); | |
800 | omap_enable_gpio_module(bank, offset); | |
801 | bank->mod_usage |= BIT(offset); | |
802 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |
808 | { | |
809 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
810 | unsigned long flags; | |
811 | ||
812 | raw_spin_lock_irqsave(&bank->lock, flags); | |
813 | bank->mod_usage &= ~(BIT(offset)); | |
814 | if (!LINE_USED(bank->irq_usage, offset)) { | |
815 | omap_set_gpio_direction(bank, offset, 1); | |
816 | omap_clear_gpio_debounce(bank, offset); | |
817 | } | |
818 | omap_disable_gpio_module(bank, offset); | |
819 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
820 | ||
821 | pm_runtime_put(chip->parent); | |
822 | } | |
823 | ||
a0e827c6 | 824 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e | 825 | { |
40bb2273 | 826 | struct gpio_bank *bank = gpiochip_get_data(chip); |
9370084e | 827 | |
40bb2273 RK |
828 | return !!(readl_relaxed(bank->base + bank->regs->direction) & |
829 | BIT(offset)); | |
9370084e YY |
830 | } |
831 | ||
a0e827c6 | 832 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
833 | { |
834 | struct gpio_bank *bank; | |
835 | unsigned long flags; | |
836 | ||
d99f7aec | 837 | bank = gpiochip_get_data(chip); |
4dbada2b | 838 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 839 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 840 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
841 | return 0; |
842 | } | |
843 | ||
a0e827c6 | 844 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 845 | { |
5ca5f92c RK |
846 | struct gpio_bank *bank = gpiochip_get_data(chip); |
847 | void __iomem *reg; | |
b37c45b8 | 848 | |
b2b20045 | 849 | if (omap_gpio_is_input(bank, offset)) |
5ca5f92c | 850 | reg = bank->base + bank->regs->datain; |
b37c45b8 | 851 | else |
5ca5f92c RK |
852 | reg = bank->base + bank->regs->dataout; |
853 | ||
854 | return (readl_relaxed(reg) & BIT(offset)) != 0; | |
52e31344 DB |
855 | } |
856 | ||
a0e827c6 | 857 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
858 | { |
859 | struct gpio_bank *bank; | |
860 | unsigned long flags; | |
861 | ||
d99f7aec | 862 | bank = gpiochip_get_data(chip); |
4dbada2b | 863 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 864 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 865 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 866 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 867 | return 0; |
52e31344 DB |
868 | } |
869 | ||
442af140 JK |
870 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
871 | unsigned long *bits) | |
872 | { | |
873 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
6653dd88 RK |
874 | void __iomem *base = bank->base; |
875 | u32 direction, m, val = 0; | |
876 | ||
877 | direction = readl_relaxed(base + bank->regs->direction); | |
442af140 | 878 | |
6653dd88 RK |
879 | m = direction & *mask; |
880 | if (m) | |
881 | val |= readl_relaxed(base + bank->regs->datain) & m; | |
442af140 | 882 | |
6653dd88 RK |
883 | m = ~direction & *mask; |
884 | if (m) | |
885 | val |= readl_relaxed(base + bank->regs->dataout) & m; | |
442af140 | 886 | |
6653dd88 | 887 | *bits = val; |
442af140 JK |
888 | |
889 | return 0; | |
890 | } | |
891 | ||
a0e827c6 JMC |
892 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
893 | unsigned debounce) | |
168ef3d9 FB |
894 | { |
895 | struct gpio_bank *bank; | |
896 | unsigned long flags; | |
83977443 | 897 | int ret; |
168ef3d9 | 898 | |
d99f7aec | 899 | bank = gpiochip_get_data(chip); |
77640aab | 900 | |
4dbada2b | 901 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 902 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 903 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 904 | |
83977443 DR |
905 | if (ret) |
906 | dev_info(chip->parent, | |
907 | "Could not set line %u debounce to %u microseconds (%d)", | |
908 | offset, debounce, ret); | |
909 | ||
910 | return ret; | |
168ef3d9 FB |
911 | } |
912 | ||
2956b5d9 MW |
913 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
914 | unsigned long config) | |
915 | { | |
916 | u32 debounce; | |
917 | ||
918 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
919 | return -ENOTSUPP; | |
920 | ||
921 | debounce = pinconf_to_config_argument(config); | |
922 | return omap_gpio_debounce(chip, offset, debounce); | |
923 | } | |
924 | ||
a0e827c6 | 925 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
926 | { |
927 | struct gpio_bank *bank; | |
928 | unsigned long flags; | |
929 | ||
d99f7aec | 930 | bank = gpiochip_get_data(chip); |
4dbada2b | 931 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 932 | bank->set_dataout(bank, offset, value); |
4dbada2b | 933 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
934 | } |
935 | ||
442af140 JK |
936 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
937 | unsigned long *bits) | |
938 | { | |
939 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
8ba70595 | 940 | void __iomem *reg = bank->base + bank->regs->dataout; |
442af140 | 941 | unsigned long flags; |
8ba70595 | 942 | u32 l; |
442af140 JK |
943 | |
944 | raw_spin_lock_irqsave(&bank->lock, flags); | |
8ba70595 RK |
945 | l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); |
946 | writel_relaxed(l, reg); | |
947 | bank->context.dataout = l; | |
442af140 JK |
948 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
949 | } | |
950 | ||
52e31344 DB |
951 | /*---------------------------------------------------------------------*/ |
952 | ||
e4b2ae7a | 953 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 954 | { |
e5ff4440 | 955 | static bool called; |
9f7065da TL |
956 | u32 rev; |
957 | ||
e5ff4440 | 958 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
959 | return; |
960 | ||
661553b9 | 961 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 962 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 963 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
964 | |
965 | called = true; | |
9f7065da TL |
966 | } |
967 | ||
03e128ca | 968 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 969 | { |
ab985f0f TKD |
970 | void __iomem *base = bank->base; |
971 | u32 l = 0xffffffff; | |
2fae7fbe | 972 | |
ab985f0f TKD |
973 | if (bank->width == 16) |
974 | l = 0xffff; | |
975 | ||
d0d665a8 | 976 | if (bank->is_mpuio) { |
661553b9 | 977 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 978 | return; |
2fae7fbe | 979 | } |
ab985f0f | 980 | |
8ee1de65 | 981 | omap_gpio_rmw(base + bank->regs->irqenable, l, |
a0e827c6 | 982 | bank->regs->irqenable_inv); |
8ee1de65 | 983 | omap_gpio_rmw(base + bank->regs->irqstatus, l, |
a0e827c6 | 984 | !bank->regs->irqenable_inv); |
ab985f0f | 985 | if (bank->regs->debounce_en) |
661553b9 | 986 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 987 | |
2dc983c5 | 988 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 989 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
990 | /* Initialize interface clk ungated, module enabled */ |
991 | if (bank->regs->ctrl) | |
661553b9 | 992 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
993 | } |
994 | ||
46824e22 | 995 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 996 | { |
81930328 | 997 | struct gpio_irq_chip *irq; |
2fae7fbe | 998 | static int gpio; |
088413bc | 999 | const char *label; |
fb655f57 | 1000 | int irq_base = 0; |
6ef7f385 | 1001 | int ret; |
2fae7fbe | 1002 | |
2fae7fbe VC |
1003 | /* |
1004 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1005 | * over to the generic ones | |
1006 | */ | |
1007 | bank->chip.request = omap_gpio_request; | |
1008 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1009 | bank->chip.get_direction = omap_gpio_get_direction; |
1010 | bank->chip.direction_input = omap_gpio_input; | |
1011 | bank->chip.get = omap_gpio_get; | |
442af140 | 1012 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1013 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1014 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1015 | bank->chip.set = omap_gpio_set; |
442af140 | 1016 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1017 | if (bank->is_mpuio) { |
2fae7fbe | 1018 | bank->chip.label = "mpuio"; |
6ed87c5b | 1019 | if (bank->regs->wkup_en) |
58383c78 | 1020 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1021 | bank->chip.base = OMAP_MPUIO(0); |
1022 | } else { | |
088413bc LW |
1023 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1024 | gpio, gpio + bank->width - 1); | |
1025 | if (!label) | |
1026 | return -ENOMEM; | |
1027 | bank->chip.label = label; | |
2fae7fbe | 1028 | bank->chip.base = gpio; |
2fae7fbe | 1029 | } |
d5f46247 | 1030 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1031 | |
fb655f57 JMC |
1032 | #ifdef CONFIG_ARCH_OMAP1 |
1033 | /* | |
1034 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1035 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1036 | */ | |
2ed36f30 BG |
1037 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1038 | -1, 0, bank->width, 0); | |
fb655f57 | 1039 | if (irq_base < 0) { |
7b1e5dc8 | 1040 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1041 | return -ENODEV; |
1042 | } | |
1043 | #endif | |
1044 | ||
d2d05c65 | 1045 | /* MPUIO is a bit different, reading IRQ status clears it */ |
693de831 RK |
1046 | if (bank->is_mpuio && !bank->regs->wkup_en) |
1047 | irqc->irq_set_wake = NULL; | |
d2d05c65 | 1048 | |
81930328 GS |
1049 | irq = &bank->chip.irq; |
1050 | irq->chip = irqc; | |
1051 | irq->handler = handle_bad_irq; | |
1052 | irq->default_type = IRQ_TYPE_NONE; | |
1053 | irq->num_parents = 1; | |
1054 | irq->parents = &bank->irq; | |
1055 | irq->first = irq_base; | |
fb655f57 | 1056 | |
81930328 | 1057 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1058 | if (ret) { |
7b1e5dc8 | 1059 | dev_err(bank->chip.parent, |
81930328 GS |
1060 | "Could not register gpio chip %d\n", ret); |
1061 | return ret; | |
fb655f57 JMC |
1062 | } |
1063 | ||
7b1e5dc8 GS |
1064 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1065 | omap_gpio_irq_handler, | |
1066 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1067 | if (ret) |
1068 | gpiochip_remove(&bank->chip); | |
1069 | ||
81930328 GS |
1070 | if (!bank->is_mpuio) |
1071 | gpio += bank->width; | |
1072 | ||
450fa54c | 1073 | return ret; |
2fae7fbe VC |
1074 | } |
1075 | ||
7c68571f | 1076 | static void omap_gpio_init_context(struct gpio_bank *p) |
b764a586 | 1077 | { |
7c68571f AB |
1078 | struct omap_gpio_reg_offs *regs = p->regs; |
1079 | void __iomem *base = p->base; | |
b764a586 | 1080 | |
7c68571f AB |
1081 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1082 | p->context.oe = readl_relaxed(base + regs->direction); | |
1083 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1084 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1085 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1086 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1087 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1088 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1089 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
9a302781 | 1090 | p->context.dataout = readl_relaxed(base + regs->dataout); |
b764a586 | 1091 | |
7c68571f | 1092 | p->context_valid = true; |
b764a586 TL |
1093 | } |
1094 | ||
7c68571f | 1095 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
5e1c5ff4 | 1096 | { |
9c7f798d RK |
1097 | struct omap_gpio_reg_offs *regs = bank->regs; |
1098 | void __iomem *base = bank->base; | |
1099 | ||
1100 | writel_relaxed(bank->context.wake_en, base + regs->wkup_en); | |
1101 | writel_relaxed(bank->context.ctrl, base + regs->ctrl); | |
1102 | writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); | |
1103 | writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); | |
1104 | writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); | |
1105 | writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); | |
1106 | writel_relaxed(bank->context.dataout, base + regs->dataout); | |
1107 | writel_relaxed(bank->context.oe, base + regs->direction); | |
9f7065da | 1108 | |
7c68571f | 1109 | if (bank->dbck_enable_mask) { |
9c7f798d | 1110 | writel_relaxed(bank->context.debounce, base + regs->debounce); |
7c68571f | 1111 | writel_relaxed(bank->context.debounce_en, |
9c7f798d | 1112 | base + regs->debounce_en); |
b764a586 TL |
1113 | } |
1114 | ||
9c7f798d RK |
1115 | writel_relaxed(bank->context.irqenable1, base + regs->irqenable); |
1116 | writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); | |
cac089f9 TL |
1117 | } |
1118 | ||
b764a586 | 1119 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1120 | { |
b764a586 | 1121 | struct device *dev = bank->chip.parent; |
21e2118f TL |
1122 | void __iomem *base = bank->base; |
1123 | u32 nowake; | |
1124 | ||
1125 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1126 | |
b3c64bc3 KH |
1127 | if (!bank->enabled_non_wakeup_gpios) |
1128 | goto update_gpio_context_count; | |
1129 | ||
b764a586 | 1130 | if (!may_lose_context) |
41d87cbd | 1131 | goto update_gpio_context_count; |
b764a586 | 1132 | |
2dc983c5 | 1133 | /* |
21e2118f | 1134 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1135 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1136 | * generated. See OMAP2420 Errata item 1.101. | |
1137 | */ | |
21e2118f TL |
1138 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1139 | nowake = bank->enabled_non_wakeup_gpios; | |
8ee1de65 RK |
1140 | omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); |
1141 | omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); | |
21e2118f | 1142 | } |
3f1686a9 | 1143 | |
41d87cbd | 1144 | update_gpio_context_count: |
2dc983c5 TKD |
1145 | if (bank->get_context_loss_count) |
1146 | bank->context_loss_count = | |
7b1e5dc8 | 1147 | bank->get_context_loss_count(dev); |
60a3437d | 1148 | |
a0e827c6 | 1149 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1150 | } |
1151 | ||
b764a586 | 1152 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1153 | { |
b764a586 | 1154 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1155 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1156 | int c; |
8865b9b6 | 1157 | |
352a2d5b JH |
1158 | /* |
1159 | * On the first resume during the probe, the context has not | |
1160 | * been initialised and so initialise it now. Also initialise | |
1161 | * the context loss count. | |
1162 | */ | |
1163 | if (bank->loses_context && !bank->context_valid) { | |
1164 | omap_gpio_init_context(bank); | |
1165 | ||
1166 | if (bank->get_context_loss_count) | |
1167 | bank->context_loss_count = | |
7b1e5dc8 | 1168 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1169 | } |
1170 | ||
a0e827c6 | 1171 | omap_gpio_dbck_enable(bank); |
68942edb | 1172 | |
a2797bea JH |
1173 | if (bank->loses_context) { |
1174 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1175 | omap_gpio_restore_context(bank); |
1176 | } else { | |
7b1e5dc8 | 1177 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1178 | if (c != bank->context_loss_count) { |
1179 | omap_gpio_restore_context(bank); | |
1180 | } else { | |
b764a586 | 1181 | return; |
a2797bea | 1182 | } |
60a3437d | 1183 | } |
21e2118f TL |
1184 | } else { |
1185 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1186 | writel_relaxed(bank->context.fallingdetect, | |
1187 | bank->base + bank->regs->fallingdetect); | |
1188 | writel_relaxed(bank->context.risingdetect, | |
1189 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1190 | } |
43ffcd9a | 1191 | |
661553b9 | 1192 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1193 | |
2dc983c5 TKD |
1194 | /* |
1195 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1196 | * state. If so, generate an IRQ by software. This is | |
1197 | * horribly racy, but it's the best we can do to work around | |
1198 | * this silicon bug. | |
1199 | */ | |
1200 | l ^= bank->saved_datain; | |
1201 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1202 | |
2dc983c5 TKD |
1203 | /* |
1204 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1205 | * configured with falling edge only; and vice versa. | |
1206 | */ | |
c6f31c9e | 1207 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1208 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1209 | |
c6f31c9e | 1210 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1211 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1212 | |
2dc983c5 | 1213 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1214 | gen = l & (~(bank->context.fallingdetect) & |
1215 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1216 | /* Consider all GPIO IRQs needed to be updated */ |
1217 | gen |= gen0 | gen1; | |
82dbb9d3 | 1218 | |
2dc983c5 TKD |
1219 | if (gen) { |
1220 | u32 old0, old1; | |
82dbb9d3 | 1221 | |
661553b9 VK |
1222 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1223 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1224 | |
4e962e89 | 1225 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1226 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1227 | bank->regs->leveldetect0); |
661553b9 | 1228 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1229 | bank->regs->leveldetect1); |
2dc983c5 | 1230 | } |
9ea14d8c | 1231 | |
4e962e89 | 1232 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1233 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1234 | bank->regs->leveldetect0); |
661553b9 | 1235 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1236 | bank->regs->leveldetect1); |
3ac4fa99 | 1237 | } |
661553b9 VK |
1238 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1239 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1240 | } |
2dc983c5 | 1241 | } |
2dc983c5 | 1242 | |
7c68571f AB |
1243 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, |
1244 | unsigned long cmd, void *v) | |
352a2d5b | 1245 | { |
7c68571f AB |
1246 | struct gpio_bank *bank; |
1247 | unsigned long flags; | |
352a2d5b | 1248 | |
7c68571f | 1249 | bank = container_of(nb, struct gpio_bank, nb); |
352a2d5b | 1250 | |
7c68571f AB |
1251 | raw_spin_lock_irqsave(&bank->lock, flags); |
1252 | switch (cmd) { | |
1253 | case CPU_CLUSTER_PM_ENTER: | |
1254 | if (bank->is_suspended) | |
1255 | break; | |
1256 | omap_gpio_idle(bank, true); | |
1257 | break; | |
1258 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1259 | case CPU_CLUSTER_PM_EXIT: | |
1260 | if (bank->is_suspended) | |
1261 | break; | |
1262 | omap_gpio_unidle(bank); | |
1263 | break; | |
1264 | } | |
1265 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
352a2d5b | 1266 | |
7c68571f | 1267 | return NOTIFY_OK; |
b764a586 TL |
1268 | } |
1269 | ||
384ebe1c BC |
1270 | static struct omap_gpio_reg_offs omap2_gpio_regs = { |
1271 | .revision = OMAP24XX_GPIO_REVISION, | |
1272 | .direction = OMAP24XX_GPIO_OE, | |
1273 | .datain = OMAP24XX_GPIO_DATAIN, | |
1274 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1275 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1276 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1277 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1278 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1279 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1280 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1281 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1282 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1283 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1284 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1285 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1286 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1287 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1288 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1289 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1290 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1291 | }; | |
1292 | ||
1293 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1294 | .revision = OMAP4_GPIO_REVISION, | |
1295 | .direction = OMAP4_GPIO_OE, | |
1296 | .datain = OMAP4_GPIO_DATAIN, | |
1297 | .dataout = OMAP4_GPIO_DATAOUT, | |
1298 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1299 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1300 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1301 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
64ea3e90 RK |
1302 | .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, |
1303 | .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, | |
384ebe1c BC |
1304 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, |
1305 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1306 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1307 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1308 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1309 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1310 | .ctrl = OMAP4_GPIO_CTRL, | |
1311 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1312 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1313 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1314 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1315 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1316 | }; | |
1317 | ||
e9a65bb6 | 1318 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1319 | .regs = &omap2_gpio_regs, |
1320 | .bank_width = 32, | |
1321 | .dbck_flag = false, | |
1322 | }; | |
1323 | ||
e9a65bb6 | 1324 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1325 | .regs = &omap2_gpio_regs, |
1326 | .bank_width = 32, | |
1327 | .dbck_flag = true, | |
1328 | }; | |
1329 | ||
e9a65bb6 | 1330 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1331 | .regs = &omap4_gpio_regs, |
1332 | .bank_width = 32, | |
1333 | .dbck_flag = true, | |
1334 | }; | |
1335 | ||
1336 | static const struct of_device_id omap_gpio_match[] = { | |
1337 | { | |
1338 | .compatible = "ti,omap4-gpio", | |
1339 | .data = &omap4_pdata, | |
1340 | }, | |
1341 | { | |
1342 | .compatible = "ti,omap3-gpio", | |
1343 | .data = &omap3_pdata, | |
1344 | }, | |
1345 | { | |
1346 | .compatible = "ti,omap2-gpio", | |
1347 | .data = &omap2_pdata, | |
1348 | }, | |
1349 | { }, | |
1350 | }; | |
1351 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
7c68571f AB |
1352 | |
1353 | static int omap_gpio_probe(struct platform_device *pdev) | |
1354 | { | |
1355 | struct device *dev = &pdev->dev; | |
1356 | struct device_node *node = dev->of_node; | |
1357 | const struct of_device_id *match; | |
1358 | const struct omap_gpio_platform_data *pdata; | |
7c68571f AB |
1359 | struct gpio_bank *bank; |
1360 | struct irq_chip *irqc; | |
1361 | int ret; | |
1362 | ||
1363 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); | |
1364 | ||
1365 | pdata = match ? match->data : dev_get_platdata(dev); | |
1366 | if (!pdata) | |
1367 | return -EINVAL; | |
1368 | ||
1369 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
1370 | if (!bank) | |
1371 | return -ENOMEM; | |
1372 | ||
1373 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); | |
1374 | if (!irqc) | |
1375 | return -ENOMEM; | |
1376 | ||
1377 | irqc->irq_startup = omap_gpio_irq_startup, | |
1378 | irqc->irq_shutdown = omap_gpio_irq_shutdown, | |
693de831 | 1379 | irqc->irq_ack = dummy_irq_chip.irq_ack, |
7c68571f AB |
1380 | irqc->irq_mask = omap_gpio_mask_irq, |
1381 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1382 | irqc->irq_set_type = omap_gpio_irq_type, | |
1383 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1384 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, | |
1385 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
1386 | irqc->name = dev_name(&pdev->dev); | |
1387 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1388 | irqc->parent_device = dev; | |
1389 | ||
1390 | bank->irq = platform_get_irq(pdev, 0); | |
1391 | if (bank->irq <= 0) { | |
1392 | if (!bank->irq) | |
1393 | bank->irq = -ENXIO; | |
1394 | if (bank->irq != -EPROBE_DEFER) | |
1395 | dev_err(dev, | |
1396 | "can't get irq resource ret=%d\n", bank->irq); | |
1397 | return bank->irq; | |
1398 | } | |
1399 | ||
1400 | bank->chip.parent = dev; | |
1401 | bank->chip.owner = THIS_MODULE; | |
1402 | bank->dbck_flag = pdata->dbck_flag; | |
7c68571f AB |
1403 | bank->stride = pdata->bank_stride; |
1404 | bank->width = pdata->bank_width; | |
1405 | bank->is_mpuio = pdata->is_mpuio; | |
1406 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; | |
1407 | bank->regs = pdata->regs; | |
1408 | #ifdef CONFIG_OF_GPIO | |
1409 | bank->chip.of_node = of_node_get(node); | |
384ebe1c BC |
1410 | #endif |
1411 | ||
7c68571f AB |
1412 | if (node) { |
1413 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1414 | bank->loses_context = true; | |
1415 | } else { | |
1416 | bank->loses_context = pdata->loses_context; | |
1417 | ||
1418 | if (bank->loses_context) | |
1419 | bank->get_context_loss_count = | |
1420 | pdata->get_context_loss_count; | |
1421 | } | |
1422 | ||
8ba70595 | 1423 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
7c68571f | 1424 | bank->set_dataout = omap_set_gpio_dataout_reg; |
8ba70595 | 1425 | else |
7c68571f | 1426 | bank->set_dataout = omap_set_gpio_dataout_mask; |
7c68571f | 1427 | |
7c68571f AB |
1428 | raw_spin_lock_init(&bank->lock); |
1429 | raw_spin_lock_init(&bank->wa_lock); | |
1430 | ||
1431 | /* Static mapping, never released */ | |
58f57f86 | 1432 | bank->base = devm_platform_ioremap_resource(pdev, 0); |
7c68571f AB |
1433 | if (IS_ERR(bank->base)) { |
1434 | return PTR_ERR(bank->base); | |
1435 | } | |
1436 | ||
1437 | if (bank->dbck_flag) { | |
1438 | bank->dbck = devm_clk_get(dev, "dbclk"); | |
1439 | if (IS_ERR(bank->dbck)) { | |
1440 | dev_err(dev, | |
1441 | "Could not get gpio dbck. Disable debounce\n"); | |
1442 | bank->dbck_flag = false; | |
1443 | } else { | |
1444 | clk_prepare(bank->dbck); | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | platform_set_drvdata(pdev, bank); | |
1449 | ||
1450 | pm_runtime_enable(dev); | |
1451 | pm_runtime_get_sync(dev); | |
1452 | ||
1453 | if (bank->is_mpuio) | |
1454 | omap_mpuio_init(bank); | |
1455 | ||
1456 | omap_gpio_mod_init(bank); | |
1457 | ||
1458 | ret = omap_gpio_chip_init(bank, irqc); | |
1459 | if (ret) { | |
1460 | pm_runtime_put_sync(dev); | |
1461 | pm_runtime_disable(dev); | |
1462 | if (bank->dbck_flag) | |
1463 | clk_unprepare(bank->dbck); | |
1464 | return ret; | |
1465 | } | |
1466 | ||
1467 | omap_gpio_show_rev(bank); | |
1468 | ||
e6818d29 RK |
1469 | bank->nb.notifier_call = gpio_omap_cpu_notifier; |
1470 | cpu_pm_register_notifier(&bank->nb); | |
7c68571f AB |
1471 | |
1472 | pm_runtime_put(dev); | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static int omap_gpio_remove(struct platform_device *pdev) | |
1478 | { | |
1479 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1480 | ||
e6818d29 | 1481 | cpu_pm_unregister_notifier(&bank->nb); |
7c68571f AB |
1482 | gpiochip_remove(&bank->chip); |
1483 | pm_runtime_disable(&pdev->dev); | |
1484 | if (bank->dbck_flag) | |
1485 | clk_unprepare(bank->dbck); | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) | |
1491 | { | |
1492 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1493 | unsigned long flags; | |
7c68571f AB |
1494 | |
1495 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1496 | omap_gpio_idle(bank, true); |
1497 | bank->is_suspended = true; | |
7c68571f AB |
1498 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1499 | ||
044e499a | 1500 | return 0; |
7c68571f AB |
1501 | } |
1502 | ||
1503 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1504 | { | |
1505 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1506 | unsigned long flags; | |
7c68571f AB |
1507 | |
1508 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1509 | omap_gpio_unidle(bank); |
1510 | bank->is_suspended = false; | |
7c68571f AB |
1511 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1512 | ||
044e499a | 1513 | return 0; |
7c68571f AB |
1514 | } |
1515 | ||
1516 | static const struct dev_pm_ops gpio_pm_ops = { | |
1517 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, | |
1518 | NULL) | |
1519 | }; | |
1520 | ||
77640aab VC |
1521 | static struct platform_driver omap_gpio_driver = { |
1522 | .probe = omap_gpio_probe, | |
cac089f9 | 1523 | .remove = omap_gpio_remove, |
77640aab VC |
1524 | .driver = { |
1525 | .name = "omap_gpio", | |
55b93c32 | 1526 | .pm = &gpio_pm_ops, |
7c68571f | 1527 | .of_match_table = omap_gpio_match, |
77640aab VC |
1528 | }, |
1529 | }; | |
1530 | ||
5e1c5ff4 | 1531 | /* |
77640aab VC |
1532 | * gpio driver register needs to be done before |
1533 | * machine_init functions access gpio APIs. | |
1534 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1535 | */ |
77640aab | 1536 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1537 | { |
77640aab | 1538 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1539 | } |
77640aab | 1540 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1541 | |
1542 | static void __exit omap_gpio_exit(void) | |
1543 | { | |
1544 | platform_driver_unregister(&omap_gpio_driver); | |
1545 | } | |
1546 | module_exit(omap_gpio_exit); | |
1547 | ||
1548 | MODULE_DESCRIPTION("omap gpio driver"); | |
1549 | MODULE_ALIAS("platform:gpio-omap"); | |
1550 | MODULE_LICENSE("GPL v2"); |