Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5e1c5ff4 | 2 | /* |
5e1c5ff4 TL |
3 | * Support functions for OMAP GPIO |
4 | * | |
92105bb7 | 5 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 6 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 7 | * |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
5e1c5ff4 TL |
10 | */ |
11 | ||
5e1c5ff4 TL |
12 | #include <linux/init.h> |
13 | #include <linux/module.h> | |
5e1c5ff4 | 14 | #include <linux/interrupt.h> |
3c437ffd | 15 | #include <linux/syscore_ops.h> |
92105bb7 | 16 | #include <linux/err.h> |
f8ce2547 | 17 | #include <linux/clk.h> |
fced80c7 | 18 | #include <linux/io.h> |
b764a586 | 19 | #include <linux/cpu_pm.h> |
96751fcb | 20 | #include <linux/device.h> |
77640aab | 21 | #include <linux/pm_runtime.h> |
55b93c32 | 22 | #include <linux/pm.h> |
384ebe1c BC |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
b7351b07 | 25 | #include <linux/gpio/driver.h> |
9370084e | 26 | #include <linux/bitops.h> |
4b25408f | 27 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 28 | |
e85ec6c3 | 29 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 30 | |
6d62e216 C |
31 | struct gpio_regs { |
32 | u32 irqenable1; | |
33 | u32 irqenable2; | |
34 | u32 wake_en; | |
35 | u32 ctrl; | |
36 | u32 oe; | |
37 | u32 leveldetect0; | |
38 | u32 leveldetect1; | |
39 | u32 risingdetect; | |
40 | u32 fallingdetect; | |
41 | u32 dataout; | |
ae547354 NM |
42 | u32 debounce; |
43 | u32 debounce_en; | |
6d62e216 C |
44 | }; |
45 | ||
5e1c5ff4 | 46 | struct gpio_bank { |
92105bb7 | 47 | void __iomem *base; |
18bd49c4 RK |
48 | const struct omap_gpio_reg_offs *regs; |
49 | ||
30cefeac | 50 | int irq; |
3ac4fa99 JY |
51 | u32 non_wakeup_gpios; |
52 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 53 | struct gpio_regs context; |
3ac4fa99 | 54 | u32 saved_datain; |
b144ff6f | 55 | u32 level_mask; |
4318f36b | 56 | u32 toggle_mask; |
4dbada2b | 57 | raw_spinlock_t lock; |
450fa54c | 58 | raw_spinlock_t wa_lock; |
52e31344 | 59 | struct gpio_chip chip; |
89db9482 | 60 | struct clk *dbck; |
b764a586 TL |
61 | struct notifier_block nb; |
62 | unsigned int is_suspended:1; | |
058af1ea | 63 | u32 mod_usage; |
fa365e4d | 64 | u32 irq_usage; |
8865b9b6 | 65 | u32 dbck_enable_mask; |
72f83af9 | 66 | bool dbck_enabled; |
d0d665a8 | 67 | bool is_mpuio; |
77640aab | 68 | bool dbck_flag; |
0cde8d03 | 69 | bool loses_context; |
352a2d5b | 70 | bool context_valid; |
5de62b86 | 71 | int stride; |
d5f46247 | 72 | u32 width; |
60a3437d | 73 | int context_loss_count; |
fa87931a | 74 | |
04ebcbd8 | 75 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 76 | int (*get_context_loss_count)(struct device *dev); |
5e1c5ff4 TL |
77 | }; |
78 | ||
c8eef65a | 79 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 80 | |
fa365e4d | 81 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 82 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 83 | |
3d009c8c TL |
84 | static void omap_gpio_unmask_irq(struct irq_data *d); |
85 | ||
a0e827c6 | 86 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 87 | { |
fb655f57 | 88 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 89 | return gpiochip_get_data(chip); |
25db711d BC |
90 | } |
91 | ||
8ee1de65 | 92 | static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) |
5e1c5ff4 | 93 | { |
8ee1de65 | 94 | u32 val = readl_relaxed(reg); |
5e1c5ff4 | 95 | |
8ee1de65 RK |
96 | if (set) |
97 | val |= mask; | |
5e1c5ff4 | 98 | else |
8ee1de65 RK |
99 | val &= ~mask; |
100 | ||
101 | writel_relaxed(val, reg); | |
102 | ||
103 | return val; | |
104 | } | |
105 | ||
106 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, | |
107 | int is_input) | |
108 | { | |
109 | bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, | |
110 | BIT(gpio), is_input); | |
5e1c5ff4 TL |
111 | } |
112 | ||
fa87931a KH |
113 | |
114 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 115 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 116 | int enable) |
5e1c5ff4 | 117 | { |
92105bb7 | 118 | void __iomem *reg = bank->base; |
04ebcbd8 | 119 | u32 l = BIT(offset); |
5e1c5ff4 | 120 | |
2c836f7e | 121 | if (enable) { |
fa87931a | 122 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
123 | bank->context.dataout |= l; |
124 | } else { | |
fa87931a | 125 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
126 | bank->context.dataout &= ~l; |
127 | } | |
5e1c5ff4 | 128 | |
661553b9 | 129 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
130 | } |
131 | ||
fa87931a | 132 | /* set data out value using mask register */ |
04ebcbd8 | 133 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 134 | int enable) |
5e1c5ff4 | 135 | { |
8ee1de65 RK |
136 | bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, |
137 | BIT(offset), enable); | |
ece9528e | 138 | } |
92105bb7 | 139 | |
a0e827c6 | 140 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
141 | { |
142 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 143 | clk_enable(bank->dbck); |
72f83af9 | 144 | bank->dbck_enabled = true; |
9e303f22 | 145 | |
661553b9 | 146 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 147 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
148 | } |
149 | } | |
150 | ||
a0e827c6 | 151 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
152 | { |
153 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
154 | /* |
155 | * Disable debounce before cutting it's clock. If debounce is | |
156 | * enabled but the clock is not, GPIO module seems to be unable | |
157 | * to detect events and generate interrupts at least on OMAP3. | |
158 | */ | |
661553b9 | 159 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 160 | |
5d9452e7 | 161 | clk_disable(bank->dbck); |
72f83af9 TKD |
162 | bank->dbck_enabled = false; |
163 | } | |
164 | } | |
165 | ||
168ef3d9 | 166 | /** |
a0e827c6 | 167 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 168 | * @bank: the gpio bank we're acting upon |
4a58d229 | 169 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
170 | * @debounce: debounce time to use |
171 | * | |
e85ec6c3 GS |
172 | * OMAP's debounce time is in 31us steps |
173 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
174 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
175 | * |
176 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 177 | */ |
83977443 DR |
178 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
179 | unsigned debounce) | |
168ef3d9 | 180 | { |
168ef3d9 FB |
181 | u32 val; |
182 | u32 l; | |
e85ec6c3 | 183 | bool enable = !!debounce; |
168ef3d9 | 184 | |
77640aab | 185 | if (!bank->dbck_flag) |
83977443 | 186 | return -ENOTSUPP; |
77640aab | 187 | |
e85ec6c3 GS |
188 | if (enable) { |
189 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
190 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
191 | return -EINVAL; | |
e85ec6c3 | 192 | } |
168ef3d9 | 193 | |
4a58d229 | 194 | l = BIT(offset); |
168ef3d9 | 195 | |
5d9452e7 | 196 | clk_enable(bank->dbck); |
754dfd79 | 197 | writel_relaxed(debounce, bank->base + bank->regs->debounce); |
168ef3d9 | 198 | |
8ee1de65 | 199 | val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); |
f7ec0b0b | 200 | bank->dbck_enable_mask = val; |
168ef3d9 | 201 | |
5d9452e7 | 202 | clk_disable(bank->dbck); |
6fd9c421 TKD |
203 | /* |
204 | * Enable debounce clock per module. | |
205 | * This call is mandatory because in omap_gpio_request() when | |
206 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
207 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
208 | * used within _gpio_dbck_enable() is still not initialized at | |
209 | * that point. Therefore we have to enable dbck here. | |
210 | */ | |
a0e827c6 | 211 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
212 | if (bank->dbck_enable_mask) { |
213 | bank->context.debounce = debounce; | |
214 | bank->context.debounce_en = val; | |
215 | } | |
83977443 DR |
216 | |
217 | return 0; | |
168ef3d9 FB |
218 | } |
219 | ||
c9c55d92 | 220 | /** |
a0e827c6 | 221 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 222 | * @bank: the gpio bank we're acting upon |
4a58d229 | 223 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
224 | * |
225 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
226 | * this is the only gpio in this bank using debounce, then clear the debounce | |
227 | * time too. The debounce clock will also be disabled when calling this function | |
228 | * if this is the only gpio in the bank using debounce. | |
229 | */ | |
4a58d229 | 230 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 231 | { |
4a58d229 | 232 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
233 | |
234 | if (!bank->dbck_flag) | |
235 | return; | |
236 | ||
237 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
238 | return; | |
239 | ||
240 | bank->dbck_enable_mask &= ~gpio_bit; | |
241 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 242 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
243 | bank->base + bank->regs->debounce_en); |
244 | ||
245 | if (!bank->dbck_enable_mask) { | |
246 | bank->context.debounce = 0; | |
661553b9 | 247 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 248 | bank->regs->debounce); |
5d9452e7 | 249 | clk_disable(bank->dbck); |
c9c55d92 JH |
250 | bank->dbck_enabled = false; |
251 | } | |
252 | } | |
253 | ||
da38ef3e TL |
254 | /* |
255 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
256 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
257 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
258 | * are capable waking up the system from off mode. | |
259 | */ | |
260 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
261 | { | |
262 | u32 no_wake = bank->non_wakeup_gpios; | |
263 | ||
264 | if (no_wake) | |
265 | return !!(~no_wake & gpio_mask); | |
266 | ||
267 | return false; | |
268 | } | |
269 | ||
a0e827c6 | 270 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 271 | unsigned trigger) |
5e1c5ff4 | 272 | { |
3ac4fa99 | 273 | void __iomem *base = bank->base; |
b1e9fec2 | 274 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 275 | |
8ee1de65 | 276 | omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, |
a0e827c6 | 277 | trigger & IRQ_TYPE_LEVEL_LOW); |
8ee1de65 | 278 | omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, |
a0e827c6 | 279 | trigger & IRQ_TYPE_LEVEL_HIGH); |
e6818d29 RK |
280 | |
281 | /* | |
282 | * We need the edge detection enabled for to allow the GPIO block | |
283 | * to be woken from idle state. Set the appropriate edge detection | |
284 | * in addition to the level detection. | |
285 | */ | |
8ee1de65 | 286 | omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, |
e6818d29 | 287 | trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); |
8ee1de65 | 288 | omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, |
e6818d29 | 289 | trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); |
5e571f38 | 290 | |
41d87cbd | 291 | bank->context.leveldetect0 = |
661553b9 | 292 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 293 | bank->context.leveldetect1 = |
661553b9 | 294 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 295 | bank->context.risingdetect = |
661553b9 | 296 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 297 | bank->context.fallingdetect = |
661553b9 | 298 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd | 299 | |
a0e881e2 RK |
300 | bank->level_mask = bank->context.leveldetect0 | |
301 | bank->context.leveldetect1; | |
5e571f38 | 302 | |
55b220ca | 303 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 304 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
305 | /* |
306 | * Log the edge gpio and manually trigger the IRQ | |
307 | * after resume if the input level changes | |
308 | * to avoid irq lost during PER RET/OFF mode | |
309 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
310 | */ | |
311 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
312 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
313 | else | |
314 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
315 | } | |
92105bb7 TL |
316 | } |
317 | ||
4318f36b CM |
318 | /* |
319 | * This only applies to chips that can't do both rising and falling edge | |
320 | * detection at once. For all other chips, this function is a noop. | |
321 | */ | |
a0e827c6 | 322 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b | 323 | { |
a47b9158 RK |
324 | if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { |
325 | void __iomem *reg = bank->base + bank->regs->irqctrl; | |
5e571f38 | 326 | |
a47b9158 RK |
327 | writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); |
328 | } | |
4318f36b CM |
329 | } |
330 | ||
a0e827c6 JMC |
331 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
332 | unsigned trigger) | |
92105bb7 TL |
333 | { |
334 | void __iomem *reg = bank->base; | |
335 | u32 l = 0; | |
5e1c5ff4 | 336 | |
5e571f38 | 337 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 338 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
339 | } else if (bank->regs->irqctrl) { |
340 | reg += bank->regs->irqctrl; | |
341 | ||
661553b9 | 342 | l = readl_relaxed(reg); |
29501577 | 343 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 344 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 345 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 346 | l |= BIT(gpio); |
6cab4860 | 347 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 348 | l &= ~(BIT(gpio)); |
92105bb7 | 349 | else |
5e571f38 TKD |
350 | return -EINVAL; |
351 | ||
661553b9 | 352 | writel_relaxed(l, reg); |
5e571f38 | 353 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 354 | if (gpio & 0x08) |
5e571f38 | 355 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 356 | else |
5e571f38 TKD |
357 | reg += bank->regs->edgectrl1; |
358 | ||
5e1c5ff4 | 359 | gpio &= 0x07; |
661553b9 | 360 | l = readl_relaxed(reg); |
5e1c5ff4 | 361 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 362 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 363 | l |= 2 << (gpio << 1); |
6cab4860 | 364 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 365 | l |= BIT(gpio << 1); |
661553b9 | 366 | writel_relaxed(l, reg); |
5e1c5ff4 | 367 | } |
92105bb7 | 368 | return 0; |
5e1c5ff4 TL |
369 | } |
370 | ||
a0e827c6 | 371 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
372 | { |
373 | if (bank->regs->pinctrl) { | |
374 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
375 | ||
376 | /* Claim the pin for MPU */ | |
b1e9fec2 | 377 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
378 | } |
379 | ||
380 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
381 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
382 | u32 ctrl; | |
383 | ||
661553b9 | 384 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
385 | /* Module is enabled, clocks are not gated */ |
386 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 387 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
388 | bank->context.ctrl = ctrl; |
389 | } | |
390 | } | |
391 | ||
a0e827c6 | 392 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 | 393 | { |
fac7fa16 JMC |
394 | if (bank->regs->ctrl && !BANK_USED(bank)) { |
395 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
396 | u32 ctrl; | |
397 | ||
661553b9 | 398 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
399 | /* Module is disabled, clocks are gated */ |
400 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 401 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
402 | bank->context.ctrl = ctrl; |
403 | } | |
404 | } | |
405 | ||
b2b20045 | 406 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
407 | { |
408 | void __iomem *reg = bank->base + bank->regs->direction; | |
409 | ||
b2b20045 | 410 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
411 | } |
412 | ||
37e14ecf | 413 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
414 | { |
415 | if (!LINE_USED(bank->mod_usage, offset)) { | |
416 | omap_enable_gpio_module(bank, offset); | |
417 | omap_set_gpio_direction(bank, offset, 1); | |
418 | } | |
37e14ecf | 419 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
420 | } |
421 | ||
a0e827c6 | 422 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 423 | { |
a0e827c6 | 424 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 425 | int retval; |
a6472533 | 426 | unsigned long flags; |
ea5fbe8d | 427 | unsigned offset = d->hwirq; |
92105bb7 | 428 | |
e5c56ed3 | 429 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 430 | return -EINVAL; |
e5c56ed3 | 431 | |
9ea14d8c TKD |
432 | if (!bank->regs->leveldetect0 && |
433 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
434 | return -EINVAL; |
435 | ||
4dbada2b | 436 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 437 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 438 | if (retval) { |
627c89b4 | 439 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 440 | goto error; |
977bd8a9 | 441 | } |
37e14ecf | 442 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 443 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 444 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
445 | retval = -EINVAL; |
446 | goto error; | |
fac7fa16 | 447 | } |
4dbada2b | 448 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
449 | |
450 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 451 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 452 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
453 | /* |
454 | * Edge IRQs are already cleared/acked in irq_handler and | |
455 | * not need to be masked, as result handle_edge_irq() | |
456 | * logic is excessed here and may cause lose of interrupts. | |
457 | * So just use handle_simple_irq. | |
458 | */ | |
459 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 460 | |
1562e461 GS |
461 | return 0; |
462 | ||
463 | error: | |
92105bb7 | 464 | return retval; |
5e1c5ff4 TL |
465 | } |
466 | ||
a0e827c6 | 467 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 468 | { |
92105bb7 | 469 | void __iomem *reg = bank->base; |
5e1c5ff4 | 470 | |
eef4bec7 | 471 | reg += bank->regs->irqstatus; |
661553b9 | 472 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
473 | |
474 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
475 | if (bank->regs->irqstatus2) { |
476 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 477 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 478 | } |
bedfd154 RQ |
479 | |
480 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 481 | readl_relaxed(reg); |
5e1c5ff4 TL |
482 | } |
483 | ||
9943f261 GS |
484 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
485 | unsigned offset) | |
5e1c5ff4 | 486 | { |
9943f261 | 487 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
488 | } |
489 | ||
a0e827c6 | 490 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
491 | { |
492 | void __iomem *reg = bank->base; | |
99c47707 | 493 | u32 l; |
b1e9fec2 | 494 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 495 | |
28f3b5a0 | 496 | reg += bank->regs->irqenable; |
661553b9 | 497 | l = readl_relaxed(reg); |
28f3b5a0 | 498 | if (bank->regs->irqenable_inv) |
99c47707 ID |
499 | l = ~l; |
500 | l &= mask; | |
501 | return l; | |
ea6dedd7 ID |
502 | } |
503 | ||
31b2d7f7 RK |
504 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
505 | unsigned offset, int enable) | |
5e1c5ff4 | 506 | { |
92105bb7 | 507 | void __iomem *reg = bank->base; |
31b2d7f7 | 508 | u32 gpio_mask = BIT(offset); |
5e1c5ff4 | 509 | |
31b2d7f7 RK |
510 | if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { |
511 | if (enable) { | |
512 | reg += bank->regs->set_irqenable; | |
513 | bank->context.irqenable1 |= gpio_mask; | |
514 | } else { | |
515 | reg += bank->regs->clr_irqenable; | |
516 | bank->context.irqenable1 &= ~gpio_mask; | |
517 | } | |
518 | writel_relaxed(gpio_mask, reg); | |
28f3b5a0 | 519 | } else { |
31b2d7f7 RK |
520 | bank->context.irqenable1 = |
521 | omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, | |
522 | enable ^ bank->regs->irqenable_inv); | |
28f3b5a0 KH |
523 | } |
524 | ||
40fd422a RK |
525 | /* |
526 | * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM | |
527 | * note requiring correlation between the IRQ enable registers and | |
528 | * the wakeup registers. In any case, we want wakeup from idle | |
529 | * enabled for the GPIOs which support this feature. | |
530 | */ | |
531 | if (bank->regs->wkup_en && | |
532 | (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { | |
533 | bank->context.wake_en = | |
534 | omap_gpio_rmw(bank->base + bank->regs->wkup_en, | |
535 | gpio_mask, enable); | |
5e1c5ff4 | 536 | } |
5e1c5ff4 TL |
537 | } |
538 | ||
92105bb7 | 539 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 540 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 541 | { |
a0e827c6 | 542 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 543 | |
0c0451e7 | 544 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
545 | } |
546 | ||
5e1c5ff4 TL |
547 | /* |
548 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
549 | * avoid missing GPIO interrupts for other lines in the bank. | |
550 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
551 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
552 | * If we wait to unmask individual GPIO lines in the bank after the | |
553 | * line's interrupt handler has been run, we may miss some nested | |
554 | * interrupts. | |
555 | */ | |
450fa54c | 556 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 557 | { |
92105bb7 | 558 | void __iomem *isr_reg = NULL; |
395373c7 | 559 | u32 enabled, isr, edge; |
3513cdec | 560 | unsigned int bit; |
450fa54c GS |
561 | struct gpio_bank *bank = gpiobank; |
562 | unsigned long wa_lock_flags; | |
235f1eb1 | 563 | unsigned long lock_flags; |
5e1c5ff4 | 564 | |
eef4bec7 | 565 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
566 | if (WARN_ON(!isr_reg)) |
567 | goto exit; | |
568 | ||
5284521a TL |
569 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
570 | "gpio irq%i while runtime suspended?\n", irq)) | |
571 | return IRQ_NONE; | |
450fa54c | 572 | |
e83507b7 | 573 | while (1) { |
235f1eb1 GS |
574 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
575 | ||
a0e827c6 | 576 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 577 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 578 | |
395373c7 RK |
579 | /* |
580 | * Clear edge sensitive interrupts before calling handler(s) | |
581 | * so subsequent edge transitions are not missed while the | |
582 | * handlers are running. | |
583 | */ | |
584 | edge = isr & ~bank->level_mask; | |
585 | if (edge) | |
586 | omap_clear_gpio_irqbank(bank, edge); | |
6e60e79a | 587 | |
235f1eb1 GS |
588 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
589 | ||
92105bb7 TL |
590 | if (!isr) |
591 | break; | |
592 | ||
3513cdec JH |
593 | while (isr) { |
594 | bit = __ffs(isr); | |
b1e9fec2 | 595 | isr &= ~(BIT(bit)); |
25db711d | 596 | |
235f1eb1 | 597 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
598 | /* |
599 | * Some chips can't respond to both rising and falling | |
600 | * at the same time. If this irq was requested with | |
601 | * both flags, we need to flip the ICR data for the IRQ | |
602 | * to respond to the IRQ for the opposite direction. | |
603 | * This will be indicated in the bank toggle_mask. | |
604 | */ | |
b1e9fec2 | 605 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 606 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 607 | |
235f1eb1 GS |
608 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
609 | ||
450fa54c GS |
610 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
611 | ||
f0fbe7bc | 612 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 613 | bit)); |
450fa54c GS |
614 | |
615 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
616 | wa_lock_flags); | |
92105bb7 | 617 | } |
1a8bfa1e | 618 | } |
b1cc4c55 | 619 | exit: |
450fa54c | 620 | return IRQ_HANDLED; |
5e1c5ff4 TL |
621 | } |
622 | ||
3d009c8c TL |
623 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
624 | { | |
625 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 626 | unsigned long flags; |
37e14ecf | 627 | unsigned offset = d->hwirq; |
3d009c8c | 628 | |
4dbada2b | 629 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
630 | |
631 | if (!LINE_USED(bank->mod_usage, offset)) | |
632 | omap_set_gpio_direction(bank, offset, 1); | |
121dcb76 GS |
633 | omap_enable_gpio_module(bank, offset); |
634 | bank->irq_usage |= BIT(offset); | |
635 | ||
4dbada2b | 636 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
637 | omap_gpio_unmask_irq(d); |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
a0e827c6 | 642 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 643 | { |
a0e827c6 | 644 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 645 | unsigned long flags; |
9943f261 | 646 | unsigned offset = d->hwirq; |
4196dd6b | 647 | |
4dbada2b | 648 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 649 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 | 650 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 RK |
651 | omap_clear_gpio_irqstatus(bank, offset); |
652 | omap_set_gpio_irqenable(bank, offset, 0); | |
6e96c1b5 GS |
653 | if (!LINE_USED(bank->mod_usage, offset)) |
654 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 655 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 656 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
657 | } |
658 | ||
659 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
660 | { | |
661 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
662 | ||
46748073 | 663 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
664 | } |
665 | ||
666 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
667 | { | |
668 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 669 | |
46748073 | 670 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
671 | } |
672 | ||
a0e827c6 | 673 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 674 | { |
a0e827c6 | 675 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 676 | unsigned offset = d->hwirq; |
85ec7b97 | 677 | unsigned long flags; |
5e1c5ff4 | 678 | |
4dbada2b | 679 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 | 680 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 | 681 | omap_set_gpio_irqenable(bank, offset, 0); |
4dbada2b | 682 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
683 | } |
684 | ||
a0e827c6 | 685 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 686 | { |
a0e827c6 | 687 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 688 | unsigned offset = d->hwirq; |
8c04a176 | 689 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 690 | unsigned long flags; |
55b6019a | 691 | |
4dbada2b | 692 | raw_spin_lock_irqsave(&bank->lock, flags); |
d01849f7 RK |
693 | omap_set_gpio_irqenable(bank, offset, 1); |
694 | ||
695 | /* | |
696 | * For level-triggered GPIOs, clearing must be done after the source | |
697 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
698 | * after enabing the interrupt to clear the wakeup status. | |
699 | */ | |
c859e0d4 RK |
700 | if (bank->regs->leveldetect0 && bank->regs->wkup_en && |
701 | trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
9943f261 | 702 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 703 | |
c859e0d4 RK |
704 | if (trigger) |
705 | omap_set_gpio_triggering(bank, offset, trigger); | |
706 | ||
4dbada2b | 707 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
708 | } |
709 | ||
e5c56ed3 DB |
710 | /*---------------------------------------------------------------------*/ |
711 | ||
79ee031f | 712 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 713 | { |
a3f4f728 | 714 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
715 | void __iomem *mask_reg = bank->base + |
716 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 717 | unsigned long flags; |
11a78b79 | 718 | |
4dbada2b | 719 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 720 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 721 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
722 | |
723 | return 0; | |
724 | } | |
725 | ||
79ee031f | 726 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 727 | { |
a3f4f728 | 728 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
729 | void __iomem *mask_reg = bank->base + |
730 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 731 | unsigned long flags; |
11a78b79 | 732 | |
4dbada2b | 733 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 734 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 735 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
736 | |
737 | return 0; | |
738 | } | |
739 | ||
47145210 | 740 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
741 | .suspend_noirq = omap_mpuio_suspend_noirq, |
742 | .resume_noirq = omap_mpuio_resume_noirq, | |
743 | }; | |
744 | ||
3c437ffd | 745 | /* use platform_driver for this. */ |
11a78b79 | 746 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
747 | .driver = { |
748 | .name = "mpuio", | |
79ee031f | 749 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
750 | }, |
751 | }; | |
752 | ||
753 | static struct platform_device omap_mpuio_device = { | |
754 | .name = "mpuio", | |
755 | .id = -1, | |
756 | .dev = { | |
757 | .driver = &omap_mpuio_driver.driver, | |
758 | } | |
759 | /* could list the /proc/iomem resources */ | |
760 | }; | |
761 | ||
a0e827c6 | 762 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 763 | { |
77640aab | 764 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 765 | |
11a78b79 DB |
766 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
767 | (void) platform_device_register(&omap_mpuio_device); | |
768 | } | |
769 | ||
e5c56ed3 | 770 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 771 | |
dfbc6c7a | 772 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
9370084e | 773 | { |
dfbc6c7a RK |
774 | struct gpio_bank *bank = gpiochip_get_data(chip); |
775 | unsigned long flags; | |
776 | ||
777 | pm_runtime_get_sync(chip->parent); | |
778 | ||
779 | raw_spin_lock_irqsave(&bank->lock, flags); | |
780 | omap_enable_gpio_module(bank, offset); | |
781 | bank->mod_usage |= BIT(offset); | |
782 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
787 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |
788 | { | |
789 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
9370084e | 790 | unsigned long flags; |
9370084e | 791 | |
4dbada2b | 792 | raw_spin_lock_irqsave(&bank->lock, flags); |
dfbc6c7a RK |
793 | bank->mod_usage &= ~(BIT(offset)); |
794 | if (!LINE_USED(bank->irq_usage, offset)) { | |
795 | omap_set_gpio_direction(bank, offset, 1); | |
796 | omap_clear_gpio_debounce(bank, offset); | |
797 | } | |
798 | omap_disable_gpio_module(bank, offset); | |
4dbada2b | 799 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
dfbc6c7a RK |
800 | |
801 | pm_runtime_put(chip->parent); | |
802 | } | |
803 | ||
a0e827c6 | 804 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e | 805 | { |
40bb2273 | 806 | struct gpio_bank *bank = gpiochip_get_data(chip); |
9370084e | 807 | |
40bb2273 RK |
808 | return !!(readl_relaxed(bank->base + bank->regs->direction) & |
809 | BIT(offset)); | |
9370084e YY |
810 | } |
811 | ||
a0e827c6 | 812 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
813 | { |
814 | struct gpio_bank *bank; | |
815 | unsigned long flags; | |
816 | ||
d99f7aec | 817 | bank = gpiochip_get_data(chip); |
4dbada2b | 818 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 819 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 820 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
821 | return 0; |
822 | } | |
823 | ||
a0e827c6 | 824 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 825 | { |
5ca5f92c RK |
826 | struct gpio_bank *bank = gpiochip_get_data(chip); |
827 | void __iomem *reg; | |
b37c45b8 | 828 | |
b2b20045 | 829 | if (omap_gpio_is_input(bank, offset)) |
5ca5f92c | 830 | reg = bank->base + bank->regs->datain; |
b37c45b8 | 831 | else |
5ca5f92c RK |
832 | reg = bank->base + bank->regs->dataout; |
833 | ||
834 | return (readl_relaxed(reg) & BIT(offset)) != 0; | |
52e31344 DB |
835 | } |
836 | ||
a0e827c6 | 837 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
838 | { |
839 | struct gpio_bank *bank; | |
840 | unsigned long flags; | |
841 | ||
d99f7aec | 842 | bank = gpiochip_get_data(chip); |
4dbada2b | 843 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 844 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 845 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 846 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 847 | return 0; |
52e31344 DB |
848 | } |
849 | ||
442af140 JK |
850 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
851 | unsigned long *bits) | |
852 | { | |
853 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
6653dd88 RK |
854 | void __iomem *base = bank->base; |
855 | u32 direction, m, val = 0; | |
442af140 | 856 | |
6653dd88 | 857 | direction = readl_relaxed(base + bank->regs->direction); |
442af140 | 858 | |
6653dd88 RK |
859 | m = direction & *mask; |
860 | if (m) | |
861 | val |= readl_relaxed(base + bank->regs->datain) & m; | |
442af140 | 862 | |
6653dd88 RK |
863 | m = ~direction & *mask; |
864 | if (m) | |
865 | val |= readl_relaxed(base + bank->regs->dataout) & m; | |
442af140 | 866 | |
6653dd88 | 867 | *bits = val; |
442af140 JK |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
a0e827c6 JMC |
872 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
873 | unsigned debounce) | |
168ef3d9 FB |
874 | { |
875 | struct gpio_bank *bank; | |
876 | unsigned long flags; | |
83977443 | 877 | int ret; |
168ef3d9 | 878 | |
d99f7aec | 879 | bank = gpiochip_get_data(chip); |
77640aab | 880 | |
4dbada2b | 881 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 882 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 883 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 884 | |
83977443 DR |
885 | if (ret) |
886 | dev_info(chip->parent, | |
887 | "Could not set line %u debounce to %u microseconds (%d)", | |
888 | offset, debounce, ret); | |
889 | ||
890 | return ret; | |
168ef3d9 FB |
891 | } |
892 | ||
2956b5d9 MW |
893 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
894 | unsigned long config) | |
895 | { | |
896 | u32 debounce; | |
897 | ||
898 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
899 | return -ENOTSUPP; | |
900 | ||
901 | debounce = pinconf_to_config_argument(config); | |
902 | return omap_gpio_debounce(chip, offset, debounce); | |
903 | } | |
904 | ||
a0e827c6 | 905 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
906 | { |
907 | struct gpio_bank *bank; | |
908 | unsigned long flags; | |
909 | ||
d99f7aec | 910 | bank = gpiochip_get_data(chip); |
4dbada2b | 911 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 912 | bank->set_dataout(bank, offset, value); |
4dbada2b | 913 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
914 | } |
915 | ||
442af140 JK |
916 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
917 | unsigned long *bits) | |
918 | { | |
919 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
8ba70595 | 920 | void __iomem *reg = bank->base + bank->regs->dataout; |
442af140 | 921 | unsigned long flags; |
8ba70595 | 922 | u32 l; |
442af140 JK |
923 | |
924 | raw_spin_lock_irqsave(&bank->lock, flags); | |
8ba70595 RK |
925 | l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); |
926 | writel_relaxed(l, reg); | |
927 | bank->context.dataout = l; | |
442af140 JK |
928 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
929 | } | |
930 | ||
52e31344 DB |
931 | /*---------------------------------------------------------------------*/ |
932 | ||
e4b2ae7a | 933 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 934 | { |
e5ff4440 | 935 | static bool called; |
9f7065da TL |
936 | u32 rev; |
937 | ||
e5ff4440 | 938 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
939 | return; |
940 | ||
661553b9 | 941 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 942 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 943 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
944 | |
945 | called = true; | |
9f7065da TL |
946 | } |
947 | ||
03e128ca | 948 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 949 | { |
ab985f0f TKD |
950 | void __iomem *base = bank->base; |
951 | u32 l = 0xffffffff; | |
2fae7fbe | 952 | |
ab985f0f TKD |
953 | if (bank->width == 16) |
954 | l = 0xffff; | |
955 | ||
d0d665a8 | 956 | if (bank->is_mpuio) { |
661553b9 | 957 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 958 | return; |
2fae7fbe | 959 | } |
ab985f0f | 960 | |
8ee1de65 | 961 | omap_gpio_rmw(base + bank->regs->irqenable, l, |
a0e827c6 | 962 | bank->regs->irqenable_inv); |
8ee1de65 | 963 | omap_gpio_rmw(base + bank->regs->irqstatus, l, |
a0e827c6 | 964 | !bank->regs->irqenable_inv); |
ab985f0f | 965 | if (bank->regs->debounce_en) |
661553b9 | 966 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 967 | |
2dc983c5 | 968 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 969 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
970 | /* Initialize interface clk ungated, module enabled */ |
971 | if (bank->regs->ctrl) | |
661553b9 | 972 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
973 | } |
974 | ||
46824e22 | 975 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 976 | { |
81930328 | 977 | struct gpio_irq_chip *irq; |
2fae7fbe | 978 | static int gpio; |
088413bc | 979 | const char *label; |
fb655f57 | 980 | int irq_base = 0; |
6ef7f385 | 981 | int ret; |
2fae7fbe | 982 | |
2fae7fbe VC |
983 | /* |
984 | * REVISIT eventually switch from OMAP-specific gpio structs | |
985 | * over to the generic ones | |
986 | */ | |
987 | bank->chip.request = omap_gpio_request; | |
988 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
989 | bank->chip.get_direction = omap_gpio_get_direction; |
990 | bank->chip.direction_input = omap_gpio_input; | |
991 | bank->chip.get = omap_gpio_get; | |
442af140 | 992 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 993 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 994 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 995 | bank->chip.set = omap_gpio_set; |
442af140 | 996 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 997 | if (bank->is_mpuio) { |
2fae7fbe | 998 | bank->chip.label = "mpuio"; |
6ed87c5b | 999 | if (bank->regs->wkup_en) |
58383c78 | 1000 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1001 | bank->chip.base = OMAP_MPUIO(0); |
1002 | } else { | |
088413bc LW |
1003 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1004 | gpio, gpio + bank->width - 1); | |
1005 | if (!label) | |
1006 | return -ENOMEM; | |
1007 | bank->chip.label = label; | |
2fae7fbe | 1008 | bank->chip.base = gpio; |
2fae7fbe | 1009 | } |
d5f46247 | 1010 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1011 | |
fb655f57 JMC |
1012 | #ifdef CONFIG_ARCH_OMAP1 |
1013 | /* | |
1014 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1015 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1016 | */ | |
2ed36f30 BG |
1017 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1018 | -1, 0, bank->width, 0); | |
fb655f57 | 1019 | if (irq_base < 0) { |
7b1e5dc8 | 1020 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1021 | return -ENODEV; |
1022 | } | |
1023 | #endif | |
1024 | ||
d2d05c65 | 1025 | /* MPUIO is a bit different, reading IRQ status clears it */ |
693de831 RK |
1026 | if (bank->is_mpuio && !bank->regs->wkup_en) |
1027 | irqc->irq_set_wake = NULL; | |
d2d05c65 | 1028 | |
81930328 GS |
1029 | irq = &bank->chip.irq; |
1030 | irq->chip = irqc; | |
1031 | irq->handler = handle_bad_irq; | |
1032 | irq->default_type = IRQ_TYPE_NONE; | |
1033 | irq->num_parents = 1; | |
1034 | irq->parents = &bank->irq; | |
1035 | irq->first = irq_base; | |
fb655f57 | 1036 | |
81930328 | 1037 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1038 | if (ret) { |
7b1e5dc8 | 1039 | dev_err(bank->chip.parent, |
81930328 GS |
1040 | "Could not register gpio chip %d\n", ret); |
1041 | return ret; | |
fb655f57 JMC |
1042 | } |
1043 | ||
7b1e5dc8 GS |
1044 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1045 | omap_gpio_irq_handler, | |
1046 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1047 | if (ret) |
1048 | gpiochip_remove(&bank->chip); | |
1049 | ||
81930328 GS |
1050 | if (!bank->is_mpuio) |
1051 | gpio += bank->width; | |
1052 | ||
450fa54c | 1053 | return ret; |
2fae7fbe VC |
1054 | } |
1055 | ||
7c68571f | 1056 | static void omap_gpio_init_context(struct gpio_bank *p) |
b764a586 | 1057 | { |
18bd49c4 | 1058 | const struct omap_gpio_reg_offs *regs = p->regs; |
7c68571f | 1059 | void __iomem *base = p->base; |
b764a586 | 1060 | |
7c68571f AB |
1061 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1062 | p->context.oe = readl_relaxed(base + regs->direction); | |
1063 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1064 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1065 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1066 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1067 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1068 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1069 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
9a302781 | 1070 | p->context.dataout = readl_relaxed(base + regs->dataout); |
b764a586 | 1071 | |
7c68571f | 1072 | p->context_valid = true; |
b764a586 TL |
1073 | } |
1074 | ||
7c68571f | 1075 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
5e1c5ff4 | 1076 | { |
18bd49c4 | 1077 | const struct omap_gpio_reg_offs *regs = bank->regs; |
9c7f798d RK |
1078 | void __iomem *base = bank->base; |
1079 | ||
1080 | writel_relaxed(bank->context.wake_en, base + regs->wkup_en); | |
1081 | writel_relaxed(bank->context.ctrl, base + regs->ctrl); | |
1082 | writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); | |
1083 | writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); | |
1084 | writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); | |
1085 | writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); | |
1086 | writel_relaxed(bank->context.dataout, base + regs->dataout); | |
1087 | writel_relaxed(bank->context.oe, base + regs->direction); | |
9f7065da | 1088 | |
7c68571f | 1089 | if (bank->dbck_enable_mask) { |
9c7f798d | 1090 | writel_relaxed(bank->context.debounce, base + regs->debounce); |
7c68571f | 1091 | writel_relaxed(bank->context.debounce_en, |
9c7f798d | 1092 | base + regs->debounce_en); |
b764a586 TL |
1093 | } |
1094 | ||
9c7f798d RK |
1095 | writel_relaxed(bank->context.irqenable1, base + regs->irqenable); |
1096 | writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); | |
cac089f9 TL |
1097 | } |
1098 | ||
b764a586 | 1099 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1100 | { |
b764a586 | 1101 | struct device *dev = bank->chip.parent; |
21e2118f | 1102 | void __iomem *base = bank->base; |
a522f1d0 | 1103 | u32 mask, nowake; |
21e2118f TL |
1104 | |
1105 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1106 | |
b3c64bc3 KH |
1107 | if (!bank->enabled_non_wakeup_gpios) |
1108 | goto update_gpio_context_count; | |
1109 | ||
a522f1d0 TL |
1110 | /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */ |
1111 | mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; | |
1112 | mask &= ~bank->context.risingdetect; | |
1113 | bank->saved_datain |= mask; | |
1114 | ||
1115 | /* Check for pending EDGE_RISING, ignore EDGE_BOTH */ | |
1116 | mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; | |
1117 | mask &= ~bank->context.fallingdetect; | |
1118 | bank->saved_datain &= ~mask; | |
1119 | ||
b764a586 | 1120 | if (!may_lose_context) |
41d87cbd | 1121 | goto update_gpio_context_count; |
b764a586 | 1122 | |
2dc983c5 | 1123 | /* |
21e2118f | 1124 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1125 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1126 | * generated. See OMAP2420 Errata item 1.101. | |
1127 | */ | |
21e2118f TL |
1128 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1129 | nowake = bank->enabled_non_wakeup_gpios; | |
8ee1de65 RK |
1130 | omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); |
1131 | omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); | |
21e2118f | 1132 | } |
3f1686a9 | 1133 | |
41d87cbd | 1134 | update_gpio_context_count: |
2dc983c5 TKD |
1135 | if (bank->get_context_loss_count) |
1136 | bank->context_loss_count = | |
7b1e5dc8 | 1137 | bank->get_context_loss_count(dev); |
60a3437d | 1138 | |
a0e827c6 | 1139 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1140 | } |
1141 | ||
b764a586 | 1142 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1143 | { |
b764a586 | 1144 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1145 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1146 | int c; |
8865b9b6 | 1147 | |
352a2d5b JH |
1148 | /* |
1149 | * On the first resume during the probe, the context has not | |
1150 | * been initialised and so initialise it now. Also initialise | |
1151 | * the context loss count. | |
1152 | */ | |
1153 | if (bank->loses_context && !bank->context_valid) { | |
1154 | omap_gpio_init_context(bank); | |
1155 | ||
1156 | if (bank->get_context_loss_count) | |
1157 | bank->context_loss_count = | |
7b1e5dc8 | 1158 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1159 | } |
1160 | ||
a0e827c6 | 1161 | omap_gpio_dbck_enable(bank); |
68942edb | 1162 | |
a2797bea JH |
1163 | if (bank->loses_context) { |
1164 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1165 | omap_gpio_restore_context(bank); |
1166 | } else { | |
7b1e5dc8 | 1167 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1168 | if (c != bank->context_loss_count) { |
1169 | omap_gpio_restore_context(bank); | |
1170 | } else { | |
b764a586 | 1171 | return; |
a2797bea | 1172 | } |
60a3437d | 1173 | } |
21e2118f TL |
1174 | } else { |
1175 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1176 | writel_relaxed(bank->context.fallingdetect, | |
1177 | bank->base + bank->regs->fallingdetect); | |
1178 | writel_relaxed(bank->context.risingdetect, | |
1179 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1180 | } |
43ffcd9a | 1181 | |
661553b9 | 1182 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1183 | |
2dc983c5 TKD |
1184 | /* |
1185 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1186 | * state. If so, generate an IRQ by software. This is | |
1187 | * horribly racy, but it's the best we can do to work around | |
1188 | * this silicon bug. | |
1189 | */ | |
1190 | l ^= bank->saved_datain; | |
1191 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1192 | |
2dc983c5 TKD |
1193 | /* |
1194 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1195 | * configured with falling edge only; and vice versa. | |
1196 | */ | |
c6f31c9e | 1197 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1198 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1199 | |
c6f31c9e | 1200 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1201 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1202 | |
2dc983c5 | 1203 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1204 | gen = l & (~(bank->context.fallingdetect) & |
1205 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1206 | /* Consider all GPIO IRQs needed to be updated */ |
1207 | gen |= gen0 | gen1; | |
82dbb9d3 | 1208 | |
2dc983c5 TKD |
1209 | if (gen) { |
1210 | u32 old0, old1; | |
82dbb9d3 | 1211 | |
661553b9 VK |
1212 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1213 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1214 | |
4e962e89 | 1215 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1216 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1217 | bank->regs->leveldetect0); |
661553b9 | 1218 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1219 | bank->regs->leveldetect1); |
2dc983c5 | 1220 | } |
9ea14d8c | 1221 | |
4e962e89 | 1222 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1223 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1224 | bank->regs->leveldetect0); |
661553b9 | 1225 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1226 | bank->regs->leveldetect1); |
3ac4fa99 | 1227 | } |
661553b9 VK |
1228 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1229 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1230 | } |
2dc983c5 | 1231 | } |
2dc983c5 | 1232 | |
7c68571f AB |
1233 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, |
1234 | unsigned long cmd, void *v) | |
352a2d5b | 1235 | { |
7c68571f AB |
1236 | struct gpio_bank *bank; |
1237 | unsigned long flags; | |
352a2d5b | 1238 | |
7c68571f | 1239 | bank = container_of(nb, struct gpio_bank, nb); |
352a2d5b | 1240 | |
7c68571f AB |
1241 | raw_spin_lock_irqsave(&bank->lock, flags); |
1242 | switch (cmd) { | |
1243 | case CPU_CLUSTER_PM_ENTER: | |
1244 | if (bank->is_suspended) | |
1245 | break; | |
1246 | omap_gpio_idle(bank, true); | |
1247 | break; | |
1248 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1249 | case CPU_CLUSTER_PM_EXIT: | |
1250 | if (bank->is_suspended) | |
1251 | break; | |
1252 | omap_gpio_unidle(bank); | |
1253 | break; | |
1254 | } | |
1255 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
352a2d5b | 1256 | |
7c68571f | 1257 | return NOTIFY_OK; |
b764a586 TL |
1258 | } |
1259 | ||
18bd49c4 | 1260 | static const struct omap_gpio_reg_offs omap2_gpio_regs = { |
384ebe1c BC |
1261 | .revision = OMAP24XX_GPIO_REVISION, |
1262 | .direction = OMAP24XX_GPIO_OE, | |
1263 | .datain = OMAP24XX_GPIO_DATAIN, | |
1264 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1265 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1266 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1267 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1268 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1269 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1270 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1271 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1272 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1273 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1274 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1275 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1276 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1277 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1278 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1279 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1280 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1281 | }; | |
1282 | ||
18bd49c4 | 1283 | static const struct omap_gpio_reg_offs omap4_gpio_regs = { |
384ebe1c BC |
1284 | .revision = OMAP4_GPIO_REVISION, |
1285 | .direction = OMAP4_GPIO_OE, | |
1286 | .datain = OMAP4_GPIO_DATAIN, | |
1287 | .dataout = OMAP4_GPIO_DATAOUT, | |
1288 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1289 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1290 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1291 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
64ea3e90 RK |
1292 | .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, |
1293 | .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, | |
384ebe1c BC |
1294 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, |
1295 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1296 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1297 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1298 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1299 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1300 | .ctrl = OMAP4_GPIO_CTRL, | |
1301 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1302 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1303 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1304 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1305 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1306 | }; | |
1307 | ||
e9a65bb6 | 1308 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1309 | .regs = &omap2_gpio_regs, |
1310 | .bank_width = 32, | |
1311 | .dbck_flag = false, | |
1312 | }; | |
1313 | ||
e9a65bb6 | 1314 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1315 | .regs = &omap2_gpio_regs, |
1316 | .bank_width = 32, | |
1317 | .dbck_flag = true, | |
1318 | }; | |
1319 | ||
e9a65bb6 | 1320 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1321 | .regs = &omap4_gpio_regs, |
1322 | .bank_width = 32, | |
1323 | .dbck_flag = true, | |
1324 | }; | |
1325 | ||
1326 | static const struct of_device_id omap_gpio_match[] = { | |
1327 | { | |
1328 | .compatible = "ti,omap4-gpio", | |
1329 | .data = &omap4_pdata, | |
1330 | }, | |
1331 | { | |
1332 | .compatible = "ti,omap3-gpio", | |
1333 | .data = &omap3_pdata, | |
1334 | }, | |
1335 | { | |
1336 | .compatible = "ti,omap2-gpio", | |
1337 | .data = &omap2_pdata, | |
1338 | }, | |
1339 | { }, | |
1340 | }; | |
1341 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
7c68571f AB |
1342 | |
1343 | static int omap_gpio_probe(struct platform_device *pdev) | |
1344 | { | |
1345 | struct device *dev = &pdev->dev; | |
1346 | struct device_node *node = dev->of_node; | |
1347 | const struct of_device_id *match; | |
1348 | const struct omap_gpio_platform_data *pdata; | |
7c68571f AB |
1349 | struct gpio_bank *bank; |
1350 | struct irq_chip *irqc; | |
1351 | int ret; | |
1352 | ||
1353 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); | |
1354 | ||
1355 | pdata = match ? match->data : dev_get_platdata(dev); | |
1356 | if (!pdata) | |
1357 | return -EINVAL; | |
1358 | ||
1359 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
1360 | if (!bank) | |
1361 | return -ENOMEM; | |
1362 | ||
1363 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); | |
1364 | if (!irqc) | |
1365 | return -ENOMEM; | |
1366 | ||
1367 | irqc->irq_startup = omap_gpio_irq_startup, | |
1368 | irqc->irq_shutdown = omap_gpio_irq_shutdown, | |
693de831 | 1369 | irqc->irq_ack = dummy_irq_chip.irq_ack, |
7c68571f AB |
1370 | irqc->irq_mask = omap_gpio_mask_irq, |
1371 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1372 | irqc->irq_set_type = omap_gpio_irq_type, | |
1373 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1374 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, | |
1375 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
1376 | irqc->name = dev_name(&pdev->dev); | |
1377 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1378 | irqc->parent_device = dev; | |
1379 | ||
1380 | bank->irq = platform_get_irq(pdev, 0); | |
1381 | if (bank->irq <= 0) { | |
1382 | if (!bank->irq) | |
1383 | bank->irq = -ENXIO; | |
1384 | if (bank->irq != -EPROBE_DEFER) | |
1385 | dev_err(dev, | |
1386 | "can't get irq resource ret=%d\n", bank->irq); | |
1387 | return bank->irq; | |
1388 | } | |
1389 | ||
1390 | bank->chip.parent = dev; | |
1391 | bank->chip.owner = THIS_MODULE; | |
1392 | bank->dbck_flag = pdata->dbck_flag; | |
7c68571f AB |
1393 | bank->stride = pdata->bank_stride; |
1394 | bank->width = pdata->bank_width; | |
1395 | bank->is_mpuio = pdata->is_mpuio; | |
1396 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; | |
1397 | bank->regs = pdata->regs; | |
1398 | #ifdef CONFIG_OF_GPIO | |
1399 | bank->chip.of_node = of_node_get(node); | |
384ebe1c BC |
1400 | #endif |
1401 | ||
7c68571f AB |
1402 | if (node) { |
1403 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1404 | bank->loses_context = true; | |
1405 | } else { | |
1406 | bank->loses_context = pdata->loses_context; | |
1407 | ||
1408 | if (bank->loses_context) | |
1409 | bank->get_context_loss_count = | |
1410 | pdata->get_context_loss_count; | |
1411 | } | |
1412 | ||
8ba70595 | 1413 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
7c68571f | 1414 | bank->set_dataout = omap_set_gpio_dataout_reg; |
8ba70595 | 1415 | else |
7c68571f | 1416 | bank->set_dataout = omap_set_gpio_dataout_mask; |
7c68571f | 1417 | |
7c68571f AB |
1418 | raw_spin_lock_init(&bank->lock); |
1419 | raw_spin_lock_init(&bank->wa_lock); | |
1420 | ||
1421 | /* Static mapping, never released */ | |
58f57f86 | 1422 | bank->base = devm_platform_ioremap_resource(pdev, 0); |
7c68571f AB |
1423 | if (IS_ERR(bank->base)) { |
1424 | return PTR_ERR(bank->base); | |
1425 | } | |
1426 | ||
1427 | if (bank->dbck_flag) { | |
1428 | bank->dbck = devm_clk_get(dev, "dbclk"); | |
1429 | if (IS_ERR(bank->dbck)) { | |
1430 | dev_err(dev, | |
1431 | "Could not get gpio dbck. Disable debounce\n"); | |
1432 | bank->dbck_flag = false; | |
1433 | } else { | |
1434 | clk_prepare(bank->dbck); | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | platform_set_drvdata(pdev, bank); | |
1439 | ||
1440 | pm_runtime_enable(dev); | |
1441 | pm_runtime_get_sync(dev); | |
1442 | ||
1443 | if (bank->is_mpuio) | |
1444 | omap_mpuio_init(bank); | |
1445 | ||
1446 | omap_gpio_mod_init(bank); | |
1447 | ||
1448 | ret = omap_gpio_chip_init(bank, irqc); | |
1449 | if (ret) { | |
1450 | pm_runtime_put_sync(dev); | |
1451 | pm_runtime_disable(dev); | |
1452 | if (bank->dbck_flag) | |
1453 | clk_unprepare(bank->dbck); | |
1454 | return ret; | |
1455 | } | |
1456 | ||
1457 | omap_gpio_show_rev(bank); | |
1458 | ||
e6818d29 RK |
1459 | bank->nb.notifier_call = gpio_omap_cpu_notifier; |
1460 | cpu_pm_register_notifier(&bank->nb); | |
7c68571f AB |
1461 | |
1462 | pm_runtime_put(dev); | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | static int omap_gpio_remove(struct platform_device *pdev) | |
1468 | { | |
1469 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1470 | ||
e6818d29 | 1471 | cpu_pm_unregister_notifier(&bank->nb); |
7c68571f AB |
1472 | gpiochip_remove(&bank->chip); |
1473 | pm_runtime_disable(&pdev->dev); | |
1474 | if (bank->dbck_flag) | |
1475 | clk_unprepare(bank->dbck); | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) | |
1481 | { | |
1482 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1483 | unsigned long flags; | |
7c68571f AB |
1484 | |
1485 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1486 | omap_gpio_idle(bank, true); |
1487 | bank->is_suspended = true; | |
7c68571f AB |
1488 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1489 | ||
044e499a | 1490 | return 0; |
7c68571f AB |
1491 | } |
1492 | ||
1493 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1494 | { | |
1495 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1496 | unsigned long flags; | |
7c68571f AB |
1497 | |
1498 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1499 | omap_gpio_unidle(bank); |
1500 | bank->is_suspended = false; | |
7c68571f AB |
1501 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1502 | ||
044e499a | 1503 | return 0; |
7c68571f AB |
1504 | } |
1505 | ||
1506 | static const struct dev_pm_ops gpio_pm_ops = { | |
1507 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, | |
1508 | NULL) | |
1509 | }; | |
1510 | ||
77640aab VC |
1511 | static struct platform_driver omap_gpio_driver = { |
1512 | .probe = omap_gpio_probe, | |
cac089f9 | 1513 | .remove = omap_gpio_remove, |
77640aab VC |
1514 | .driver = { |
1515 | .name = "omap_gpio", | |
55b93c32 | 1516 | .pm = &gpio_pm_ops, |
7c68571f | 1517 | .of_match_table = omap_gpio_match, |
77640aab VC |
1518 | }, |
1519 | }; | |
1520 | ||
5e1c5ff4 | 1521 | /* |
77640aab VC |
1522 | * gpio driver register needs to be done before |
1523 | * machine_init functions access gpio APIs. | |
1524 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1525 | */ |
77640aab | 1526 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1527 | { |
77640aab | 1528 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1529 | } |
77640aab | 1530 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1531 | |
1532 | static void __exit omap_gpio_exit(void) | |
1533 | { | |
1534 | platform_driver_unregister(&omap_gpio_driver); | |
1535 | } | |
1536 | module_exit(omap_gpio_exit); | |
1537 | ||
1538 | MODULE_DESCRIPTION("omap gpio driver"); | |
1539 | MODULE_ALIAS("platform:gpio-omap"); | |
1540 | MODULE_LICENSE("GPL v2"); |