Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
b764a586 | 22 | #include <linux/cpu_pm.h> |
96751fcb | 23 | #include <linux/device.h> |
77640aab | 24 | #include <linux/pm_runtime.h> |
55b93c32 | 25 | #include <linux/pm.h> |
384ebe1c BC |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
b7351b07 | 28 | #include <linux/gpio/driver.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
6d62e216 C |
34 | struct gpio_regs { |
35 | u32 irqenable1; | |
36 | u32 irqenable2; | |
37 | u32 wake_en; | |
38 | u32 ctrl; | |
39 | u32 oe; | |
40 | u32 leveldetect0; | |
41 | u32 leveldetect1; | |
42 | u32 risingdetect; | |
43 | u32 fallingdetect; | |
44 | u32 dataout; | |
ae547354 NM |
45 | u32 debounce; |
46 | u32 debounce_en; | |
6d62e216 C |
47 | }; |
48 | ||
5e1c5ff4 | 49 | struct gpio_bank { |
92105bb7 | 50 | void __iomem *base; |
30cefeac | 51 | int irq; |
3ac4fa99 JY |
52 | u32 non_wakeup_gpios; |
53 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 54 | struct gpio_regs context; |
3ac4fa99 | 55 | u32 saved_datain; |
b144ff6f | 56 | u32 level_mask; |
4318f36b | 57 | u32 toggle_mask; |
4dbada2b | 58 | raw_spinlock_t lock; |
450fa54c | 59 | raw_spinlock_t wa_lock; |
52e31344 | 60 | struct gpio_chip chip; |
89db9482 | 61 | struct clk *dbck; |
b764a586 TL |
62 | struct notifier_block nb; |
63 | unsigned int is_suspended:1; | |
058af1ea | 64 | u32 mod_usage; |
fa365e4d | 65 | u32 irq_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
72f83af9 | 67 | bool dbck_enabled; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
fa87931a | 75 | |
04ebcbd8 | 76 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 77 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
78 | |
79 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
80 | }; |
81 | ||
c8eef65a | 82 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 83 | |
fa365e4d | 84 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 85 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 86 | |
3d009c8c TL |
87 | static void omap_gpio_unmask_irq(struct irq_data *d); |
88 | ||
a0e827c6 | 89 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 90 | { |
fb655f57 | 91 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 92 | return gpiochip_get_data(chip); |
25db711d BC |
93 | } |
94 | ||
a0e827c6 JMC |
95 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
96 | int is_input) | |
5e1c5ff4 | 97 | { |
92105bb7 | 98 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
99 | u32 l; |
100 | ||
fa87931a | 101 | reg += bank->regs->direction; |
661553b9 | 102 | l = readl_relaxed(reg); |
5e1c5ff4 | 103 | if (is_input) |
b1e9fec2 | 104 | l |= BIT(gpio); |
5e1c5ff4 | 105 | else |
b1e9fec2 | 106 | l &= ~(BIT(gpio)); |
661553b9 | 107 | writel_relaxed(l, reg); |
41d87cbd | 108 | bank->context.oe = l; |
5e1c5ff4 TL |
109 | } |
110 | ||
fa87931a KH |
111 | |
112 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 113 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 114 | int enable) |
5e1c5ff4 | 115 | { |
92105bb7 | 116 | void __iomem *reg = bank->base; |
04ebcbd8 | 117 | u32 l = BIT(offset); |
5e1c5ff4 | 118 | |
2c836f7e | 119 | if (enable) { |
fa87931a | 120 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
121 | bank->context.dataout |= l; |
122 | } else { | |
fa87931a | 123 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
124 | bank->context.dataout &= ~l; |
125 | } | |
5e1c5ff4 | 126 | |
661553b9 | 127 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
128 | } |
129 | ||
fa87931a | 130 | /* set data out value using mask register */ |
04ebcbd8 | 131 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 132 | int enable) |
5e1c5ff4 | 133 | { |
fa87931a | 134 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 135 | u32 gpio_bit = BIT(offset); |
fa87931a | 136 | u32 l; |
5e1c5ff4 | 137 | |
661553b9 | 138 | l = readl_relaxed(reg); |
fa87931a KH |
139 | if (enable) |
140 | l |= gpio_bit; | |
141 | else | |
142 | l &= ~gpio_bit; | |
661553b9 | 143 | writel_relaxed(l, reg); |
41d87cbd | 144 | bank->context.dataout = l; |
5e1c5ff4 TL |
145 | } |
146 | ||
a0e827c6 | 147 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 148 | { |
661553b9 | 149 | int l = readl_relaxed(base + reg); |
ece9528e | 150 | |
862ff640 | 151 | if (set) |
ece9528e KH |
152 | l |= mask; |
153 | else | |
154 | l &= ~mask; | |
155 | ||
661553b9 | 156 | writel_relaxed(l, base + reg); |
ece9528e | 157 | } |
92105bb7 | 158 | |
a0e827c6 | 159 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
160 | { |
161 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 162 | clk_enable(bank->dbck); |
72f83af9 | 163 | bank->dbck_enabled = true; |
9e303f22 | 164 | |
661553b9 | 165 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 166 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
167 | } |
168 | } | |
169 | ||
a0e827c6 | 170 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
171 | { |
172 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
173 | /* |
174 | * Disable debounce before cutting it's clock. If debounce is | |
175 | * enabled but the clock is not, GPIO module seems to be unable | |
176 | * to detect events and generate interrupts at least on OMAP3. | |
177 | */ | |
661553b9 | 178 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 179 | |
5d9452e7 | 180 | clk_disable(bank->dbck); |
72f83af9 TKD |
181 | bank->dbck_enabled = false; |
182 | } | |
183 | } | |
184 | ||
168ef3d9 | 185 | /** |
a0e827c6 | 186 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 187 | * @bank: the gpio bank we're acting upon |
4a58d229 | 188 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
189 | * @debounce: debounce time to use |
190 | * | |
e85ec6c3 GS |
191 | * OMAP's debounce time is in 31us steps |
192 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
193 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
194 | * |
195 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 196 | */ |
83977443 DR |
197 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
198 | unsigned debounce) | |
168ef3d9 | 199 | { |
9942da0e | 200 | void __iomem *reg; |
168ef3d9 FB |
201 | u32 val; |
202 | u32 l; | |
e85ec6c3 | 203 | bool enable = !!debounce; |
168ef3d9 | 204 | |
77640aab | 205 | if (!bank->dbck_flag) |
83977443 | 206 | return -ENOTSUPP; |
77640aab | 207 | |
e85ec6c3 GS |
208 | if (enable) { |
209 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
210 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
211 | return -EINVAL; | |
e85ec6c3 | 212 | } |
168ef3d9 | 213 | |
4a58d229 | 214 | l = BIT(offset); |
168ef3d9 | 215 | |
5d9452e7 | 216 | clk_enable(bank->dbck); |
9942da0e | 217 | reg = bank->base + bank->regs->debounce; |
661553b9 | 218 | writel_relaxed(debounce, reg); |
168ef3d9 | 219 | |
9942da0e | 220 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 221 | val = readl_relaxed(reg); |
168ef3d9 | 222 | |
e85ec6c3 | 223 | if (enable) |
168ef3d9 | 224 | val |= l; |
6fd9c421 | 225 | else |
168ef3d9 | 226 | val &= ~l; |
f7ec0b0b | 227 | bank->dbck_enable_mask = val; |
168ef3d9 | 228 | |
661553b9 | 229 | writel_relaxed(val, reg); |
5d9452e7 | 230 | clk_disable(bank->dbck); |
6fd9c421 TKD |
231 | /* |
232 | * Enable debounce clock per module. | |
233 | * This call is mandatory because in omap_gpio_request() when | |
234 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
235 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
236 | * used within _gpio_dbck_enable() is still not initialized at | |
237 | * that point. Therefore we have to enable dbck here. | |
238 | */ | |
a0e827c6 | 239 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
240 | if (bank->dbck_enable_mask) { |
241 | bank->context.debounce = debounce; | |
242 | bank->context.debounce_en = val; | |
243 | } | |
83977443 DR |
244 | |
245 | return 0; | |
168ef3d9 FB |
246 | } |
247 | ||
c9c55d92 | 248 | /** |
a0e827c6 | 249 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 250 | * @bank: the gpio bank we're acting upon |
4a58d229 | 251 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
252 | * |
253 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
254 | * this is the only gpio in this bank using debounce, then clear the debounce | |
255 | * time too. The debounce clock will also be disabled when calling this function | |
256 | * if this is the only gpio in the bank using debounce. | |
257 | */ | |
4a58d229 | 258 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 259 | { |
4a58d229 | 260 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
261 | |
262 | if (!bank->dbck_flag) | |
263 | return; | |
264 | ||
265 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
266 | return; | |
267 | ||
268 | bank->dbck_enable_mask &= ~gpio_bit; | |
269 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 270 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
271 | bank->base + bank->regs->debounce_en); |
272 | ||
273 | if (!bank->dbck_enable_mask) { | |
274 | bank->context.debounce = 0; | |
661553b9 | 275 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 276 | bank->regs->debounce); |
5d9452e7 | 277 | clk_disable(bank->dbck); |
c9c55d92 JH |
278 | bank->dbck_enabled = false; |
279 | } | |
280 | } | |
281 | ||
da38ef3e TL |
282 | /* |
283 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
284 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
285 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
286 | * are capable waking up the system from off mode. | |
287 | */ | |
288 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
289 | { | |
290 | u32 no_wake = bank->non_wakeup_gpios; | |
291 | ||
292 | if (no_wake) | |
293 | return !!(~no_wake & gpio_mask); | |
294 | ||
295 | return false; | |
296 | } | |
297 | ||
a0e827c6 | 298 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 299 | unsigned trigger) |
5e1c5ff4 | 300 | { |
3ac4fa99 | 301 | void __iomem *base = bank->base; |
b1e9fec2 | 302 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 303 | |
a0e827c6 JMC |
304 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
305 | trigger & IRQ_TYPE_LEVEL_LOW); | |
306 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
307 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
e6818d29 RK |
308 | |
309 | /* | |
310 | * We need the edge detection enabled for to allow the GPIO block | |
311 | * to be woken from idle state. Set the appropriate edge detection | |
312 | * in addition to the level detection. | |
313 | */ | |
a0e827c6 | 314 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, |
e6818d29 | 315 | trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); |
a0e827c6 | 316 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, |
e6818d29 | 317 | trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); |
5e571f38 | 318 | |
41d87cbd | 319 | bank->context.leveldetect0 = |
661553b9 | 320 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 321 | bank->context.leveldetect1 = |
661553b9 | 322 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 323 | bank->context.risingdetect = |
661553b9 | 324 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 325 | bank->context.fallingdetect = |
661553b9 | 326 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
327 | |
328 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
00ded24c TL |
329 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
330 | bank->context.wake_en = | |
331 | readl_relaxed(bank->base + bank->regs->wkup_en); | |
41d87cbd | 332 | } |
5e571f38 | 333 | |
55b220ca | 334 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 335 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
336 | /* |
337 | * Log the edge gpio and manually trigger the IRQ | |
338 | * after resume if the input level changes | |
339 | * to avoid irq lost during PER RET/OFF mode | |
340 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
341 | */ | |
342 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
343 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
344 | else | |
345 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
346 | } | |
5eb3bb9c | 347 | |
9ea14d8c | 348 | bank->level_mask = |
661553b9 VK |
349 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
350 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
351 | } |
352 | ||
9198bcd3 | 353 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
354 | /* |
355 | * This only applies to chips that can't do both rising and falling edge | |
356 | * detection at once. For all other chips, this function is a noop. | |
357 | */ | |
a0e827c6 | 358 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
359 | { |
360 | void __iomem *reg = bank->base; | |
361 | u32 l = 0; | |
362 | ||
5e571f38 | 363 | if (!bank->regs->irqctrl) |
4318f36b | 364 | return; |
5e571f38 TKD |
365 | |
366 | reg += bank->regs->irqctrl; | |
4318f36b | 367 | |
661553b9 | 368 | l = readl_relaxed(reg); |
4318f36b | 369 | if ((l >> gpio) & 1) |
b1e9fec2 | 370 | l &= ~(BIT(gpio)); |
4318f36b | 371 | else |
b1e9fec2 | 372 | l |= BIT(gpio); |
4318f36b | 373 | |
661553b9 | 374 | writel_relaxed(l, reg); |
4318f36b | 375 | } |
5e571f38 | 376 | #else |
a0e827c6 | 377 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 378 | #endif |
4318f36b | 379 | |
a0e827c6 JMC |
380 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
381 | unsigned trigger) | |
92105bb7 TL |
382 | { |
383 | void __iomem *reg = bank->base; | |
5e571f38 | 384 | void __iomem *base = bank->base; |
92105bb7 | 385 | u32 l = 0; |
5e1c5ff4 | 386 | |
5e571f38 | 387 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 388 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
389 | } else if (bank->regs->irqctrl) { |
390 | reg += bank->regs->irqctrl; | |
391 | ||
661553b9 | 392 | l = readl_relaxed(reg); |
29501577 | 393 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 394 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 395 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 396 | l |= BIT(gpio); |
6cab4860 | 397 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 398 | l &= ~(BIT(gpio)); |
92105bb7 | 399 | else |
5e571f38 TKD |
400 | return -EINVAL; |
401 | ||
661553b9 | 402 | writel_relaxed(l, reg); |
5e571f38 | 403 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 404 | if (gpio & 0x08) |
5e571f38 | 405 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 406 | else |
5e571f38 TKD |
407 | reg += bank->regs->edgectrl1; |
408 | ||
5e1c5ff4 | 409 | gpio &= 0x07; |
661553b9 | 410 | l = readl_relaxed(reg); |
5e1c5ff4 | 411 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 412 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 413 | l |= 2 << (gpio << 1); |
6cab4860 | 414 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 415 | l |= BIT(gpio << 1); |
5e571f38 TKD |
416 | |
417 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 418 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 419 | bank->context.wake_en = |
661553b9 VK |
420 | readl_relaxed(bank->base + bank->regs->wkup_en); |
421 | writel_relaxed(l, reg); | |
5e1c5ff4 | 422 | } |
92105bb7 | 423 | return 0; |
5e1c5ff4 TL |
424 | } |
425 | ||
a0e827c6 | 426 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
427 | { |
428 | if (bank->regs->pinctrl) { | |
429 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
430 | ||
431 | /* Claim the pin for MPU */ | |
b1e9fec2 | 432 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
433 | } |
434 | ||
435 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
436 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
437 | u32 ctrl; | |
438 | ||
661553b9 | 439 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
440 | /* Module is enabled, clocks are not gated */ |
441 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 442 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
443 | bank->context.ctrl = ctrl; |
444 | } | |
445 | } | |
446 | ||
a0e827c6 | 447 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
448 | { |
449 | void __iomem *base = bank->base; | |
450 | ||
451 | if (bank->regs->wkup_en && | |
452 | !LINE_USED(bank->mod_usage, offset) && | |
453 | !LINE_USED(bank->irq_usage, offset)) { | |
454 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 455 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 456 | bank->context.wake_en = |
661553b9 | 457 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
458 | } |
459 | ||
460 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
461 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
462 | u32 ctrl; | |
463 | ||
661553b9 | 464 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
465 | /* Module is disabled, clocks are gated */ |
466 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 467 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
468 | bank->context.ctrl = ctrl; |
469 | } | |
470 | } | |
471 | ||
b2b20045 | 472 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
473 | { |
474 | void __iomem *reg = bank->base + bank->regs->direction; | |
475 | ||
b2b20045 | 476 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
477 | } |
478 | ||
37e14ecf | 479 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
480 | { |
481 | if (!LINE_USED(bank->mod_usage, offset)) { | |
482 | omap_enable_gpio_module(bank, offset); | |
483 | omap_set_gpio_direction(bank, offset, 1); | |
484 | } | |
37e14ecf | 485 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
486 | } |
487 | ||
a0e827c6 | 488 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 489 | { |
a0e827c6 | 490 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 491 | int retval; |
a6472533 | 492 | unsigned long flags; |
ea5fbe8d | 493 | unsigned offset = d->hwirq; |
92105bb7 | 494 | |
e5c56ed3 | 495 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 496 | return -EINVAL; |
e5c56ed3 | 497 | |
9ea14d8c TKD |
498 | if (!bank->regs->leveldetect0 && |
499 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
500 | return -EINVAL; |
501 | ||
4dbada2b | 502 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 503 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 504 | if (retval) { |
627c89b4 | 505 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 506 | goto error; |
977bd8a9 | 507 | } |
37e14ecf | 508 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 509 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 510 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
511 | retval = -EINVAL; |
512 | goto error; | |
fac7fa16 | 513 | } |
4dbada2b | 514 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
515 | |
516 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 517 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 518 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
519 | /* |
520 | * Edge IRQs are already cleared/acked in irq_handler and | |
521 | * not need to be masked, as result handle_edge_irq() | |
522 | * logic is excessed here and may cause lose of interrupts. | |
523 | * So just use handle_simple_irq. | |
524 | */ | |
525 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 526 | |
1562e461 GS |
527 | return 0; |
528 | ||
529 | error: | |
92105bb7 | 530 | return retval; |
5e1c5ff4 TL |
531 | } |
532 | ||
a0e827c6 | 533 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 534 | { |
92105bb7 | 535 | void __iomem *reg = bank->base; |
5e1c5ff4 | 536 | |
eef4bec7 | 537 | reg += bank->regs->irqstatus; |
661553b9 | 538 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
539 | |
540 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
541 | if (bank->regs->irqstatus2) { |
542 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 543 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 544 | } |
bedfd154 RQ |
545 | |
546 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 547 | readl_relaxed(reg); |
5e1c5ff4 TL |
548 | } |
549 | ||
9943f261 GS |
550 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
551 | unsigned offset) | |
5e1c5ff4 | 552 | { |
9943f261 | 553 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
554 | } |
555 | ||
a0e827c6 | 556 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
557 | { |
558 | void __iomem *reg = bank->base; | |
99c47707 | 559 | u32 l; |
b1e9fec2 | 560 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 561 | |
28f3b5a0 | 562 | reg += bank->regs->irqenable; |
661553b9 | 563 | l = readl_relaxed(reg); |
28f3b5a0 | 564 | if (bank->regs->irqenable_inv) |
99c47707 ID |
565 | l = ~l; |
566 | l &= mask; | |
567 | return l; | |
ea6dedd7 ID |
568 | } |
569 | ||
a0e827c6 | 570 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 571 | { |
92105bb7 | 572 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
573 | u32 l; |
574 | ||
28f3b5a0 KH |
575 | if (bank->regs->set_irqenable) { |
576 | reg += bank->regs->set_irqenable; | |
577 | l = gpio_mask; | |
2a900eb7 | 578 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
579 | } else { |
580 | reg += bank->regs->irqenable; | |
661553b9 | 581 | l = readl_relaxed(reg); |
28f3b5a0 KH |
582 | if (bank->regs->irqenable_inv) |
583 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
584 | else |
585 | l |= gpio_mask; | |
2a900eb7 | 586 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
587 | } |
588 | ||
661553b9 | 589 | writel_relaxed(l, reg); |
28f3b5a0 KH |
590 | } |
591 | ||
a0e827c6 | 592 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
593 | { |
594 | void __iomem *reg = bank->base; | |
595 | u32 l; | |
596 | ||
597 | if (bank->regs->clr_irqenable) { | |
598 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 599 | l = gpio_mask; |
2a900eb7 | 600 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
601 | } else { |
602 | reg += bank->regs->irqenable; | |
661553b9 | 603 | l = readl_relaxed(reg); |
28f3b5a0 | 604 | if (bank->regs->irqenable_inv) |
56739a69 | 605 | l |= gpio_mask; |
92105bb7 | 606 | else |
28f3b5a0 | 607 | l &= ~gpio_mask; |
2a900eb7 | 608 | bank->context.irqenable1 = l; |
5e1c5ff4 | 609 | } |
28f3b5a0 | 610 | |
661553b9 | 611 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
612 | } |
613 | ||
9943f261 GS |
614 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
615 | unsigned offset, int enable) | |
5e1c5ff4 | 616 | { |
8276536c | 617 | if (enable) |
9943f261 | 618 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 619 | else |
9943f261 | 620 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
621 | } |
622 | ||
92105bb7 | 623 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 624 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 625 | { |
a0e827c6 | 626 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 627 | |
0c0451e7 | 628 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
629 | } |
630 | ||
5e1c5ff4 TL |
631 | /* |
632 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
633 | * avoid missing GPIO interrupts for other lines in the bank. | |
634 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
635 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
636 | * If we wait to unmask individual GPIO lines in the bank after the | |
637 | * line's interrupt handler has been run, we may miss some nested | |
638 | * interrupts. | |
639 | */ | |
450fa54c | 640 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 641 | { |
92105bb7 | 642 | void __iomem *isr_reg = NULL; |
395373c7 | 643 | u32 enabled, isr, edge; |
3513cdec | 644 | unsigned int bit; |
450fa54c GS |
645 | struct gpio_bank *bank = gpiobank; |
646 | unsigned long wa_lock_flags; | |
235f1eb1 | 647 | unsigned long lock_flags; |
5e1c5ff4 | 648 | |
eef4bec7 | 649 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
650 | if (WARN_ON(!isr_reg)) |
651 | goto exit; | |
652 | ||
5284521a TL |
653 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
654 | "gpio irq%i while runtime suspended?\n", irq)) | |
655 | return IRQ_NONE; | |
450fa54c | 656 | |
e83507b7 | 657 | while (1) { |
235f1eb1 GS |
658 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
659 | ||
a0e827c6 | 660 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 661 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 662 | |
395373c7 RK |
663 | /* |
664 | * Clear edge sensitive interrupts before calling handler(s) | |
665 | * so subsequent edge transitions are not missed while the | |
666 | * handlers are running. | |
667 | */ | |
668 | edge = isr & ~bank->level_mask; | |
669 | if (edge) | |
670 | omap_clear_gpio_irqbank(bank, edge); | |
6e60e79a | 671 | |
235f1eb1 GS |
672 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
673 | ||
92105bb7 TL |
674 | if (!isr) |
675 | break; | |
676 | ||
3513cdec JH |
677 | while (isr) { |
678 | bit = __ffs(isr); | |
b1e9fec2 | 679 | isr &= ~(BIT(bit)); |
25db711d | 680 | |
235f1eb1 | 681 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
682 | /* |
683 | * Some chips can't respond to both rising and falling | |
684 | * at the same time. If this irq was requested with | |
685 | * both flags, we need to flip the ICR data for the IRQ | |
686 | * to respond to the IRQ for the opposite direction. | |
687 | * This will be indicated in the bank toggle_mask. | |
688 | */ | |
b1e9fec2 | 689 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 690 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 691 | |
235f1eb1 GS |
692 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
693 | ||
450fa54c GS |
694 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
695 | ||
f0fbe7bc | 696 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 697 | bit)); |
450fa54c GS |
698 | |
699 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
700 | wa_lock_flags); | |
92105bb7 | 701 | } |
1a8bfa1e | 702 | } |
b1cc4c55 | 703 | exit: |
450fa54c | 704 | return IRQ_HANDLED; |
5e1c5ff4 TL |
705 | } |
706 | ||
3d009c8c TL |
707 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
708 | { | |
709 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 710 | unsigned long flags; |
37e14ecf | 711 | unsigned offset = d->hwirq; |
3d009c8c | 712 | |
4dbada2b | 713 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
714 | |
715 | if (!LINE_USED(bank->mod_usage, offset)) | |
716 | omap_set_gpio_direction(bank, offset, 1); | |
717 | else if (!omap_gpio_is_input(bank, offset)) | |
718 | goto err; | |
719 | omap_enable_gpio_module(bank, offset); | |
720 | bank->irq_usage |= BIT(offset); | |
721 | ||
4dbada2b | 722 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
723 | omap_gpio_unmask_irq(d); |
724 | ||
725 | return 0; | |
121dcb76 | 726 | err: |
4dbada2b | 727 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 728 | return -EINVAL; |
3d009c8c TL |
729 | } |
730 | ||
a0e827c6 | 731 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 732 | { |
a0e827c6 | 733 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 734 | unsigned long flags; |
9943f261 | 735 | unsigned offset = d->hwirq; |
4196dd6b | 736 | |
4dbada2b | 737 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 738 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 | 739 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 RK |
740 | omap_clear_gpio_irqstatus(bank, offset); |
741 | omap_set_gpio_irqenable(bank, offset, 0); | |
6e96c1b5 GS |
742 | if (!LINE_USED(bank->mod_usage, offset)) |
743 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 744 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 745 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
746 | } |
747 | ||
748 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
749 | { | |
750 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
751 | ||
46748073 | 752 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
753 | } |
754 | ||
755 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
756 | { | |
757 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 758 | |
46748073 | 759 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
760 | } |
761 | ||
a0e827c6 | 762 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 763 | { |
a0e827c6 | 764 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 765 | unsigned offset = d->hwirq; |
85ec7b97 | 766 | unsigned long flags; |
5e1c5ff4 | 767 | |
4dbada2b | 768 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 | 769 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 | 770 | omap_set_gpio_irqenable(bank, offset, 0); |
4dbada2b | 771 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
772 | } |
773 | ||
a0e827c6 | 774 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 775 | { |
a0e827c6 | 776 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 777 | unsigned offset = d->hwirq; |
8c04a176 | 778 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 779 | unsigned long flags; |
55b6019a | 780 | |
4dbada2b | 781 | raw_spin_lock_irqsave(&bank->lock, flags); |
d01849f7 RK |
782 | omap_set_gpio_irqenable(bank, offset, 1); |
783 | ||
784 | /* | |
785 | * For level-triggered GPIOs, clearing must be done after the source | |
786 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
787 | * after enabing the interrupt to clear the wakeup status. | |
788 | */ | |
c859e0d4 RK |
789 | if (bank->regs->leveldetect0 && bank->regs->wkup_en && |
790 | trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
9943f261 | 791 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 792 | |
c859e0d4 RK |
793 | if (trigger) |
794 | omap_set_gpio_triggering(bank, offset, trigger); | |
795 | ||
4dbada2b | 796 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
797 | } |
798 | ||
e5c56ed3 DB |
799 | /*---------------------------------------------------------------------*/ |
800 | ||
79ee031f | 801 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 802 | { |
a3f4f728 | 803 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
804 | void __iomem *mask_reg = bank->base + |
805 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 806 | unsigned long flags; |
11a78b79 | 807 | |
4dbada2b | 808 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 809 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 810 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
811 | |
812 | return 0; | |
813 | } | |
814 | ||
79ee031f | 815 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 816 | { |
a3f4f728 | 817 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
818 | void __iomem *mask_reg = bank->base + |
819 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 820 | unsigned long flags; |
11a78b79 | 821 | |
4dbada2b | 822 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 823 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 824 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
825 | |
826 | return 0; | |
827 | } | |
828 | ||
47145210 | 829 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
830 | .suspend_noirq = omap_mpuio_suspend_noirq, |
831 | .resume_noirq = omap_mpuio_resume_noirq, | |
832 | }; | |
833 | ||
3c437ffd | 834 | /* use platform_driver for this. */ |
11a78b79 | 835 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
836 | .driver = { |
837 | .name = "mpuio", | |
79ee031f | 838 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
839 | }, |
840 | }; | |
841 | ||
842 | static struct platform_device omap_mpuio_device = { | |
843 | .name = "mpuio", | |
844 | .id = -1, | |
845 | .dev = { | |
846 | .driver = &omap_mpuio_driver.driver, | |
847 | } | |
848 | /* could list the /proc/iomem resources */ | |
849 | }; | |
850 | ||
a0e827c6 | 851 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 852 | { |
77640aab | 853 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 854 | |
11a78b79 DB |
855 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
856 | (void) platform_device_register(&omap_mpuio_device); | |
857 | } | |
858 | ||
e5c56ed3 | 859 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 860 | |
dfbc6c7a RK |
861 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
862 | { | |
863 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
864 | unsigned long flags; | |
865 | ||
866 | pm_runtime_get_sync(chip->parent); | |
867 | ||
868 | raw_spin_lock_irqsave(&bank->lock, flags); | |
869 | omap_enable_gpio_module(bank, offset); | |
870 | bank->mod_usage |= BIT(offset); | |
871 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
876 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |
877 | { | |
878 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
879 | unsigned long flags; | |
880 | ||
881 | raw_spin_lock_irqsave(&bank->lock, flags); | |
882 | bank->mod_usage &= ~(BIT(offset)); | |
883 | if (!LINE_USED(bank->irq_usage, offset)) { | |
884 | omap_set_gpio_direction(bank, offset, 1); | |
885 | omap_clear_gpio_debounce(bank, offset); | |
886 | } | |
887 | omap_disable_gpio_module(bank, offset); | |
888 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
889 | ||
890 | pm_runtime_put(chip->parent); | |
891 | } | |
892 | ||
a0e827c6 | 893 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e | 894 | { |
40bb2273 | 895 | struct gpio_bank *bank = gpiochip_get_data(chip); |
9370084e | 896 | |
40bb2273 RK |
897 | return !!(readl_relaxed(bank->base + bank->regs->direction) & |
898 | BIT(offset)); | |
9370084e YY |
899 | } |
900 | ||
a0e827c6 | 901 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
902 | { |
903 | struct gpio_bank *bank; | |
904 | unsigned long flags; | |
905 | ||
d99f7aec | 906 | bank = gpiochip_get_data(chip); |
4dbada2b | 907 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 908 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 909 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
910 | return 0; |
911 | } | |
912 | ||
a0e827c6 | 913 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 914 | { |
5ca5f92c RK |
915 | struct gpio_bank *bank = gpiochip_get_data(chip); |
916 | void __iomem *reg; | |
b37c45b8 | 917 | |
b2b20045 | 918 | if (omap_gpio_is_input(bank, offset)) |
5ca5f92c | 919 | reg = bank->base + bank->regs->datain; |
b37c45b8 | 920 | else |
5ca5f92c RK |
921 | reg = bank->base + bank->regs->dataout; |
922 | ||
923 | return (readl_relaxed(reg) & BIT(offset)) != 0; | |
52e31344 DB |
924 | } |
925 | ||
a0e827c6 | 926 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
927 | { |
928 | struct gpio_bank *bank; | |
929 | unsigned long flags; | |
930 | ||
d99f7aec | 931 | bank = gpiochip_get_data(chip); |
4dbada2b | 932 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 933 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 934 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 935 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 936 | return 0; |
52e31344 DB |
937 | } |
938 | ||
442af140 JK |
939 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
940 | unsigned long *bits) | |
941 | { | |
942 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
6653dd88 RK |
943 | void __iomem *base = bank->base; |
944 | u32 direction, m, val = 0; | |
945 | ||
946 | direction = readl_relaxed(base + bank->regs->direction); | |
442af140 | 947 | |
6653dd88 RK |
948 | m = direction & *mask; |
949 | if (m) | |
950 | val |= readl_relaxed(base + bank->regs->datain) & m; | |
442af140 | 951 | |
6653dd88 RK |
952 | m = ~direction & *mask; |
953 | if (m) | |
954 | val |= readl_relaxed(base + bank->regs->dataout) & m; | |
442af140 | 955 | |
6653dd88 | 956 | *bits = val; |
442af140 JK |
957 | |
958 | return 0; | |
959 | } | |
960 | ||
a0e827c6 JMC |
961 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
962 | unsigned debounce) | |
168ef3d9 FB |
963 | { |
964 | struct gpio_bank *bank; | |
965 | unsigned long flags; | |
83977443 | 966 | int ret; |
168ef3d9 | 967 | |
d99f7aec | 968 | bank = gpiochip_get_data(chip); |
77640aab | 969 | |
4dbada2b | 970 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 971 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 972 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 973 | |
83977443 DR |
974 | if (ret) |
975 | dev_info(chip->parent, | |
976 | "Could not set line %u debounce to %u microseconds (%d)", | |
977 | offset, debounce, ret); | |
978 | ||
979 | return ret; | |
168ef3d9 FB |
980 | } |
981 | ||
2956b5d9 MW |
982 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
983 | unsigned long config) | |
984 | { | |
985 | u32 debounce; | |
986 | ||
987 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
988 | return -ENOTSUPP; | |
989 | ||
990 | debounce = pinconf_to_config_argument(config); | |
991 | return omap_gpio_debounce(chip, offset, debounce); | |
992 | } | |
993 | ||
a0e827c6 | 994 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
995 | { |
996 | struct gpio_bank *bank; | |
997 | unsigned long flags; | |
998 | ||
d99f7aec | 999 | bank = gpiochip_get_data(chip); |
4dbada2b | 1000 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1001 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1002 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1003 | } |
1004 | ||
442af140 JK |
1005 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
1006 | unsigned long *bits) | |
1007 | { | |
1008 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
8ba70595 | 1009 | void __iomem *reg = bank->base + bank->regs->dataout; |
442af140 | 1010 | unsigned long flags; |
8ba70595 | 1011 | u32 l; |
442af140 JK |
1012 | |
1013 | raw_spin_lock_irqsave(&bank->lock, flags); | |
8ba70595 RK |
1014 | l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); |
1015 | writel_relaxed(l, reg); | |
1016 | bank->context.dataout = l; | |
442af140 JK |
1017 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1018 | } | |
1019 | ||
52e31344 DB |
1020 | /*---------------------------------------------------------------------*/ |
1021 | ||
e4b2ae7a | 1022 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1023 | { |
e5ff4440 | 1024 | static bool called; |
9f7065da TL |
1025 | u32 rev; |
1026 | ||
e5ff4440 | 1027 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1028 | return; |
1029 | ||
661553b9 | 1030 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1031 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1032 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1033 | |
1034 | called = true; | |
9f7065da TL |
1035 | } |
1036 | ||
03e128ca | 1037 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1038 | { |
ab985f0f TKD |
1039 | void __iomem *base = bank->base; |
1040 | u32 l = 0xffffffff; | |
2fae7fbe | 1041 | |
ab985f0f TKD |
1042 | if (bank->width == 16) |
1043 | l = 0xffff; | |
1044 | ||
d0d665a8 | 1045 | if (bank->is_mpuio) { |
661553b9 | 1046 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1047 | return; |
2fae7fbe | 1048 | } |
ab985f0f | 1049 | |
a0e827c6 JMC |
1050 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1051 | bank->regs->irqenable_inv); | |
1052 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1053 | !bank->regs->irqenable_inv); | |
ab985f0f | 1054 | if (bank->regs->debounce_en) |
661553b9 | 1055 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1056 | |
2dc983c5 | 1057 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1058 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1059 | /* Initialize interface clk ungated, module enabled */ |
1060 | if (bank->regs->ctrl) | |
661553b9 | 1061 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1062 | } |
1063 | ||
46824e22 | 1064 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1065 | { |
81930328 | 1066 | struct gpio_irq_chip *irq; |
2fae7fbe | 1067 | static int gpio; |
088413bc | 1068 | const char *label; |
fb655f57 | 1069 | int irq_base = 0; |
6ef7f385 | 1070 | int ret; |
2fae7fbe | 1071 | |
2fae7fbe VC |
1072 | /* |
1073 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1074 | * over to the generic ones | |
1075 | */ | |
1076 | bank->chip.request = omap_gpio_request; | |
1077 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1078 | bank->chip.get_direction = omap_gpio_get_direction; |
1079 | bank->chip.direction_input = omap_gpio_input; | |
1080 | bank->chip.get = omap_gpio_get; | |
442af140 | 1081 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1082 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1083 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1084 | bank->chip.set = omap_gpio_set; |
442af140 | 1085 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1086 | if (bank->is_mpuio) { |
2fae7fbe | 1087 | bank->chip.label = "mpuio"; |
6ed87c5b | 1088 | if (bank->regs->wkup_en) |
58383c78 | 1089 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1090 | bank->chip.base = OMAP_MPUIO(0); |
1091 | } else { | |
088413bc LW |
1092 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1093 | gpio, gpio + bank->width - 1); | |
1094 | if (!label) | |
1095 | return -ENOMEM; | |
1096 | bank->chip.label = label; | |
2fae7fbe | 1097 | bank->chip.base = gpio; |
2fae7fbe | 1098 | } |
d5f46247 | 1099 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1100 | |
fb655f57 JMC |
1101 | #ifdef CONFIG_ARCH_OMAP1 |
1102 | /* | |
1103 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1104 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1105 | */ | |
2ed36f30 BG |
1106 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1107 | -1, 0, bank->width, 0); | |
fb655f57 | 1108 | if (irq_base < 0) { |
7b1e5dc8 | 1109 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1110 | return -ENODEV; |
1111 | } | |
1112 | #endif | |
1113 | ||
d2d05c65 | 1114 | /* MPUIO is a bit different, reading IRQ status clears it */ |
693de831 RK |
1115 | if (bank->is_mpuio && !bank->regs->wkup_en) |
1116 | irqc->irq_set_wake = NULL; | |
d2d05c65 | 1117 | |
81930328 GS |
1118 | irq = &bank->chip.irq; |
1119 | irq->chip = irqc; | |
1120 | irq->handler = handle_bad_irq; | |
1121 | irq->default_type = IRQ_TYPE_NONE; | |
1122 | irq->num_parents = 1; | |
1123 | irq->parents = &bank->irq; | |
1124 | irq->first = irq_base; | |
fb655f57 | 1125 | |
81930328 | 1126 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1127 | if (ret) { |
7b1e5dc8 | 1128 | dev_err(bank->chip.parent, |
81930328 GS |
1129 | "Could not register gpio chip %d\n", ret); |
1130 | return ret; | |
fb655f57 JMC |
1131 | } |
1132 | ||
7b1e5dc8 GS |
1133 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1134 | omap_gpio_irq_handler, | |
1135 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1136 | if (ret) |
1137 | gpiochip_remove(&bank->chip); | |
1138 | ||
81930328 GS |
1139 | if (!bank->is_mpuio) |
1140 | gpio += bank->width; | |
1141 | ||
450fa54c | 1142 | return ret; |
2fae7fbe VC |
1143 | } |
1144 | ||
7c68571f | 1145 | static void omap_gpio_init_context(struct gpio_bank *p) |
b764a586 | 1146 | { |
7c68571f AB |
1147 | struct omap_gpio_reg_offs *regs = p->regs; |
1148 | void __iomem *base = p->base; | |
b764a586 | 1149 | |
7c68571f AB |
1150 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1151 | p->context.oe = readl_relaxed(base + regs->direction); | |
1152 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1153 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1154 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1155 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1156 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1157 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1158 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
b764a586 | 1159 | |
7c68571f AB |
1160 | if (regs->set_dataout && p->regs->clr_dataout) |
1161 | p->context.dataout = readl_relaxed(base + regs->set_dataout); | |
1162 | else | |
1163 | p->context.dataout = readl_relaxed(base + regs->dataout); | |
b764a586 | 1164 | |
7c68571f | 1165 | p->context_valid = true; |
b764a586 TL |
1166 | } |
1167 | ||
7c68571f | 1168 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
5e1c5ff4 | 1169 | { |
7c68571f AB |
1170 | writel_relaxed(bank->context.wake_en, |
1171 | bank->base + bank->regs->wkup_en); | |
1172 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1173 | writel_relaxed(bank->context.leveldetect0, | |
1174 | bank->base + bank->regs->leveldetect0); | |
1175 | writel_relaxed(bank->context.leveldetect1, | |
1176 | bank->base + bank->regs->leveldetect1); | |
1177 | writel_relaxed(bank->context.risingdetect, | |
1178 | bank->base + bank->regs->risingdetect); | |
1179 | writel_relaxed(bank->context.fallingdetect, | |
1180 | bank->base + bank->regs->fallingdetect); | |
1181 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1182 | writel_relaxed(bank->context.dataout, | |
1183 | bank->base + bank->regs->set_dataout); | |
1184 | else | |
1185 | writel_relaxed(bank->context.dataout, | |
1186 | bank->base + bank->regs->dataout); | |
1187 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); | |
9f7065da | 1188 | |
7c68571f AB |
1189 | if (bank->dbck_enable_mask) { |
1190 | writel_relaxed(bank->context.debounce, bank->base + | |
1191 | bank->regs->debounce); | |
1192 | writel_relaxed(bank->context.debounce_en, | |
1193 | bank->base + bank->regs->debounce_en); | |
b764a586 TL |
1194 | } |
1195 | ||
7c68571f AB |
1196 | writel_relaxed(bank->context.irqenable1, |
1197 | bank->base + bank->regs->irqenable); | |
1198 | writel_relaxed(bank->context.irqenable2, | |
1199 | bank->base + bank->regs->irqenable2); | |
cac089f9 TL |
1200 | } |
1201 | ||
b764a586 | 1202 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1203 | { |
b764a586 | 1204 | struct device *dev = bank->chip.parent; |
21e2118f TL |
1205 | void __iomem *base = bank->base; |
1206 | u32 nowake; | |
1207 | ||
1208 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1209 | |
b3c64bc3 KH |
1210 | if (!bank->enabled_non_wakeup_gpios) |
1211 | goto update_gpio_context_count; | |
1212 | ||
b764a586 | 1213 | if (!may_lose_context) |
41d87cbd | 1214 | goto update_gpio_context_count; |
b764a586 | 1215 | |
2dc983c5 | 1216 | /* |
21e2118f | 1217 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1218 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1219 | * generated. See OMAP2420 Errata item 1.101. | |
1220 | */ | |
21e2118f TL |
1221 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1222 | nowake = bank->enabled_non_wakeup_gpios; | |
1223 | omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake); | |
1224 | omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake); | |
1225 | } | |
3f1686a9 | 1226 | |
41d87cbd | 1227 | update_gpio_context_count: |
2dc983c5 TKD |
1228 | if (bank->get_context_loss_count) |
1229 | bank->context_loss_count = | |
7b1e5dc8 | 1230 | bank->get_context_loss_count(dev); |
60a3437d | 1231 | |
a0e827c6 | 1232 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1233 | } |
1234 | ||
b764a586 | 1235 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1236 | { |
b764a586 | 1237 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1238 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1239 | int c; |
8865b9b6 | 1240 | |
352a2d5b JH |
1241 | /* |
1242 | * On the first resume during the probe, the context has not | |
1243 | * been initialised and so initialise it now. Also initialise | |
1244 | * the context loss count. | |
1245 | */ | |
1246 | if (bank->loses_context && !bank->context_valid) { | |
1247 | omap_gpio_init_context(bank); | |
1248 | ||
1249 | if (bank->get_context_loss_count) | |
1250 | bank->context_loss_count = | |
7b1e5dc8 | 1251 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1252 | } |
1253 | ||
a0e827c6 | 1254 | omap_gpio_dbck_enable(bank); |
68942edb | 1255 | |
a2797bea JH |
1256 | if (bank->loses_context) { |
1257 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1258 | omap_gpio_restore_context(bank); |
1259 | } else { | |
7b1e5dc8 | 1260 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1261 | if (c != bank->context_loss_count) { |
1262 | omap_gpio_restore_context(bank); | |
1263 | } else { | |
b764a586 | 1264 | return; |
a2797bea | 1265 | } |
60a3437d | 1266 | } |
21e2118f TL |
1267 | } else { |
1268 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1269 | writel_relaxed(bank->context.fallingdetect, | |
1270 | bank->base + bank->regs->fallingdetect); | |
1271 | writel_relaxed(bank->context.risingdetect, | |
1272 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1273 | } |
43ffcd9a | 1274 | |
661553b9 | 1275 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1276 | |
2dc983c5 TKD |
1277 | /* |
1278 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1279 | * state. If so, generate an IRQ by software. This is | |
1280 | * horribly racy, but it's the best we can do to work around | |
1281 | * this silicon bug. | |
1282 | */ | |
1283 | l ^= bank->saved_datain; | |
1284 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1285 | |
2dc983c5 TKD |
1286 | /* |
1287 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1288 | * configured with falling edge only; and vice versa. | |
1289 | */ | |
c6f31c9e | 1290 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1291 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1292 | |
c6f31c9e | 1293 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1294 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1295 | |
2dc983c5 | 1296 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1297 | gen = l & (~(bank->context.fallingdetect) & |
1298 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1299 | /* Consider all GPIO IRQs needed to be updated */ |
1300 | gen |= gen0 | gen1; | |
82dbb9d3 | 1301 | |
2dc983c5 TKD |
1302 | if (gen) { |
1303 | u32 old0, old1; | |
82dbb9d3 | 1304 | |
661553b9 VK |
1305 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1306 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1307 | |
4e962e89 | 1308 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1309 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1310 | bank->regs->leveldetect0); |
661553b9 | 1311 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1312 | bank->regs->leveldetect1); |
2dc983c5 | 1313 | } |
9ea14d8c | 1314 | |
4e962e89 | 1315 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1316 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1317 | bank->regs->leveldetect0); |
661553b9 | 1318 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1319 | bank->regs->leveldetect1); |
3ac4fa99 | 1320 | } |
661553b9 VK |
1321 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1322 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1323 | } |
2dc983c5 | 1324 | } |
2dc983c5 | 1325 | |
7c68571f AB |
1326 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, |
1327 | unsigned long cmd, void *v) | |
352a2d5b | 1328 | { |
7c68571f AB |
1329 | struct gpio_bank *bank; |
1330 | unsigned long flags; | |
352a2d5b | 1331 | |
7c68571f | 1332 | bank = container_of(nb, struct gpio_bank, nb); |
352a2d5b | 1333 | |
7c68571f AB |
1334 | raw_spin_lock_irqsave(&bank->lock, flags); |
1335 | switch (cmd) { | |
1336 | case CPU_CLUSTER_PM_ENTER: | |
1337 | if (bank->is_suspended) | |
1338 | break; | |
1339 | omap_gpio_idle(bank, true); | |
1340 | break; | |
1341 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1342 | case CPU_CLUSTER_PM_EXIT: | |
1343 | if (bank->is_suspended) | |
1344 | break; | |
1345 | omap_gpio_unidle(bank); | |
1346 | break; | |
1347 | } | |
1348 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
352a2d5b | 1349 | |
7c68571f | 1350 | return NOTIFY_OK; |
b764a586 TL |
1351 | } |
1352 | ||
384ebe1c BC |
1353 | static struct omap_gpio_reg_offs omap2_gpio_regs = { |
1354 | .revision = OMAP24XX_GPIO_REVISION, | |
1355 | .direction = OMAP24XX_GPIO_OE, | |
1356 | .datain = OMAP24XX_GPIO_DATAIN, | |
1357 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1358 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1359 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1360 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1361 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1362 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1363 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1364 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1365 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1366 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1367 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1368 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1369 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1370 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1371 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1372 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1373 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1374 | }; | |
1375 | ||
1376 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1377 | .revision = OMAP4_GPIO_REVISION, | |
1378 | .direction = OMAP4_GPIO_OE, | |
1379 | .datain = OMAP4_GPIO_DATAIN, | |
1380 | .dataout = OMAP4_GPIO_DATAOUT, | |
1381 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1382 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1383 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1384 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
64ea3e90 RK |
1385 | .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, |
1386 | .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, | |
384ebe1c BC |
1387 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, |
1388 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1389 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1390 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1391 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1392 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1393 | .ctrl = OMAP4_GPIO_CTRL, | |
1394 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1395 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1396 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1397 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1398 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1399 | }; | |
1400 | ||
e9a65bb6 | 1401 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1402 | .regs = &omap2_gpio_regs, |
1403 | .bank_width = 32, | |
1404 | .dbck_flag = false, | |
1405 | }; | |
1406 | ||
e9a65bb6 | 1407 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1408 | .regs = &omap2_gpio_regs, |
1409 | .bank_width = 32, | |
1410 | .dbck_flag = true, | |
1411 | }; | |
1412 | ||
e9a65bb6 | 1413 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1414 | .regs = &omap4_gpio_regs, |
1415 | .bank_width = 32, | |
1416 | .dbck_flag = true, | |
1417 | }; | |
1418 | ||
1419 | static const struct of_device_id omap_gpio_match[] = { | |
1420 | { | |
1421 | .compatible = "ti,omap4-gpio", | |
1422 | .data = &omap4_pdata, | |
1423 | }, | |
1424 | { | |
1425 | .compatible = "ti,omap3-gpio", | |
1426 | .data = &omap3_pdata, | |
1427 | }, | |
1428 | { | |
1429 | .compatible = "ti,omap2-gpio", | |
1430 | .data = &omap2_pdata, | |
1431 | }, | |
1432 | { }, | |
1433 | }; | |
1434 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
7c68571f AB |
1435 | |
1436 | static int omap_gpio_probe(struct platform_device *pdev) | |
1437 | { | |
1438 | struct device *dev = &pdev->dev; | |
1439 | struct device_node *node = dev->of_node; | |
1440 | const struct of_device_id *match; | |
1441 | const struct omap_gpio_platform_data *pdata; | |
7c68571f AB |
1442 | struct gpio_bank *bank; |
1443 | struct irq_chip *irqc; | |
1444 | int ret; | |
1445 | ||
1446 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); | |
1447 | ||
1448 | pdata = match ? match->data : dev_get_platdata(dev); | |
1449 | if (!pdata) | |
1450 | return -EINVAL; | |
1451 | ||
1452 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
1453 | if (!bank) | |
1454 | return -ENOMEM; | |
1455 | ||
1456 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); | |
1457 | if (!irqc) | |
1458 | return -ENOMEM; | |
1459 | ||
1460 | irqc->irq_startup = omap_gpio_irq_startup, | |
1461 | irqc->irq_shutdown = omap_gpio_irq_shutdown, | |
693de831 | 1462 | irqc->irq_ack = dummy_irq_chip.irq_ack, |
7c68571f AB |
1463 | irqc->irq_mask = omap_gpio_mask_irq, |
1464 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1465 | irqc->irq_set_type = omap_gpio_irq_type, | |
1466 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1467 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, | |
1468 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
1469 | irqc->name = dev_name(&pdev->dev); | |
1470 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1471 | irqc->parent_device = dev; | |
1472 | ||
1473 | bank->irq = platform_get_irq(pdev, 0); | |
1474 | if (bank->irq <= 0) { | |
1475 | if (!bank->irq) | |
1476 | bank->irq = -ENXIO; | |
1477 | if (bank->irq != -EPROBE_DEFER) | |
1478 | dev_err(dev, | |
1479 | "can't get irq resource ret=%d\n", bank->irq); | |
1480 | return bank->irq; | |
1481 | } | |
1482 | ||
1483 | bank->chip.parent = dev; | |
1484 | bank->chip.owner = THIS_MODULE; | |
1485 | bank->dbck_flag = pdata->dbck_flag; | |
7c68571f AB |
1486 | bank->stride = pdata->bank_stride; |
1487 | bank->width = pdata->bank_width; | |
1488 | bank->is_mpuio = pdata->is_mpuio; | |
1489 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; | |
1490 | bank->regs = pdata->regs; | |
1491 | #ifdef CONFIG_OF_GPIO | |
1492 | bank->chip.of_node = of_node_get(node); | |
384ebe1c BC |
1493 | #endif |
1494 | ||
7c68571f AB |
1495 | if (node) { |
1496 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1497 | bank->loses_context = true; | |
1498 | } else { | |
1499 | bank->loses_context = pdata->loses_context; | |
1500 | ||
1501 | if (bank->loses_context) | |
1502 | bank->get_context_loss_count = | |
1503 | pdata->get_context_loss_count; | |
1504 | } | |
1505 | ||
8ba70595 | 1506 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
7c68571f | 1507 | bank->set_dataout = omap_set_gpio_dataout_reg; |
8ba70595 | 1508 | else |
7c68571f | 1509 | bank->set_dataout = omap_set_gpio_dataout_mask; |
7c68571f | 1510 | |
7c68571f AB |
1511 | raw_spin_lock_init(&bank->lock); |
1512 | raw_spin_lock_init(&bank->wa_lock); | |
1513 | ||
1514 | /* Static mapping, never released */ | |
58f57f86 | 1515 | bank->base = devm_platform_ioremap_resource(pdev, 0); |
7c68571f AB |
1516 | if (IS_ERR(bank->base)) { |
1517 | return PTR_ERR(bank->base); | |
1518 | } | |
1519 | ||
1520 | if (bank->dbck_flag) { | |
1521 | bank->dbck = devm_clk_get(dev, "dbclk"); | |
1522 | if (IS_ERR(bank->dbck)) { | |
1523 | dev_err(dev, | |
1524 | "Could not get gpio dbck. Disable debounce\n"); | |
1525 | bank->dbck_flag = false; | |
1526 | } else { | |
1527 | clk_prepare(bank->dbck); | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | platform_set_drvdata(pdev, bank); | |
1532 | ||
1533 | pm_runtime_enable(dev); | |
1534 | pm_runtime_get_sync(dev); | |
1535 | ||
1536 | if (bank->is_mpuio) | |
1537 | omap_mpuio_init(bank); | |
1538 | ||
1539 | omap_gpio_mod_init(bank); | |
1540 | ||
1541 | ret = omap_gpio_chip_init(bank, irqc); | |
1542 | if (ret) { | |
1543 | pm_runtime_put_sync(dev); | |
1544 | pm_runtime_disable(dev); | |
1545 | if (bank->dbck_flag) | |
1546 | clk_unprepare(bank->dbck); | |
1547 | return ret; | |
1548 | } | |
1549 | ||
1550 | omap_gpio_show_rev(bank); | |
1551 | ||
e6818d29 RK |
1552 | bank->nb.notifier_call = gpio_omap_cpu_notifier; |
1553 | cpu_pm_register_notifier(&bank->nb); | |
7c68571f AB |
1554 | |
1555 | pm_runtime_put(dev); | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | static int omap_gpio_remove(struct platform_device *pdev) | |
1561 | { | |
1562 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1563 | ||
e6818d29 | 1564 | cpu_pm_unregister_notifier(&bank->nb); |
7c68571f AB |
1565 | gpiochip_remove(&bank->chip); |
1566 | pm_runtime_disable(&pdev->dev); | |
1567 | if (bank->dbck_flag) | |
1568 | clk_unprepare(bank->dbck); | |
1569 | ||
1570 | return 0; | |
1571 | } | |
1572 | ||
1573 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) | |
1574 | { | |
1575 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1576 | unsigned long flags; | |
7c68571f AB |
1577 | |
1578 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1579 | omap_gpio_idle(bank, true); |
1580 | bank->is_suspended = true; | |
7c68571f AB |
1581 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1582 | ||
044e499a | 1583 | return 0; |
7c68571f AB |
1584 | } |
1585 | ||
1586 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1587 | { | |
1588 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1589 | unsigned long flags; | |
7c68571f AB |
1590 | |
1591 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1592 | omap_gpio_unidle(bank); |
1593 | bank->is_suspended = false; | |
7c68571f AB |
1594 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1595 | ||
044e499a | 1596 | return 0; |
7c68571f AB |
1597 | } |
1598 | ||
1599 | static const struct dev_pm_ops gpio_pm_ops = { | |
1600 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, | |
1601 | NULL) | |
1602 | }; | |
1603 | ||
77640aab VC |
1604 | static struct platform_driver omap_gpio_driver = { |
1605 | .probe = omap_gpio_probe, | |
cac089f9 | 1606 | .remove = omap_gpio_remove, |
77640aab VC |
1607 | .driver = { |
1608 | .name = "omap_gpio", | |
55b93c32 | 1609 | .pm = &gpio_pm_ops, |
7c68571f | 1610 | .of_match_table = omap_gpio_match, |
77640aab VC |
1611 | }, |
1612 | }; | |
1613 | ||
5e1c5ff4 | 1614 | /* |
77640aab VC |
1615 | * gpio driver register needs to be done before |
1616 | * machine_init functions access gpio APIs. | |
1617 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1618 | */ |
77640aab | 1619 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1620 | { |
77640aab | 1621 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1622 | } |
77640aab | 1623 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1624 | |
1625 | static void __exit omap_gpio_exit(void) | |
1626 | { | |
1627 | platform_driver_unregister(&omap_gpio_driver); | |
1628 | } | |
1629 | module_exit(omap_gpio_exit); | |
1630 | ||
1631 | MODULE_DESCRIPTION("omap gpio driver"); | |
1632 | MODULE_ALIAS("platform:gpio-omap"); | |
1633 | MODULE_LICENSE("GPL v2"); |