Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
b764a586 | 22 | #include <linux/cpu_pm.h> |
96751fcb | 23 | #include <linux/device.h> |
77640aab | 24 | #include <linux/pm_runtime.h> |
55b93c32 | 25 | #include <linux/pm.h> |
384ebe1c BC |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
b7351b07 | 28 | #include <linux/gpio/driver.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
6d62e216 C |
34 | struct gpio_regs { |
35 | u32 irqenable1; | |
36 | u32 irqenable2; | |
37 | u32 wake_en; | |
38 | u32 ctrl; | |
39 | u32 oe; | |
40 | u32 leveldetect0; | |
41 | u32 leveldetect1; | |
42 | u32 risingdetect; | |
43 | u32 fallingdetect; | |
44 | u32 dataout; | |
ae547354 NM |
45 | u32 debounce; |
46 | u32 debounce_en; | |
6d62e216 C |
47 | }; |
48 | ||
5e1c5ff4 | 49 | struct gpio_bank { |
92105bb7 | 50 | void __iomem *base; |
30cefeac | 51 | int irq; |
3ac4fa99 JY |
52 | u32 non_wakeup_gpios; |
53 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 54 | struct gpio_regs context; |
3ac4fa99 | 55 | u32 saved_datain; |
b144ff6f | 56 | u32 level_mask; |
4318f36b | 57 | u32 toggle_mask; |
4dbada2b | 58 | raw_spinlock_t lock; |
450fa54c | 59 | raw_spinlock_t wa_lock; |
52e31344 | 60 | struct gpio_chip chip; |
89db9482 | 61 | struct clk *dbck; |
b764a586 TL |
62 | struct notifier_block nb; |
63 | unsigned int is_suspended:1; | |
058af1ea | 64 | u32 mod_usage; |
fa365e4d | 65 | u32 irq_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
72f83af9 | 67 | bool dbck_enabled; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
fa87931a | 75 | |
04ebcbd8 | 76 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
442af140 JK |
77 | void (*set_dataout_multiple)(struct gpio_bank *bank, |
78 | unsigned long *mask, unsigned long *bits); | |
60a3437d | 79 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
80 | |
81 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
82 | }; |
83 | ||
c8eef65a | 84 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 85 | |
fa365e4d | 86 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 87 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 88 | |
3d009c8c TL |
89 | static void omap_gpio_unmask_irq(struct irq_data *d); |
90 | ||
a0e827c6 | 91 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 92 | { |
fb655f57 | 93 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 94 | return gpiochip_get_data(chip); |
25db711d BC |
95 | } |
96 | ||
a0e827c6 JMC |
97 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
98 | int is_input) | |
5e1c5ff4 | 99 | { |
92105bb7 | 100 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
101 | u32 l; |
102 | ||
fa87931a | 103 | reg += bank->regs->direction; |
661553b9 | 104 | l = readl_relaxed(reg); |
5e1c5ff4 | 105 | if (is_input) |
b1e9fec2 | 106 | l |= BIT(gpio); |
5e1c5ff4 | 107 | else |
b1e9fec2 | 108 | l &= ~(BIT(gpio)); |
661553b9 | 109 | writel_relaxed(l, reg); |
41d87cbd | 110 | bank->context.oe = l; |
5e1c5ff4 TL |
111 | } |
112 | ||
fa87931a KH |
113 | |
114 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 115 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 116 | int enable) |
5e1c5ff4 | 117 | { |
92105bb7 | 118 | void __iomem *reg = bank->base; |
04ebcbd8 | 119 | u32 l = BIT(offset); |
5e1c5ff4 | 120 | |
2c836f7e | 121 | if (enable) { |
fa87931a | 122 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
123 | bank->context.dataout |= l; |
124 | } else { | |
fa87931a | 125 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
126 | bank->context.dataout &= ~l; |
127 | } | |
5e1c5ff4 | 128 | |
661553b9 | 129 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
130 | } |
131 | ||
fa87931a | 132 | /* set data out value using mask register */ |
04ebcbd8 | 133 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 134 | int enable) |
5e1c5ff4 | 135 | { |
fa87931a | 136 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 137 | u32 gpio_bit = BIT(offset); |
fa87931a | 138 | u32 l; |
5e1c5ff4 | 139 | |
661553b9 | 140 | l = readl_relaxed(reg); |
fa87931a KH |
141 | if (enable) |
142 | l |= gpio_bit; | |
143 | else | |
144 | l &= ~gpio_bit; | |
661553b9 | 145 | writel_relaxed(l, reg); |
41d87cbd | 146 | bank->context.dataout = l; |
5e1c5ff4 TL |
147 | } |
148 | ||
442af140 JK |
149 | /* set multiple data out values using dedicate set/clear register */ |
150 | static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, | |
151 | unsigned long *mask, | |
152 | unsigned long *bits) | |
153 | { | |
154 | void __iomem *reg = bank->base; | |
155 | u32 l; | |
156 | ||
157 | l = *bits & *mask; | |
158 | writel_relaxed(l, reg + bank->regs->set_dataout); | |
159 | bank->context.dataout |= l; | |
160 | ||
161 | l = ~*bits & *mask; | |
162 | writel_relaxed(l, reg + bank->regs->clr_dataout); | |
163 | bank->context.dataout &= ~l; | |
164 | } | |
165 | ||
166 | /* set multiple data out values using mask register */ | |
167 | static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, | |
168 | unsigned long *mask, | |
169 | unsigned long *bits) | |
170 | { | |
171 | void __iomem *reg = bank->base + bank->regs->dataout; | |
172 | u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); | |
173 | ||
174 | writel_relaxed(l, reg); | |
175 | bank->context.dataout = l; | |
176 | } | |
177 | ||
a0e827c6 | 178 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 179 | { |
661553b9 | 180 | int l = readl_relaxed(base + reg); |
ece9528e | 181 | |
862ff640 | 182 | if (set) |
ece9528e KH |
183 | l |= mask; |
184 | else | |
185 | l &= ~mask; | |
186 | ||
661553b9 | 187 | writel_relaxed(l, base + reg); |
ece9528e | 188 | } |
92105bb7 | 189 | |
a0e827c6 | 190 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
191 | { |
192 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 193 | clk_enable(bank->dbck); |
72f83af9 | 194 | bank->dbck_enabled = true; |
9e303f22 | 195 | |
661553b9 | 196 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 197 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
198 | } |
199 | } | |
200 | ||
a0e827c6 | 201 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
202 | { |
203 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
204 | /* |
205 | * Disable debounce before cutting it's clock. If debounce is | |
206 | * enabled but the clock is not, GPIO module seems to be unable | |
207 | * to detect events and generate interrupts at least on OMAP3. | |
208 | */ | |
661553b9 | 209 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 210 | |
5d9452e7 | 211 | clk_disable(bank->dbck); |
72f83af9 TKD |
212 | bank->dbck_enabled = false; |
213 | } | |
214 | } | |
215 | ||
168ef3d9 | 216 | /** |
a0e827c6 | 217 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 218 | * @bank: the gpio bank we're acting upon |
4a58d229 | 219 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
220 | * @debounce: debounce time to use |
221 | * | |
e85ec6c3 GS |
222 | * OMAP's debounce time is in 31us steps |
223 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
224 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
225 | * |
226 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 227 | */ |
83977443 DR |
228 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
229 | unsigned debounce) | |
168ef3d9 | 230 | { |
9942da0e | 231 | void __iomem *reg; |
168ef3d9 FB |
232 | u32 val; |
233 | u32 l; | |
e85ec6c3 | 234 | bool enable = !!debounce; |
168ef3d9 | 235 | |
77640aab | 236 | if (!bank->dbck_flag) |
83977443 | 237 | return -ENOTSUPP; |
77640aab | 238 | |
e85ec6c3 GS |
239 | if (enable) { |
240 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
241 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
242 | return -EINVAL; | |
e85ec6c3 | 243 | } |
168ef3d9 | 244 | |
4a58d229 | 245 | l = BIT(offset); |
168ef3d9 | 246 | |
5d9452e7 | 247 | clk_enable(bank->dbck); |
9942da0e | 248 | reg = bank->base + bank->regs->debounce; |
661553b9 | 249 | writel_relaxed(debounce, reg); |
168ef3d9 | 250 | |
9942da0e | 251 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 252 | val = readl_relaxed(reg); |
168ef3d9 | 253 | |
e85ec6c3 | 254 | if (enable) |
168ef3d9 | 255 | val |= l; |
6fd9c421 | 256 | else |
168ef3d9 | 257 | val &= ~l; |
f7ec0b0b | 258 | bank->dbck_enable_mask = val; |
168ef3d9 | 259 | |
661553b9 | 260 | writel_relaxed(val, reg); |
5d9452e7 | 261 | clk_disable(bank->dbck); |
6fd9c421 TKD |
262 | /* |
263 | * Enable debounce clock per module. | |
264 | * This call is mandatory because in omap_gpio_request() when | |
265 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
266 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
267 | * used within _gpio_dbck_enable() is still not initialized at | |
268 | * that point. Therefore we have to enable dbck here. | |
269 | */ | |
a0e827c6 | 270 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
271 | if (bank->dbck_enable_mask) { |
272 | bank->context.debounce = debounce; | |
273 | bank->context.debounce_en = val; | |
274 | } | |
83977443 DR |
275 | |
276 | return 0; | |
168ef3d9 FB |
277 | } |
278 | ||
c9c55d92 | 279 | /** |
a0e827c6 | 280 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 281 | * @bank: the gpio bank we're acting upon |
4a58d229 | 282 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
283 | * |
284 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
285 | * this is the only gpio in this bank using debounce, then clear the debounce | |
286 | * time too. The debounce clock will also be disabled when calling this function | |
287 | * if this is the only gpio in the bank using debounce. | |
288 | */ | |
4a58d229 | 289 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 290 | { |
4a58d229 | 291 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
292 | |
293 | if (!bank->dbck_flag) | |
294 | return; | |
295 | ||
296 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
297 | return; | |
298 | ||
299 | bank->dbck_enable_mask &= ~gpio_bit; | |
300 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 301 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
302 | bank->base + bank->regs->debounce_en); |
303 | ||
304 | if (!bank->dbck_enable_mask) { | |
305 | bank->context.debounce = 0; | |
661553b9 | 306 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 307 | bank->regs->debounce); |
5d9452e7 | 308 | clk_disable(bank->dbck); |
c9c55d92 JH |
309 | bank->dbck_enabled = false; |
310 | } | |
311 | } | |
312 | ||
da38ef3e TL |
313 | /* |
314 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
315 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
316 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
317 | * are capable waking up the system from off mode. | |
318 | */ | |
319 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
320 | { | |
321 | u32 no_wake = bank->non_wakeup_gpios; | |
322 | ||
323 | if (no_wake) | |
324 | return !!(~no_wake & gpio_mask); | |
325 | ||
326 | return false; | |
327 | } | |
328 | ||
a0e827c6 | 329 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 330 | unsigned trigger) |
5e1c5ff4 | 331 | { |
3ac4fa99 | 332 | void __iomem *base = bank->base; |
b1e9fec2 | 333 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 334 | |
a0e827c6 JMC |
335 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
336 | trigger & IRQ_TYPE_LEVEL_LOW); | |
337 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
338 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
e6818d29 RK |
339 | |
340 | /* | |
341 | * We need the edge detection enabled for to allow the GPIO block | |
342 | * to be woken from idle state. Set the appropriate edge detection | |
343 | * in addition to the level detection. | |
344 | */ | |
a0e827c6 | 345 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, |
e6818d29 | 346 | trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); |
a0e827c6 | 347 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, |
e6818d29 | 348 | trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); |
5e571f38 | 349 | |
41d87cbd | 350 | bank->context.leveldetect0 = |
661553b9 | 351 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 352 | bank->context.leveldetect1 = |
661553b9 | 353 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 354 | bank->context.risingdetect = |
661553b9 | 355 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 356 | bank->context.fallingdetect = |
661553b9 | 357 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
358 | |
359 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
00ded24c TL |
360 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
361 | bank->context.wake_en = | |
362 | readl_relaxed(bank->base + bank->regs->wkup_en); | |
41d87cbd | 363 | } |
5e571f38 | 364 | |
55b220ca | 365 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 366 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
367 | /* |
368 | * Log the edge gpio and manually trigger the IRQ | |
369 | * after resume if the input level changes | |
370 | * to avoid irq lost during PER RET/OFF mode | |
371 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
372 | */ | |
373 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
374 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
375 | else | |
376 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
377 | } | |
5eb3bb9c | 378 | |
9ea14d8c | 379 | bank->level_mask = |
661553b9 VK |
380 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
381 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
382 | } |
383 | ||
9198bcd3 | 384 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
385 | /* |
386 | * This only applies to chips that can't do both rising and falling edge | |
387 | * detection at once. For all other chips, this function is a noop. | |
388 | */ | |
a0e827c6 | 389 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
390 | { |
391 | void __iomem *reg = bank->base; | |
392 | u32 l = 0; | |
393 | ||
5e571f38 | 394 | if (!bank->regs->irqctrl) |
4318f36b | 395 | return; |
5e571f38 TKD |
396 | |
397 | reg += bank->regs->irqctrl; | |
4318f36b | 398 | |
661553b9 | 399 | l = readl_relaxed(reg); |
4318f36b | 400 | if ((l >> gpio) & 1) |
b1e9fec2 | 401 | l &= ~(BIT(gpio)); |
4318f36b | 402 | else |
b1e9fec2 | 403 | l |= BIT(gpio); |
4318f36b | 404 | |
661553b9 | 405 | writel_relaxed(l, reg); |
4318f36b | 406 | } |
5e571f38 | 407 | #else |
a0e827c6 | 408 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 409 | #endif |
4318f36b | 410 | |
a0e827c6 JMC |
411 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
412 | unsigned trigger) | |
92105bb7 TL |
413 | { |
414 | void __iomem *reg = bank->base; | |
5e571f38 | 415 | void __iomem *base = bank->base; |
92105bb7 | 416 | u32 l = 0; |
5e1c5ff4 | 417 | |
5e571f38 | 418 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 419 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
420 | } else if (bank->regs->irqctrl) { |
421 | reg += bank->regs->irqctrl; | |
422 | ||
661553b9 | 423 | l = readl_relaxed(reg); |
29501577 | 424 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 425 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 426 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 427 | l |= BIT(gpio); |
6cab4860 | 428 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 429 | l &= ~(BIT(gpio)); |
92105bb7 | 430 | else |
5e571f38 TKD |
431 | return -EINVAL; |
432 | ||
661553b9 | 433 | writel_relaxed(l, reg); |
5e571f38 | 434 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 435 | if (gpio & 0x08) |
5e571f38 | 436 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 437 | else |
5e571f38 TKD |
438 | reg += bank->regs->edgectrl1; |
439 | ||
5e1c5ff4 | 440 | gpio &= 0x07; |
661553b9 | 441 | l = readl_relaxed(reg); |
5e1c5ff4 | 442 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 443 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 444 | l |= 2 << (gpio << 1); |
6cab4860 | 445 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 446 | l |= BIT(gpio << 1); |
5e571f38 TKD |
447 | |
448 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 449 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 450 | bank->context.wake_en = |
661553b9 VK |
451 | readl_relaxed(bank->base + bank->regs->wkup_en); |
452 | writel_relaxed(l, reg); | |
5e1c5ff4 | 453 | } |
92105bb7 | 454 | return 0; |
5e1c5ff4 TL |
455 | } |
456 | ||
a0e827c6 | 457 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
458 | { |
459 | if (bank->regs->pinctrl) { | |
460 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
461 | ||
462 | /* Claim the pin for MPU */ | |
b1e9fec2 | 463 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
464 | } |
465 | ||
466 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
467 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
468 | u32 ctrl; | |
469 | ||
661553b9 | 470 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
471 | /* Module is enabled, clocks are not gated */ |
472 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 473 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
474 | bank->context.ctrl = ctrl; |
475 | } | |
476 | } | |
477 | ||
a0e827c6 | 478 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
479 | { |
480 | void __iomem *base = bank->base; | |
481 | ||
482 | if (bank->regs->wkup_en && | |
483 | !LINE_USED(bank->mod_usage, offset) && | |
484 | !LINE_USED(bank->irq_usage, offset)) { | |
485 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 486 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 487 | bank->context.wake_en = |
661553b9 | 488 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
489 | } |
490 | ||
491 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
492 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
493 | u32 ctrl; | |
494 | ||
661553b9 | 495 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
496 | /* Module is disabled, clocks are gated */ |
497 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 498 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
499 | bank->context.ctrl = ctrl; |
500 | } | |
501 | } | |
502 | ||
b2b20045 | 503 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
504 | { |
505 | void __iomem *reg = bank->base + bank->regs->direction; | |
506 | ||
b2b20045 | 507 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
508 | } |
509 | ||
37e14ecf | 510 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
511 | { |
512 | if (!LINE_USED(bank->mod_usage, offset)) { | |
513 | omap_enable_gpio_module(bank, offset); | |
514 | omap_set_gpio_direction(bank, offset, 1); | |
515 | } | |
37e14ecf | 516 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
517 | } |
518 | ||
a0e827c6 | 519 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 520 | { |
a0e827c6 | 521 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 522 | int retval; |
a6472533 | 523 | unsigned long flags; |
ea5fbe8d | 524 | unsigned offset = d->hwirq; |
92105bb7 | 525 | |
e5c56ed3 | 526 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 527 | return -EINVAL; |
e5c56ed3 | 528 | |
9ea14d8c TKD |
529 | if (!bank->regs->leveldetect0 && |
530 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
531 | return -EINVAL; |
532 | ||
4dbada2b | 533 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 534 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 535 | if (retval) { |
627c89b4 | 536 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 537 | goto error; |
977bd8a9 | 538 | } |
37e14ecf | 539 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 540 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 541 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
542 | retval = -EINVAL; |
543 | goto error; | |
fac7fa16 | 544 | } |
4dbada2b | 545 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
546 | |
547 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 548 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 549 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
550 | /* |
551 | * Edge IRQs are already cleared/acked in irq_handler and | |
552 | * not need to be masked, as result handle_edge_irq() | |
553 | * logic is excessed here and may cause lose of interrupts. | |
554 | * So just use handle_simple_irq. | |
555 | */ | |
556 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 557 | |
1562e461 GS |
558 | return 0; |
559 | ||
560 | error: | |
92105bb7 | 561 | return retval; |
5e1c5ff4 TL |
562 | } |
563 | ||
a0e827c6 | 564 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 565 | { |
92105bb7 | 566 | void __iomem *reg = bank->base; |
5e1c5ff4 | 567 | |
eef4bec7 | 568 | reg += bank->regs->irqstatus; |
661553b9 | 569 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
570 | |
571 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
572 | if (bank->regs->irqstatus2) { |
573 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 574 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 575 | } |
bedfd154 RQ |
576 | |
577 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 578 | readl_relaxed(reg); |
5e1c5ff4 TL |
579 | } |
580 | ||
9943f261 GS |
581 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
582 | unsigned offset) | |
5e1c5ff4 | 583 | { |
9943f261 | 584 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
585 | } |
586 | ||
a0e827c6 | 587 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
588 | { |
589 | void __iomem *reg = bank->base; | |
99c47707 | 590 | u32 l; |
b1e9fec2 | 591 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 592 | |
28f3b5a0 | 593 | reg += bank->regs->irqenable; |
661553b9 | 594 | l = readl_relaxed(reg); |
28f3b5a0 | 595 | if (bank->regs->irqenable_inv) |
99c47707 ID |
596 | l = ~l; |
597 | l &= mask; | |
598 | return l; | |
ea6dedd7 ID |
599 | } |
600 | ||
a0e827c6 | 601 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 602 | { |
92105bb7 | 603 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
604 | u32 l; |
605 | ||
28f3b5a0 KH |
606 | if (bank->regs->set_irqenable) { |
607 | reg += bank->regs->set_irqenable; | |
608 | l = gpio_mask; | |
2a900eb7 | 609 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
610 | } else { |
611 | reg += bank->regs->irqenable; | |
661553b9 | 612 | l = readl_relaxed(reg); |
28f3b5a0 KH |
613 | if (bank->regs->irqenable_inv) |
614 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
615 | else |
616 | l |= gpio_mask; | |
2a900eb7 | 617 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
618 | } |
619 | ||
661553b9 | 620 | writel_relaxed(l, reg); |
28f3b5a0 KH |
621 | } |
622 | ||
a0e827c6 | 623 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
624 | { |
625 | void __iomem *reg = bank->base; | |
626 | u32 l; | |
627 | ||
628 | if (bank->regs->clr_irqenable) { | |
629 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 630 | l = gpio_mask; |
2a900eb7 | 631 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
632 | } else { |
633 | reg += bank->regs->irqenable; | |
661553b9 | 634 | l = readl_relaxed(reg); |
28f3b5a0 | 635 | if (bank->regs->irqenable_inv) |
56739a69 | 636 | l |= gpio_mask; |
92105bb7 | 637 | else |
28f3b5a0 | 638 | l &= ~gpio_mask; |
2a900eb7 | 639 | bank->context.irqenable1 = l; |
5e1c5ff4 | 640 | } |
28f3b5a0 | 641 | |
661553b9 | 642 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
643 | } |
644 | ||
9943f261 GS |
645 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
646 | unsigned offset, int enable) | |
5e1c5ff4 | 647 | { |
8276536c | 648 | if (enable) |
9943f261 | 649 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 650 | else |
9943f261 | 651 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
652 | } |
653 | ||
92105bb7 | 654 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 655 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 656 | { |
a0e827c6 | 657 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 658 | |
0c0451e7 | 659 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
660 | } |
661 | ||
5e1c5ff4 TL |
662 | /* |
663 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
664 | * avoid missing GPIO interrupts for other lines in the bank. | |
665 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
666 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
667 | * If we wait to unmask individual GPIO lines in the bank after the | |
668 | * line's interrupt handler has been run, we may miss some nested | |
669 | * interrupts. | |
670 | */ | |
450fa54c | 671 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 672 | { |
92105bb7 | 673 | void __iomem *isr_reg = NULL; |
395373c7 | 674 | u32 enabled, isr, edge; |
3513cdec | 675 | unsigned int bit; |
450fa54c GS |
676 | struct gpio_bank *bank = gpiobank; |
677 | unsigned long wa_lock_flags; | |
235f1eb1 | 678 | unsigned long lock_flags; |
5e1c5ff4 | 679 | |
eef4bec7 | 680 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
681 | if (WARN_ON(!isr_reg)) |
682 | goto exit; | |
683 | ||
5284521a TL |
684 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
685 | "gpio irq%i while runtime suspended?\n", irq)) | |
686 | return IRQ_NONE; | |
450fa54c | 687 | |
e83507b7 | 688 | while (1) { |
235f1eb1 GS |
689 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
690 | ||
a0e827c6 | 691 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 692 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 693 | |
395373c7 RK |
694 | /* |
695 | * Clear edge sensitive interrupts before calling handler(s) | |
696 | * so subsequent edge transitions are not missed while the | |
697 | * handlers are running. | |
698 | */ | |
699 | edge = isr & ~bank->level_mask; | |
700 | if (edge) | |
701 | omap_clear_gpio_irqbank(bank, edge); | |
6e60e79a | 702 | |
235f1eb1 GS |
703 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
704 | ||
92105bb7 TL |
705 | if (!isr) |
706 | break; | |
707 | ||
3513cdec JH |
708 | while (isr) { |
709 | bit = __ffs(isr); | |
b1e9fec2 | 710 | isr &= ~(BIT(bit)); |
25db711d | 711 | |
235f1eb1 | 712 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
713 | /* |
714 | * Some chips can't respond to both rising and falling | |
715 | * at the same time. If this irq was requested with | |
716 | * both flags, we need to flip the ICR data for the IRQ | |
717 | * to respond to the IRQ for the opposite direction. | |
718 | * This will be indicated in the bank toggle_mask. | |
719 | */ | |
b1e9fec2 | 720 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 721 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 722 | |
235f1eb1 GS |
723 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
724 | ||
450fa54c GS |
725 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
726 | ||
f0fbe7bc | 727 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 728 | bit)); |
450fa54c GS |
729 | |
730 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
731 | wa_lock_flags); | |
92105bb7 | 732 | } |
1a8bfa1e | 733 | } |
b1cc4c55 | 734 | exit: |
450fa54c | 735 | return IRQ_HANDLED; |
5e1c5ff4 TL |
736 | } |
737 | ||
3d009c8c TL |
738 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
739 | { | |
740 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 741 | unsigned long flags; |
37e14ecf | 742 | unsigned offset = d->hwirq; |
3d009c8c | 743 | |
4dbada2b | 744 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
745 | |
746 | if (!LINE_USED(bank->mod_usage, offset)) | |
747 | omap_set_gpio_direction(bank, offset, 1); | |
748 | else if (!omap_gpio_is_input(bank, offset)) | |
749 | goto err; | |
750 | omap_enable_gpio_module(bank, offset); | |
751 | bank->irq_usage |= BIT(offset); | |
752 | ||
4dbada2b | 753 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
754 | omap_gpio_unmask_irq(d); |
755 | ||
756 | return 0; | |
121dcb76 | 757 | err: |
4dbada2b | 758 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 759 | return -EINVAL; |
3d009c8c TL |
760 | } |
761 | ||
a0e827c6 | 762 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 763 | { |
a0e827c6 | 764 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 765 | unsigned long flags; |
9943f261 | 766 | unsigned offset = d->hwirq; |
4196dd6b | 767 | |
4dbada2b | 768 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 769 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 | 770 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 RK |
771 | omap_clear_gpio_irqstatus(bank, offset); |
772 | omap_set_gpio_irqenable(bank, offset, 0); | |
6e96c1b5 GS |
773 | if (!LINE_USED(bank->mod_usage, offset)) |
774 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 775 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 776 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
777 | } |
778 | ||
779 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
780 | { | |
781 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
782 | ||
46748073 | 783 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
784 | } |
785 | ||
786 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
787 | { | |
788 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 789 | |
46748073 | 790 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
791 | } |
792 | ||
a0e827c6 | 793 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 794 | { |
a0e827c6 | 795 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 796 | unsigned offset = d->hwirq; |
85ec7b97 | 797 | unsigned long flags; |
5e1c5ff4 | 798 | |
4dbada2b | 799 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 | 800 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 | 801 | omap_set_gpio_irqenable(bank, offset, 0); |
4dbada2b | 802 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
803 | } |
804 | ||
a0e827c6 | 805 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 806 | { |
a0e827c6 | 807 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 808 | unsigned offset = d->hwirq; |
8c04a176 | 809 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 810 | unsigned long flags; |
55b6019a | 811 | |
4dbada2b | 812 | raw_spin_lock_irqsave(&bank->lock, flags); |
d01849f7 RK |
813 | omap_set_gpio_irqenable(bank, offset, 1); |
814 | ||
815 | /* | |
816 | * For level-triggered GPIOs, clearing must be done after the source | |
817 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
818 | * after enabing the interrupt to clear the wakeup status. | |
819 | */ | |
c859e0d4 RK |
820 | if (bank->regs->leveldetect0 && bank->regs->wkup_en && |
821 | trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
9943f261 | 822 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 823 | |
c859e0d4 RK |
824 | if (trigger) |
825 | omap_set_gpio_triggering(bank, offset, trigger); | |
826 | ||
4dbada2b | 827 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
828 | } |
829 | ||
e5c56ed3 DB |
830 | /*---------------------------------------------------------------------*/ |
831 | ||
79ee031f | 832 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 833 | { |
a3f4f728 | 834 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
835 | void __iomem *mask_reg = bank->base + |
836 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 837 | unsigned long flags; |
11a78b79 | 838 | |
4dbada2b | 839 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 840 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 841 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
842 | |
843 | return 0; | |
844 | } | |
845 | ||
79ee031f | 846 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 847 | { |
a3f4f728 | 848 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
849 | void __iomem *mask_reg = bank->base + |
850 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 851 | unsigned long flags; |
11a78b79 | 852 | |
4dbada2b | 853 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 854 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 855 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
856 | |
857 | return 0; | |
858 | } | |
859 | ||
47145210 | 860 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
861 | .suspend_noirq = omap_mpuio_suspend_noirq, |
862 | .resume_noirq = omap_mpuio_resume_noirq, | |
863 | }; | |
864 | ||
3c437ffd | 865 | /* use platform_driver for this. */ |
11a78b79 | 866 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
867 | .driver = { |
868 | .name = "mpuio", | |
79ee031f | 869 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
870 | }, |
871 | }; | |
872 | ||
873 | static struct platform_device omap_mpuio_device = { | |
874 | .name = "mpuio", | |
875 | .id = -1, | |
876 | .dev = { | |
877 | .driver = &omap_mpuio_driver.driver, | |
878 | } | |
879 | /* could list the /proc/iomem resources */ | |
880 | }; | |
881 | ||
a0e827c6 | 882 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 883 | { |
77640aab | 884 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 885 | |
11a78b79 DB |
886 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
887 | (void) platform_device_register(&omap_mpuio_device); | |
888 | } | |
889 | ||
e5c56ed3 | 890 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 891 | |
dfbc6c7a RK |
892 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
893 | { | |
894 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
895 | unsigned long flags; | |
896 | ||
897 | pm_runtime_get_sync(chip->parent); | |
898 | ||
899 | raw_spin_lock_irqsave(&bank->lock, flags); | |
900 | omap_enable_gpio_module(bank, offset); | |
901 | bank->mod_usage |= BIT(offset); | |
902 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |
908 | { | |
909 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
910 | unsigned long flags; | |
911 | ||
912 | raw_spin_lock_irqsave(&bank->lock, flags); | |
913 | bank->mod_usage &= ~(BIT(offset)); | |
914 | if (!LINE_USED(bank->irq_usage, offset)) { | |
915 | omap_set_gpio_direction(bank, offset, 1); | |
916 | omap_clear_gpio_debounce(bank, offset); | |
917 | } | |
918 | omap_disable_gpio_module(bank, offset); | |
919 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
920 | ||
921 | pm_runtime_put(chip->parent); | |
922 | } | |
923 | ||
a0e827c6 | 924 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e | 925 | { |
40bb2273 | 926 | struct gpio_bank *bank = gpiochip_get_data(chip); |
9370084e | 927 | |
40bb2273 RK |
928 | return !!(readl_relaxed(bank->base + bank->regs->direction) & |
929 | BIT(offset)); | |
9370084e YY |
930 | } |
931 | ||
a0e827c6 | 932 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
933 | { |
934 | struct gpio_bank *bank; | |
935 | unsigned long flags; | |
936 | ||
d99f7aec | 937 | bank = gpiochip_get_data(chip); |
4dbada2b | 938 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 939 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 940 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
941 | return 0; |
942 | } | |
943 | ||
a0e827c6 | 944 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 945 | { |
5ca5f92c RK |
946 | struct gpio_bank *bank = gpiochip_get_data(chip); |
947 | void __iomem *reg; | |
b37c45b8 | 948 | |
b2b20045 | 949 | if (omap_gpio_is_input(bank, offset)) |
5ca5f92c | 950 | reg = bank->base + bank->regs->datain; |
b37c45b8 | 951 | else |
5ca5f92c RK |
952 | reg = bank->base + bank->regs->dataout; |
953 | ||
954 | return (readl_relaxed(reg) & BIT(offset)) != 0; | |
52e31344 DB |
955 | } |
956 | ||
a0e827c6 | 957 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
958 | { |
959 | struct gpio_bank *bank; | |
960 | unsigned long flags; | |
961 | ||
d99f7aec | 962 | bank = gpiochip_get_data(chip); |
4dbada2b | 963 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 964 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 965 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 966 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 967 | return 0; |
52e31344 DB |
968 | } |
969 | ||
442af140 JK |
970 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
971 | unsigned long *bits) | |
972 | { | |
973 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
6653dd88 RK |
974 | void __iomem *base = bank->base; |
975 | u32 direction, m, val = 0; | |
976 | ||
977 | direction = readl_relaxed(base + bank->regs->direction); | |
442af140 | 978 | |
6653dd88 RK |
979 | m = direction & *mask; |
980 | if (m) | |
981 | val |= readl_relaxed(base + bank->regs->datain) & m; | |
442af140 | 982 | |
6653dd88 RK |
983 | m = ~direction & *mask; |
984 | if (m) | |
985 | val |= readl_relaxed(base + bank->regs->dataout) & m; | |
442af140 | 986 | |
6653dd88 | 987 | *bits = val; |
442af140 JK |
988 | |
989 | return 0; | |
990 | } | |
991 | ||
a0e827c6 JMC |
992 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
993 | unsigned debounce) | |
168ef3d9 FB |
994 | { |
995 | struct gpio_bank *bank; | |
996 | unsigned long flags; | |
83977443 | 997 | int ret; |
168ef3d9 | 998 | |
d99f7aec | 999 | bank = gpiochip_get_data(chip); |
77640aab | 1000 | |
4dbada2b | 1001 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 1002 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 1003 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 1004 | |
83977443 DR |
1005 | if (ret) |
1006 | dev_info(chip->parent, | |
1007 | "Could not set line %u debounce to %u microseconds (%d)", | |
1008 | offset, debounce, ret); | |
1009 | ||
1010 | return ret; | |
168ef3d9 FB |
1011 | } |
1012 | ||
2956b5d9 MW |
1013 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
1014 | unsigned long config) | |
1015 | { | |
1016 | u32 debounce; | |
1017 | ||
1018 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
1019 | return -ENOTSUPP; | |
1020 | ||
1021 | debounce = pinconf_to_config_argument(config); | |
1022 | return omap_gpio_debounce(chip, offset, debounce); | |
1023 | } | |
1024 | ||
a0e827c6 | 1025 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1026 | { |
1027 | struct gpio_bank *bank; | |
1028 | unsigned long flags; | |
1029 | ||
d99f7aec | 1030 | bank = gpiochip_get_data(chip); |
4dbada2b | 1031 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1032 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1033 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1034 | } |
1035 | ||
442af140 JK |
1036 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
1037 | unsigned long *bits) | |
1038 | { | |
1039 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1040 | unsigned long flags; | |
1041 | ||
1042 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1043 | bank->set_dataout_multiple(bank, mask, bits); | |
1044 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1045 | } | |
1046 | ||
52e31344 DB |
1047 | /*---------------------------------------------------------------------*/ |
1048 | ||
e4b2ae7a | 1049 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1050 | { |
e5ff4440 | 1051 | static bool called; |
9f7065da TL |
1052 | u32 rev; |
1053 | ||
e5ff4440 | 1054 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1055 | return; |
1056 | ||
661553b9 | 1057 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1058 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1059 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1060 | |
1061 | called = true; | |
9f7065da TL |
1062 | } |
1063 | ||
03e128ca | 1064 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1065 | { |
ab985f0f TKD |
1066 | void __iomem *base = bank->base; |
1067 | u32 l = 0xffffffff; | |
2fae7fbe | 1068 | |
ab985f0f TKD |
1069 | if (bank->width == 16) |
1070 | l = 0xffff; | |
1071 | ||
d0d665a8 | 1072 | if (bank->is_mpuio) { |
661553b9 | 1073 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1074 | return; |
2fae7fbe | 1075 | } |
ab985f0f | 1076 | |
a0e827c6 JMC |
1077 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1078 | bank->regs->irqenable_inv); | |
1079 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1080 | !bank->regs->irqenable_inv); | |
ab985f0f | 1081 | if (bank->regs->debounce_en) |
661553b9 | 1082 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1083 | |
2dc983c5 | 1084 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1085 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1086 | /* Initialize interface clk ungated, module enabled */ |
1087 | if (bank->regs->ctrl) | |
661553b9 | 1088 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1089 | } |
1090 | ||
46824e22 | 1091 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1092 | { |
81930328 | 1093 | struct gpio_irq_chip *irq; |
2fae7fbe | 1094 | static int gpio; |
088413bc | 1095 | const char *label; |
fb655f57 | 1096 | int irq_base = 0; |
6ef7f385 | 1097 | int ret; |
2fae7fbe | 1098 | |
2fae7fbe VC |
1099 | /* |
1100 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1101 | * over to the generic ones | |
1102 | */ | |
1103 | bank->chip.request = omap_gpio_request; | |
1104 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1105 | bank->chip.get_direction = omap_gpio_get_direction; |
1106 | bank->chip.direction_input = omap_gpio_input; | |
1107 | bank->chip.get = omap_gpio_get; | |
442af140 | 1108 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1109 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1110 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1111 | bank->chip.set = omap_gpio_set; |
442af140 | 1112 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1113 | if (bank->is_mpuio) { |
2fae7fbe | 1114 | bank->chip.label = "mpuio"; |
6ed87c5b | 1115 | if (bank->regs->wkup_en) |
58383c78 | 1116 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1117 | bank->chip.base = OMAP_MPUIO(0); |
1118 | } else { | |
088413bc LW |
1119 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1120 | gpio, gpio + bank->width - 1); | |
1121 | if (!label) | |
1122 | return -ENOMEM; | |
1123 | bank->chip.label = label; | |
2fae7fbe | 1124 | bank->chip.base = gpio; |
2fae7fbe | 1125 | } |
d5f46247 | 1126 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1127 | |
fb655f57 JMC |
1128 | #ifdef CONFIG_ARCH_OMAP1 |
1129 | /* | |
1130 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1131 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1132 | */ | |
2ed36f30 BG |
1133 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1134 | -1, 0, bank->width, 0); | |
fb655f57 | 1135 | if (irq_base < 0) { |
7b1e5dc8 | 1136 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1137 | return -ENODEV; |
1138 | } | |
1139 | #endif | |
1140 | ||
d2d05c65 | 1141 | /* MPUIO is a bit different, reading IRQ status clears it */ |
693de831 RK |
1142 | if (bank->is_mpuio && !bank->regs->wkup_en) |
1143 | irqc->irq_set_wake = NULL; | |
d2d05c65 | 1144 | |
81930328 GS |
1145 | irq = &bank->chip.irq; |
1146 | irq->chip = irqc; | |
1147 | irq->handler = handle_bad_irq; | |
1148 | irq->default_type = IRQ_TYPE_NONE; | |
1149 | irq->num_parents = 1; | |
1150 | irq->parents = &bank->irq; | |
1151 | irq->first = irq_base; | |
fb655f57 | 1152 | |
81930328 | 1153 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1154 | if (ret) { |
7b1e5dc8 | 1155 | dev_err(bank->chip.parent, |
81930328 GS |
1156 | "Could not register gpio chip %d\n", ret); |
1157 | return ret; | |
fb655f57 JMC |
1158 | } |
1159 | ||
7b1e5dc8 GS |
1160 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1161 | omap_gpio_irq_handler, | |
1162 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1163 | if (ret) |
1164 | gpiochip_remove(&bank->chip); | |
1165 | ||
81930328 GS |
1166 | if (!bank->is_mpuio) |
1167 | gpio += bank->width; | |
1168 | ||
450fa54c | 1169 | return ret; |
2fae7fbe VC |
1170 | } |
1171 | ||
7c68571f | 1172 | static void omap_gpio_init_context(struct gpio_bank *p) |
b764a586 | 1173 | { |
7c68571f AB |
1174 | struct omap_gpio_reg_offs *regs = p->regs; |
1175 | void __iomem *base = p->base; | |
b764a586 | 1176 | |
7c68571f AB |
1177 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1178 | p->context.oe = readl_relaxed(base + regs->direction); | |
1179 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1180 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1181 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1182 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1183 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1184 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1185 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
b764a586 | 1186 | |
7c68571f AB |
1187 | if (regs->set_dataout && p->regs->clr_dataout) |
1188 | p->context.dataout = readl_relaxed(base + regs->set_dataout); | |
1189 | else | |
1190 | p->context.dataout = readl_relaxed(base + regs->dataout); | |
b764a586 | 1191 | |
7c68571f | 1192 | p->context_valid = true; |
b764a586 TL |
1193 | } |
1194 | ||
7c68571f | 1195 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
5e1c5ff4 | 1196 | { |
7c68571f AB |
1197 | writel_relaxed(bank->context.wake_en, |
1198 | bank->base + bank->regs->wkup_en); | |
1199 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1200 | writel_relaxed(bank->context.leveldetect0, | |
1201 | bank->base + bank->regs->leveldetect0); | |
1202 | writel_relaxed(bank->context.leveldetect1, | |
1203 | bank->base + bank->regs->leveldetect1); | |
1204 | writel_relaxed(bank->context.risingdetect, | |
1205 | bank->base + bank->regs->risingdetect); | |
1206 | writel_relaxed(bank->context.fallingdetect, | |
1207 | bank->base + bank->regs->fallingdetect); | |
1208 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1209 | writel_relaxed(bank->context.dataout, | |
1210 | bank->base + bank->regs->set_dataout); | |
1211 | else | |
1212 | writel_relaxed(bank->context.dataout, | |
1213 | bank->base + bank->regs->dataout); | |
1214 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); | |
9f7065da | 1215 | |
7c68571f AB |
1216 | if (bank->dbck_enable_mask) { |
1217 | writel_relaxed(bank->context.debounce, bank->base + | |
1218 | bank->regs->debounce); | |
1219 | writel_relaxed(bank->context.debounce_en, | |
1220 | bank->base + bank->regs->debounce_en); | |
b764a586 TL |
1221 | } |
1222 | ||
7c68571f AB |
1223 | writel_relaxed(bank->context.irqenable1, |
1224 | bank->base + bank->regs->irqenable); | |
1225 | writel_relaxed(bank->context.irqenable2, | |
1226 | bank->base + bank->regs->irqenable2); | |
cac089f9 TL |
1227 | } |
1228 | ||
b764a586 | 1229 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1230 | { |
b764a586 | 1231 | struct device *dev = bank->chip.parent; |
21e2118f TL |
1232 | void __iomem *base = bank->base; |
1233 | u32 nowake; | |
1234 | ||
1235 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1236 | |
b3c64bc3 KH |
1237 | if (!bank->enabled_non_wakeup_gpios) |
1238 | goto update_gpio_context_count; | |
1239 | ||
b764a586 | 1240 | if (!may_lose_context) |
41d87cbd | 1241 | goto update_gpio_context_count; |
b764a586 | 1242 | |
2dc983c5 | 1243 | /* |
21e2118f | 1244 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1245 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1246 | * generated. See OMAP2420 Errata item 1.101. | |
1247 | */ | |
21e2118f TL |
1248 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1249 | nowake = bank->enabled_non_wakeup_gpios; | |
1250 | omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake); | |
1251 | omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake); | |
1252 | } | |
3f1686a9 | 1253 | |
41d87cbd | 1254 | update_gpio_context_count: |
2dc983c5 TKD |
1255 | if (bank->get_context_loss_count) |
1256 | bank->context_loss_count = | |
7b1e5dc8 | 1257 | bank->get_context_loss_count(dev); |
60a3437d | 1258 | |
a0e827c6 | 1259 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1260 | } |
1261 | ||
b764a586 | 1262 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1263 | { |
b764a586 | 1264 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1265 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1266 | int c; |
8865b9b6 | 1267 | |
352a2d5b JH |
1268 | /* |
1269 | * On the first resume during the probe, the context has not | |
1270 | * been initialised and so initialise it now. Also initialise | |
1271 | * the context loss count. | |
1272 | */ | |
1273 | if (bank->loses_context && !bank->context_valid) { | |
1274 | omap_gpio_init_context(bank); | |
1275 | ||
1276 | if (bank->get_context_loss_count) | |
1277 | bank->context_loss_count = | |
7b1e5dc8 | 1278 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1279 | } |
1280 | ||
a0e827c6 | 1281 | omap_gpio_dbck_enable(bank); |
68942edb | 1282 | |
a2797bea JH |
1283 | if (bank->loses_context) { |
1284 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1285 | omap_gpio_restore_context(bank); |
1286 | } else { | |
7b1e5dc8 | 1287 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1288 | if (c != bank->context_loss_count) { |
1289 | omap_gpio_restore_context(bank); | |
1290 | } else { | |
b764a586 | 1291 | return; |
a2797bea | 1292 | } |
60a3437d | 1293 | } |
21e2118f TL |
1294 | } else { |
1295 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1296 | writel_relaxed(bank->context.fallingdetect, | |
1297 | bank->base + bank->regs->fallingdetect); | |
1298 | writel_relaxed(bank->context.risingdetect, | |
1299 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1300 | } |
43ffcd9a | 1301 | |
661553b9 | 1302 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1303 | |
2dc983c5 TKD |
1304 | /* |
1305 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1306 | * state. If so, generate an IRQ by software. This is | |
1307 | * horribly racy, but it's the best we can do to work around | |
1308 | * this silicon bug. | |
1309 | */ | |
1310 | l ^= bank->saved_datain; | |
1311 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1312 | |
2dc983c5 TKD |
1313 | /* |
1314 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1315 | * configured with falling edge only; and vice versa. | |
1316 | */ | |
c6f31c9e | 1317 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1318 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1319 | |
c6f31c9e | 1320 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1321 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1322 | |
2dc983c5 | 1323 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1324 | gen = l & (~(bank->context.fallingdetect) & |
1325 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1326 | /* Consider all GPIO IRQs needed to be updated */ |
1327 | gen |= gen0 | gen1; | |
82dbb9d3 | 1328 | |
2dc983c5 TKD |
1329 | if (gen) { |
1330 | u32 old0, old1; | |
82dbb9d3 | 1331 | |
661553b9 VK |
1332 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1333 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1334 | |
4e962e89 | 1335 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1336 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1337 | bank->regs->leveldetect0); |
661553b9 | 1338 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1339 | bank->regs->leveldetect1); |
2dc983c5 | 1340 | } |
9ea14d8c | 1341 | |
4e962e89 | 1342 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1343 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1344 | bank->regs->leveldetect0); |
661553b9 | 1345 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1346 | bank->regs->leveldetect1); |
3ac4fa99 | 1347 | } |
661553b9 VK |
1348 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1349 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1350 | } |
2dc983c5 | 1351 | } |
2dc983c5 | 1352 | |
7c68571f AB |
1353 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, |
1354 | unsigned long cmd, void *v) | |
352a2d5b | 1355 | { |
7c68571f AB |
1356 | struct gpio_bank *bank; |
1357 | unsigned long flags; | |
352a2d5b | 1358 | |
7c68571f | 1359 | bank = container_of(nb, struct gpio_bank, nb); |
352a2d5b | 1360 | |
7c68571f AB |
1361 | raw_spin_lock_irqsave(&bank->lock, flags); |
1362 | switch (cmd) { | |
1363 | case CPU_CLUSTER_PM_ENTER: | |
1364 | if (bank->is_suspended) | |
1365 | break; | |
1366 | omap_gpio_idle(bank, true); | |
1367 | break; | |
1368 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1369 | case CPU_CLUSTER_PM_EXIT: | |
1370 | if (bank->is_suspended) | |
1371 | break; | |
1372 | omap_gpio_unidle(bank); | |
1373 | break; | |
1374 | } | |
1375 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
352a2d5b | 1376 | |
7c68571f | 1377 | return NOTIFY_OK; |
b764a586 TL |
1378 | } |
1379 | ||
384ebe1c BC |
1380 | static struct omap_gpio_reg_offs omap2_gpio_regs = { |
1381 | .revision = OMAP24XX_GPIO_REVISION, | |
1382 | .direction = OMAP24XX_GPIO_OE, | |
1383 | .datain = OMAP24XX_GPIO_DATAIN, | |
1384 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1385 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1386 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1387 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1388 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1389 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1390 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1391 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1392 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1393 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1394 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1395 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1396 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1397 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1398 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1399 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1400 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1401 | }; | |
1402 | ||
1403 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1404 | .revision = OMAP4_GPIO_REVISION, | |
1405 | .direction = OMAP4_GPIO_OE, | |
1406 | .datain = OMAP4_GPIO_DATAIN, | |
1407 | .dataout = OMAP4_GPIO_DATAOUT, | |
1408 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1409 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1410 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1411 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
64ea3e90 RK |
1412 | .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, |
1413 | .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, | |
384ebe1c BC |
1414 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, |
1415 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1416 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1417 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1418 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1419 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1420 | .ctrl = OMAP4_GPIO_CTRL, | |
1421 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1422 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1423 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1424 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1425 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1426 | }; | |
1427 | ||
e9a65bb6 | 1428 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1429 | .regs = &omap2_gpio_regs, |
1430 | .bank_width = 32, | |
1431 | .dbck_flag = false, | |
1432 | }; | |
1433 | ||
e9a65bb6 | 1434 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1435 | .regs = &omap2_gpio_regs, |
1436 | .bank_width = 32, | |
1437 | .dbck_flag = true, | |
1438 | }; | |
1439 | ||
e9a65bb6 | 1440 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1441 | .regs = &omap4_gpio_regs, |
1442 | .bank_width = 32, | |
1443 | .dbck_flag = true, | |
1444 | }; | |
1445 | ||
1446 | static const struct of_device_id omap_gpio_match[] = { | |
1447 | { | |
1448 | .compatible = "ti,omap4-gpio", | |
1449 | .data = &omap4_pdata, | |
1450 | }, | |
1451 | { | |
1452 | .compatible = "ti,omap3-gpio", | |
1453 | .data = &omap3_pdata, | |
1454 | }, | |
1455 | { | |
1456 | .compatible = "ti,omap2-gpio", | |
1457 | .data = &omap2_pdata, | |
1458 | }, | |
1459 | { }, | |
1460 | }; | |
1461 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
7c68571f AB |
1462 | |
1463 | static int omap_gpio_probe(struct platform_device *pdev) | |
1464 | { | |
1465 | struct device *dev = &pdev->dev; | |
1466 | struct device_node *node = dev->of_node; | |
1467 | const struct of_device_id *match; | |
1468 | const struct omap_gpio_platform_data *pdata; | |
7c68571f AB |
1469 | struct gpio_bank *bank; |
1470 | struct irq_chip *irqc; | |
1471 | int ret; | |
1472 | ||
1473 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); | |
1474 | ||
1475 | pdata = match ? match->data : dev_get_platdata(dev); | |
1476 | if (!pdata) | |
1477 | return -EINVAL; | |
1478 | ||
1479 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
1480 | if (!bank) | |
1481 | return -ENOMEM; | |
1482 | ||
1483 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); | |
1484 | if (!irqc) | |
1485 | return -ENOMEM; | |
1486 | ||
1487 | irqc->irq_startup = omap_gpio_irq_startup, | |
1488 | irqc->irq_shutdown = omap_gpio_irq_shutdown, | |
693de831 | 1489 | irqc->irq_ack = dummy_irq_chip.irq_ack, |
7c68571f AB |
1490 | irqc->irq_mask = omap_gpio_mask_irq, |
1491 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1492 | irqc->irq_set_type = omap_gpio_irq_type, | |
1493 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1494 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, | |
1495 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
1496 | irqc->name = dev_name(&pdev->dev); | |
1497 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1498 | irqc->parent_device = dev; | |
1499 | ||
1500 | bank->irq = platform_get_irq(pdev, 0); | |
1501 | if (bank->irq <= 0) { | |
1502 | if (!bank->irq) | |
1503 | bank->irq = -ENXIO; | |
1504 | if (bank->irq != -EPROBE_DEFER) | |
1505 | dev_err(dev, | |
1506 | "can't get irq resource ret=%d\n", bank->irq); | |
1507 | return bank->irq; | |
1508 | } | |
1509 | ||
1510 | bank->chip.parent = dev; | |
1511 | bank->chip.owner = THIS_MODULE; | |
1512 | bank->dbck_flag = pdata->dbck_flag; | |
7c68571f AB |
1513 | bank->stride = pdata->bank_stride; |
1514 | bank->width = pdata->bank_width; | |
1515 | bank->is_mpuio = pdata->is_mpuio; | |
1516 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; | |
1517 | bank->regs = pdata->regs; | |
1518 | #ifdef CONFIG_OF_GPIO | |
1519 | bank->chip.of_node = of_node_get(node); | |
384ebe1c BC |
1520 | #endif |
1521 | ||
7c68571f AB |
1522 | if (node) { |
1523 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1524 | bank->loses_context = true; | |
1525 | } else { | |
1526 | bank->loses_context = pdata->loses_context; | |
1527 | ||
1528 | if (bank->loses_context) | |
1529 | bank->get_context_loss_count = | |
1530 | pdata->get_context_loss_count; | |
1531 | } | |
1532 | ||
1533 | if (bank->regs->set_dataout && bank->regs->clr_dataout) { | |
1534 | bank->set_dataout = omap_set_gpio_dataout_reg; | |
1535 | bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; | |
1536 | } else { | |
1537 | bank->set_dataout = omap_set_gpio_dataout_mask; | |
1538 | bank->set_dataout_multiple = | |
1539 | omap_set_gpio_dataout_mask_multiple; | |
1540 | } | |
1541 | ||
7c68571f AB |
1542 | raw_spin_lock_init(&bank->lock); |
1543 | raw_spin_lock_init(&bank->wa_lock); | |
1544 | ||
1545 | /* Static mapping, never released */ | |
58f57f86 | 1546 | bank->base = devm_platform_ioremap_resource(pdev, 0); |
7c68571f AB |
1547 | if (IS_ERR(bank->base)) { |
1548 | return PTR_ERR(bank->base); | |
1549 | } | |
1550 | ||
1551 | if (bank->dbck_flag) { | |
1552 | bank->dbck = devm_clk_get(dev, "dbclk"); | |
1553 | if (IS_ERR(bank->dbck)) { | |
1554 | dev_err(dev, | |
1555 | "Could not get gpio dbck. Disable debounce\n"); | |
1556 | bank->dbck_flag = false; | |
1557 | } else { | |
1558 | clk_prepare(bank->dbck); | |
1559 | } | |
1560 | } | |
1561 | ||
1562 | platform_set_drvdata(pdev, bank); | |
1563 | ||
1564 | pm_runtime_enable(dev); | |
1565 | pm_runtime_get_sync(dev); | |
1566 | ||
1567 | if (bank->is_mpuio) | |
1568 | omap_mpuio_init(bank); | |
1569 | ||
1570 | omap_gpio_mod_init(bank); | |
1571 | ||
1572 | ret = omap_gpio_chip_init(bank, irqc); | |
1573 | if (ret) { | |
1574 | pm_runtime_put_sync(dev); | |
1575 | pm_runtime_disable(dev); | |
1576 | if (bank->dbck_flag) | |
1577 | clk_unprepare(bank->dbck); | |
1578 | return ret; | |
1579 | } | |
1580 | ||
1581 | omap_gpio_show_rev(bank); | |
1582 | ||
e6818d29 RK |
1583 | bank->nb.notifier_call = gpio_omap_cpu_notifier; |
1584 | cpu_pm_register_notifier(&bank->nb); | |
7c68571f AB |
1585 | |
1586 | pm_runtime_put(dev); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | static int omap_gpio_remove(struct platform_device *pdev) | |
1592 | { | |
1593 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1594 | ||
e6818d29 | 1595 | cpu_pm_unregister_notifier(&bank->nb); |
7c68571f AB |
1596 | gpiochip_remove(&bank->chip); |
1597 | pm_runtime_disable(&pdev->dev); | |
1598 | if (bank->dbck_flag) | |
1599 | clk_unprepare(bank->dbck); | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) | |
1605 | { | |
1606 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1607 | unsigned long flags; | |
7c68571f AB |
1608 | |
1609 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1610 | omap_gpio_idle(bank, true); |
1611 | bank->is_suspended = true; | |
7c68571f AB |
1612 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1613 | ||
044e499a | 1614 | return 0; |
7c68571f AB |
1615 | } |
1616 | ||
1617 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1618 | { | |
1619 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1620 | unsigned long flags; | |
7c68571f AB |
1621 | |
1622 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1623 | omap_gpio_unidle(bank); |
1624 | bank->is_suspended = false; | |
7c68571f AB |
1625 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1626 | ||
044e499a | 1627 | return 0; |
7c68571f AB |
1628 | } |
1629 | ||
1630 | static const struct dev_pm_ops gpio_pm_ops = { | |
1631 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, | |
1632 | NULL) | |
1633 | }; | |
1634 | ||
77640aab VC |
1635 | static struct platform_driver omap_gpio_driver = { |
1636 | .probe = omap_gpio_probe, | |
cac089f9 | 1637 | .remove = omap_gpio_remove, |
77640aab VC |
1638 | .driver = { |
1639 | .name = "omap_gpio", | |
55b93c32 | 1640 | .pm = &gpio_pm_ops, |
7c68571f | 1641 | .of_match_table = omap_gpio_match, |
77640aab VC |
1642 | }, |
1643 | }; | |
1644 | ||
5e1c5ff4 | 1645 | /* |
77640aab VC |
1646 | * gpio driver register needs to be done before |
1647 | * machine_init functions access gpio APIs. | |
1648 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1649 | */ |
77640aab | 1650 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1651 | { |
77640aab | 1652 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1653 | } |
77640aab | 1654 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1655 | |
1656 | static void __exit omap_gpio_exit(void) | |
1657 | { | |
1658 | platform_driver_unregister(&omap_gpio_driver); | |
1659 | } | |
1660 | module_exit(omap_gpio_exit); | |
1661 | ||
1662 | MODULE_DESCRIPTION("omap gpio driver"); | |
1663 | MODULE_ALIAS("platform:gpio-omap"); | |
1664 | MODULE_LICENSE("GPL v2"); |