Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 TKD |
31 | #define OFF_MODE 1 |
32 | ||
03e128ca C |
33 | static LIST_HEAD(omap_gpio_list); |
34 | ||
6d62e216 C |
35 | struct gpio_regs { |
36 | u32 irqenable1; | |
37 | u32 irqenable2; | |
38 | u32 wake_en; | |
39 | u32 ctrl; | |
40 | u32 oe; | |
41 | u32 leveldetect0; | |
42 | u32 leveldetect1; | |
43 | u32 risingdetect; | |
44 | u32 fallingdetect; | |
45 | u32 dataout; | |
ae547354 NM |
46 | u32 debounce; |
47 | u32 debounce_en; | |
6d62e216 C |
48 | }; |
49 | ||
5e1c5ff4 | 50 | struct gpio_bank { |
03e128ca | 51 | struct list_head node; |
92105bb7 | 52 | void __iomem *base; |
5e1c5ff4 | 53 | u16 irq; |
3ac4fa99 JY |
54 | u32 non_wakeup_gpios; |
55 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 56 | struct gpio_regs context; |
3ac4fa99 | 57 | u32 saved_datain; |
b144ff6f | 58 | u32 level_mask; |
4318f36b | 59 | u32 toggle_mask; |
5e1c5ff4 | 60 | spinlock_t lock; |
52e31344 | 61 | struct gpio_chip chip; |
89db9482 | 62 | struct clk *dbck; |
058af1ea | 63 | u32 mod_usage; |
fa365e4d | 64 | u32 irq_usage; |
8865b9b6 | 65 | u32 dbck_enable_mask; |
72f83af9 | 66 | bool dbck_enabled; |
77640aab | 67 | struct device *dev; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
2dc983c5 TKD |
75 | int power_mode; |
76 | bool workaround_enabled; | |
fa87931a | 77 | |
04ebcbd8 | 78 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 79 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
80 | |
81 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
82 | }; |
83 | ||
129fd223 | 84 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
b1e9fec2 | 85 | #define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio))) |
c8eef65a | 86 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 87 | |
fa365e4d | 88 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 89 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 90 | |
3d009c8c TL |
91 | static void omap_gpio_unmask_irq(struct irq_data *d); |
92 | ||
a0e827c6 | 93 | static int omap_irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
25db711d | 94 | { |
ede4d7a5 JH |
95 | return bank->chip.base + gpio_irq; |
96 | } | |
97 | ||
a0e827c6 | 98 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 99 | { |
fb655f57 JMC |
100 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
101 | return container_of(chip, struct gpio_bank, chip); | |
25db711d BC |
102 | } |
103 | ||
a0e827c6 JMC |
104 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
105 | int is_input) | |
5e1c5ff4 | 106 | { |
92105bb7 | 107 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
108 | u32 l; |
109 | ||
fa87931a | 110 | reg += bank->regs->direction; |
661553b9 | 111 | l = readl_relaxed(reg); |
5e1c5ff4 | 112 | if (is_input) |
b1e9fec2 | 113 | l |= BIT(gpio); |
5e1c5ff4 | 114 | else |
b1e9fec2 | 115 | l &= ~(BIT(gpio)); |
661553b9 | 116 | writel_relaxed(l, reg); |
41d87cbd | 117 | bank->context.oe = l; |
5e1c5ff4 TL |
118 | } |
119 | ||
fa87931a KH |
120 | |
121 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 122 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 123 | int enable) |
5e1c5ff4 | 124 | { |
92105bb7 | 125 | void __iomem *reg = bank->base; |
04ebcbd8 | 126 | u32 l = BIT(offset); |
5e1c5ff4 | 127 | |
2c836f7e | 128 | if (enable) { |
fa87931a | 129 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
130 | bank->context.dataout |= l; |
131 | } else { | |
fa87931a | 132 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
133 | bank->context.dataout &= ~l; |
134 | } | |
5e1c5ff4 | 135 | |
661553b9 | 136 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
137 | } |
138 | ||
fa87931a | 139 | /* set data out value using mask register */ |
04ebcbd8 | 140 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 141 | int enable) |
5e1c5ff4 | 142 | { |
fa87931a | 143 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 144 | u32 gpio_bit = BIT(offset); |
fa87931a | 145 | u32 l; |
5e1c5ff4 | 146 | |
661553b9 | 147 | l = readl_relaxed(reg); |
fa87931a KH |
148 | if (enable) |
149 | l |= gpio_bit; | |
150 | else | |
151 | l &= ~gpio_bit; | |
661553b9 | 152 | writel_relaxed(l, reg); |
41d87cbd | 153 | bank->context.dataout = l; |
5e1c5ff4 TL |
154 | } |
155 | ||
a0e827c6 | 156 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 157 | { |
fa87931a | 158 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 159 | |
b1e9fec2 | 160 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 161 | } |
b37c45b8 | 162 | |
a0e827c6 | 163 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 164 | { |
fa87931a | 165 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 166 | |
b1e9fec2 | 167 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
168 | } |
169 | ||
a0e827c6 | 170 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 171 | { |
661553b9 | 172 | int l = readl_relaxed(base + reg); |
ece9528e | 173 | |
862ff640 | 174 | if (set) |
ece9528e KH |
175 | l |= mask; |
176 | else | |
177 | l &= ~mask; | |
178 | ||
661553b9 | 179 | writel_relaxed(l, base + reg); |
ece9528e | 180 | } |
92105bb7 | 181 | |
a0e827c6 | 182 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
183 | { |
184 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
345477ff | 185 | clk_prepare_enable(bank->dbck); |
72f83af9 | 186 | bank->dbck_enabled = true; |
9e303f22 | 187 | |
661553b9 | 188 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 189 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
190 | } |
191 | } | |
192 | ||
a0e827c6 | 193 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
194 | { |
195 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
196 | /* |
197 | * Disable debounce before cutting it's clock. If debounce is | |
198 | * enabled but the clock is not, GPIO module seems to be unable | |
199 | * to detect events and generate interrupts at least on OMAP3. | |
200 | */ | |
661553b9 | 201 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 202 | |
345477ff | 203 | clk_disable_unprepare(bank->dbck); |
72f83af9 TKD |
204 | bank->dbck_enabled = false; |
205 | } | |
206 | } | |
207 | ||
168ef3d9 | 208 | /** |
a0e827c6 | 209 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 210 | * @bank: the gpio bank we're acting upon |
4a58d229 | 211 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
212 | * @debounce: debounce time to use |
213 | * | |
214 | * OMAP's debounce time is in 31us steps so we need | |
215 | * to convert and round up to the closest unit. | |
216 | */ | |
4a58d229 | 217 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 218 | unsigned debounce) |
168ef3d9 | 219 | { |
9942da0e | 220 | void __iomem *reg; |
168ef3d9 FB |
221 | u32 val; |
222 | u32 l; | |
223 | ||
77640aab VC |
224 | if (!bank->dbck_flag) |
225 | return; | |
226 | ||
168ef3d9 FB |
227 | if (debounce < 32) |
228 | debounce = 0x01; | |
229 | else if (debounce > 7936) | |
230 | debounce = 0xff; | |
231 | else | |
232 | debounce = (debounce / 0x1f) - 1; | |
233 | ||
4a58d229 | 234 | l = BIT(offset); |
168ef3d9 | 235 | |
345477ff | 236 | clk_prepare_enable(bank->dbck); |
9942da0e | 237 | reg = bank->base + bank->regs->debounce; |
661553b9 | 238 | writel_relaxed(debounce, reg); |
168ef3d9 | 239 | |
9942da0e | 240 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 241 | val = readl_relaxed(reg); |
168ef3d9 | 242 | |
6fd9c421 | 243 | if (debounce) |
168ef3d9 | 244 | val |= l; |
6fd9c421 | 245 | else |
168ef3d9 | 246 | val &= ~l; |
f7ec0b0b | 247 | bank->dbck_enable_mask = val; |
168ef3d9 | 248 | |
661553b9 | 249 | writel_relaxed(val, reg); |
345477ff | 250 | clk_disable_unprepare(bank->dbck); |
6fd9c421 TKD |
251 | /* |
252 | * Enable debounce clock per module. | |
253 | * This call is mandatory because in omap_gpio_request() when | |
254 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
255 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
256 | * used within _gpio_dbck_enable() is still not initialized at | |
257 | * that point. Therefore we have to enable dbck here. | |
258 | */ | |
a0e827c6 | 259 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
260 | if (bank->dbck_enable_mask) { |
261 | bank->context.debounce = debounce; | |
262 | bank->context.debounce_en = val; | |
263 | } | |
168ef3d9 FB |
264 | } |
265 | ||
c9c55d92 | 266 | /** |
a0e827c6 | 267 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 268 | * @bank: the gpio bank we're acting upon |
4a58d229 | 269 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
270 | * |
271 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
272 | * this is the only gpio in this bank using debounce, then clear the debounce | |
273 | * time too. The debounce clock will also be disabled when calling this function | |
274 | * if this is the only gpio in the bank using debounce. | |
275 | */ | |
4a58d229 | 276 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 277 | { |
4a58d229 | 278 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
279 | |
280 | if (!bank->dbck_flag) | |
281 | return; | |
282 | ||
283 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
284 | return; | |
285 | ||
286 | bank->dbck_enable_mask &= ~gpio_bit; | |
287 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 288 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
289 | bank->base + bank->regs->debounce_en); |
290 | ||
291 | if (!bank->dbck_enable_mask) { | |
292 | bank->context.debounce = 0; | |
661553b9 | 293 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 294 | bank->regs->debounce); |
345477ff | 295 | clk_disable_unprepare(bank->dbck); |
c9c55d92 JH |
296 | bank->dbck_enabled = false; |
297 | } | |
298 | } | |
299 | ||
a0e827c6 | 300 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 301 | unsigned trigger) |
5e1c5ff4 | 302 | { |
3ac4fa99 | 303 | void __iomem *base = bank->base; |
b1e9fec2 | 304 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 305 | |
a0e827c6 JMC |
306 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
307 | trigger & IRQ_TYPE_LEVEL_LOW); | |
308 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
309 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
310 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
311 | trigger & IRQ_TYPE_EDGE_RISING); | |
312 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
313 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 314 | |
41d87cbd | 315 | bank->context.leveldetect0 = |
661553b9 | 316 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 317 | bank->context.leveldetect1 = |
661553b9 | 318 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 319 | bank->context.risingdetect = |
661553b9 | 320 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 321 | bank->context.fallingdetect = |
661553b9 | 322 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
323 | |
324 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 325 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 326 | bank->context.wake_en = |
661553b9 | 327 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 328 | } |
5e571f38 | 329 | |
55b220ca | 330 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
331 | if (!bank->regs->irqctrl) { |
332 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
333 | if (bank->non_wakeup_gpios) { | |
334 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
335 | goto exit; | |
336 | } | |
337 | ||
699117a6 CW |
338 | /* |
339 | * Log the edge gpio and manually trigger the IRQ | |
340 | * after resume if the input level changes | |
341 | * to avoid irq lost during PER RET/OFF mode | |
342 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
343 | */ | |
344 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
345 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
346 | else | |
347 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
348 | } | |
5eb3bb9c | 349 | |
5e571f38 | 350 | exit: |
9ea14d8c | 351 | bank->level_mask = |
661553b9 VK |
352 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
353 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
354 | } |
355 | ||
9198bcd3 | 356 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
357 | /* |
358 | * This only applies to chips that can't do both rising and falling edge | |
359 | * detection at once. For all other chips, this function is a noop. | |
360 | */ | |
a0e827c6 | 361 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
362 | { |
363 | void __iomem *reg = bank->base; | |
364 | u32 l = 0; | |
365 | ||
5e571f38 | 366 | if (!bank->regs->irqctrl) |
4318f36b | 367 | return; |
5e571f38 TKD |
368 | |
369 | reg += bank->regs->irqctrl; | |
4318f36b | 370 | |
661553b9 | 371 | l = readl_relaxed(reg); |
4318f36b | 372 | if ((l >> gpio) & 1) |
b1e9fec2 | 373 | l &= ~(BIT(gpio)); |
4318f36b | 374 | else |
b1e9fec2 | 375 | l |= BIT(gpio); |
4318f36b | 376 | |
661553b9 | 377 | writel_relaxed(l, reg); |
4318f36b | 378 | } |
5e571f38 | 379 | #else |
a0e827c6 | 380 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 381 | #endif |
4318f36b | 382 | |
a0e827c6 JMC |
383 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
384 | unsigned trigger) | |
92105bb7 TL |
385 | { |
386 | void __iomem *reg = bank->base; | |
5e571f38 | 387 | void __iomem *base = bank->base; |
92105bb7 | 388 | u32 l = 0; |
5e1c5ff4 | 389 | |
5e571f38 | 390 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 391 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
392 | } else if (bank->regs->irqctrl) { |
393 | reg += bank->regs->irqctrl; | |
394 | ||
661553b9 | 395 | l = readl_relaxed(reg); |
29501577 | 396 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 397 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 398 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 399 | l |= BIT(gpio); |
6cab4860 | 400 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 401 | l &= ~(BIT(gpio)); |
92105bb7 | 402 | else |
5e571f38 TKD |
403 | return -EINVAL; |
404 | ||
661553b9 | 405 | writel_relaxed(l, reg); |
5e571f38 | 406 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 407 | if (gpio & 0x08) |
5e571f38 | 408 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 409 | else |
5e571f38 TKD |
410 | reg += bank->regs->edgectrl1; |
411 | ||
5e1c5ff4 | 412 | gpio &= 0x07; |
661553b9 | 413 | l = readl_relaxed(reg); |
5e1c5ff4 | 414 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 415 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 416 | l |= 2 << (gpio << 1); |
6cab4860 | 417 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 418 | l |= BIT(gpio << 1); |
5e571f38 TKD |
419 | |
420 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 421 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 422 | bank->context.wake_en = |
661553b9 VK |
423 | readl_relaxed(bank->base + bank->regs->wkup_en); |
424 | writel_relaxed(l, reg); | |
5e1c5ff4 | 425 | } |
92105bb7 | 426 | return 0; |
5e1c5ff4 TL |
427 | } |
428 | ||
a0e827c6 | 429 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
430 | { |
431 | if (bank->regs->pinctrl) { | |
432 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
433 | ||
434 | /* Claim the pin for MPU */ | |
b1e9fec2 | 435 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
436 | } |
437 | ||
438 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
439 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
440 | u32 ctrl; | |
441 | ||
661553b9 | 442 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
443 | /* Module is enabled, clocks are not gated */ |
444 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 445 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
446 | bank->context.ctrl = ctrl; |
447 | } | |
448 | } | |
449 | ||
a0e827c6 | 450 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
451 | { |
452 | void __iomem *base = bank->base; | |
453 | ||
454 | if (bank->regs->wkup_en && | |
455 | !LINE_USED(bank->mod_usage, offset) && | |
456 | !LINE_USED(bank->irq_usage, offset)) { | |
457 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 458 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 459 | bank->context.wake_en = |
661553b9 | 460 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
461 | } |
462 | ||
463 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
464 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
465 | u32 ctrl; | |
466 | ||
661553b9 | 467 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
468 | /* Module is disabled, clocks are gated */ |
469 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 470 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
471 | bank->context.ctrl = ctrl; |
472 | } | |
473 | } | |
474 | ||
b2b20045 | 475 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
476 | { |
477 | void __iomem *reg = bank->base + bank->regs->direction; | |
478 | ||
b2b20045 | 479 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
480 | } |
481 | ||
3d009c8c TL |
482 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned gpio, |
483 | unsigned offset) | |
484 | { | |
485 | if (!LINE_USED(bank->mod_usage, offset)) { | |
486 | omap_enable_gpio_module(bank, offset); | |
487 | omap_set_gpio_direction(bank, offset, 1); | |
488 | } | |
489 | bank->irq_usage |= BIT(GPIO_INDEX(bank, gpio)); | |
490 | } | |
491 | ||
a0e827c6 | 492 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 493 | { |
a0e827c6 | 494 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
4b25408f | 495 | unsigned gpio = 0; |
92105bb7 | 496 | int retval; |
a6472533 | 497 | unsigned long flags; |
fac7fa16 | 498 | unsigned offset; |
92105bb7 | 499 | |
fac7fa16 JMC |
500 | if (!BANK_USED(bank)) |
501 | pm_runtime_get_sync(bank->dev); | |
8d4c277e | 502 | |
4b25408f TL |
503 | #ifdef CONFIG_ARCH_OMAP1 |
504 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 505 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
506 | #endif |
507 | ||
508 | if (!gpio) | |
a0e827c6 | 509 | gpio = omap_irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 | 510 | |
e5c56ed3 | 511 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 512 | return -EINVAL; |
e5c56ed3 | 513 | |
9ea14d8c TKD |
514 | if (!bank->regs->leveldetect0 && |
515 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
516 | return -EINVAL; |
517 | ||
a6472533 | 518 | spin_lock_irqsave(&bank->lock, flags); |
fac7fa16 | 519 | offset = GPIO_INDEX(bank, gpio); |
a0e827c6 | 520 | retval = omap_set_gpio_triggering(bank, offset, type); |
3d009c8c | 521 | omap_gpio_init_irq(bank, gpio, offset); |
b2b20045 | 522 | if (!omap_gpio_is_input(bank, offset)) { |
fac7fa16 JMC |
523 | spin_unlock_irqrestore(&bank->lock, flags); |
524 | return -EINVAL; | |
525 | } | |
a6472533 | 526 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
527 | |
528 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 529 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 530 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 531 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 532 | |
92105bb7 | 533 | return retval; |
5e1c5ff4 TL |
534 | } |
535 | ||
a0e827c6 | 536 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 537 | { |
92105bb7 | 538 | void __iomem *reg = bank->base; |
5e1c5ff4 | 539 | |
eef4bec7 | 540 | reg += bank->regs->irqstatus; |
661553b9 | 541 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
542 | |
543 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
544 | if (bank->regs->irqstatus2) { |
545 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 546 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 547 | } |
bedfd154 RQ |
548 | |
549 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 550 | readl_relaxed(reg); |
5e1c5ff4 TL |
551 | } |
552 | ||
a0e827c6 | 553 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 554 | { |
a0e827c6 | 555 | omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
556 | } |
557 | ||
a0e827c6 | 558 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
559 | { |
560 | void __iomem *reg = bank->base; | |
99c47707 | 561 | u32 l; |
b1e9fec2 | 562 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 563 | |
28f3b5a0 | 564 | reg += bank->regs->irqenable; |
661553b9 | 565 | l = readl_relaxed(reg); |
28f3b5a0 | 566 | if (bank->regs->irqenable_inv) |
99c47707 ID |
567 | l = ~l; |
568 | l &= mask; | |
569 | return l; | |
ea6dedd7 ID |
570 | } |
571 | ||
a0e827c6 | 572 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 573 | { |
92105bb7 | 574 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
575 | u32 l; |
576 | ||
28f3b5a0 KH |
577 | if (bank->regs->set_irqenable) { |
578 | reg += bank->regs->set_irqenable; | |
579 | l = gpio_mask; | |
2a900eb7 | 580 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
581 | } else { |
582 | reg += bank->regs->irqenable; | |
661553b9 | 583 | l = readl_relaxed(reg); |
28f3b5a0 KH |
584 | if (bank->regs->irqenable_inv) |
585 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
586 | else |
587 | l |= gpio_mask; | |
2a900eb7 | 588 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
589 | } |
590 | ||
661553b9 | 591 | writel_relaxed(l, reg); |
28f3b5a0 KH |
592 | } |
593 | ||
a0e827c6 | 594 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
595 | { |
596 | void __iomem *reg = bank->base; | |
597 | u32 l; | |
598 | ||
599 | if (bank->regs->clr_irqenable) { | |
600 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 601 | l = gpio_mask; |
2a900eb7 | 602 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
603 | } else { |
604 | reg += bank->regs->irqenable; | |
661553b9 | 605 | l = readl_relaxed(reg); |
28f3b5a0 | 606 | if (bank->regs->irqenable_inv) |
56739a69 | 607 | l |= gpio_mask; |
92105bb7 | 608 | else |
28f3b5a0 | 609 | l &= ~gpio_mask; |
2a900eb7 | 610 | bank->context.irqenable1 = l; |
5e1c5ff4 | 611 | } |
28f3b5a0 | 612 | |
661553b9 | 613 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
614 | } |
615 | ||
a0e827c6 JMC |
616 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio, |
617 | int enable) | |
5e1c5ff4 | 618 | { |
8276536c | 619 | if (enable) |
a0e827c6 | 620 | omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
8276536c | 621 | else |
a0e827c6 | 622 | omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
623 | } |
624 | ||
92105bb7 TL |
625 | /* |
626 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
627 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
628 | * to the target, system will wake up always on GPIO events. While | |
629 | * system is running all registered GPIO interrupts need to have wake-up | |
630 | * enabled. When system is suspended, only selected GPIO interrupts need | |
631 | * to have wake-up enabled. | |
632 | */ | |
a0e827c6 | 633 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) |
92105bb7 | 634 | { |
f64ad1a0 KH |
635 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
636 | unsigned long flags; | |
a6472533 | 637 | |
f64ad1a0 | 638 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 639 | dev_err(bank->dev, |
f64ad1a0 | 640 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
641 | return -EINVAL; |
642 | } | |
f64ad1a0 KH |
643 | |
644 | spin_lock_irqsave(&bank->lock, flags); | |
645 | if (enable) | |
0aa27273 | 646 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 647 | else |
0aa27273 | 648 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 649 | |
661553b9 | 650 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
651 | spin_unlock_irqrestore(&bank->lock, flags); |
652 | ||
653 | return 0; | |
92105bb7 TL |
654 | } |
655 | ||
a0e827c6 | 656 | static void omap_reset_gpio(struct gpio_bank *bank, int gpio) |
4196dd6b | 657 | { |
a0e827c6 JMC |
658 | omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
659 | omap_set_gpio_irqenable(bank, gpio, 0); | |
660 | omap_clear_gpio_irqstatus(bank, gpio); | |
661 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); | |
4a58d229 | 662 | omap_clear_gpio_debounce(bank, GPIO_INDEX(bank, gpio)); |
4196dd6b TL |
663 | } |
664 | ||
92105bb7 | 665 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 666 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 667 | { |
a0e827c6 JMC |
668 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
669 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
92105bb7 | 670 | |
a0e827c6 | 671 | return omap_set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
672 | } |
673 | ||
3ff164e1 | 674 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 675 | { |
3ff164e1 | 676 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 677 | unsigned long flags; |
52e31344 | 678 | |
55b93c32 TKD |
679 | /* |
680 | * If this is the first gpio_request for the bank, | |
681 | * enable the bank module. | |
682 | */ | |
fa365e4d | 683 | if (!BANK_USED(bank)) |
55b93c32 | 684 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 685 | |
55b93c32 | 686 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 687 | /* Set trigger to none. You need to enable the desired trigger with |
fac7fa16 JMC |
688 | * request_irq() or set_irq_type(). Only do this if the IRQ line has |
689 | * not already been requested. | |
4196dd6b | 690 | */ |
fac7fa16 | 691 | if (!LINE_USED(bank->irq_usage, offset)) { |
a0e827c6 JMC |
692 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
693 | omap_enable_gpio_module(bank, offset); | |
5e1c5ff4 | 694 | } |
b1e9fec2 | 695 | bank->mod_usage |= BIT(offset); |
a6472533 | 696 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
697 | |
698 | return 0; | |
699 | } | |
700 | ||
3ff164e1 | 701 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 702 | { |
3ff164e1 | 703 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 704 | unsigned long flags; |
5e1c5ff4 | 705 | |
a6472533 | 706 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 707 | bank->mod_usage &= ~(BIT(offset)); |
a0e827c6 JMC |
708 | omap_disable_gpio_module(bank, offset); |
709 | omap_reset_gpio(bank, bank->chip.base + offset); | |
a6472533 | 710 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
711 | |
712 | /* | |
713 | * If this is the last gpio to be freed in the bank, | |
714 | * disable the bank module. | |
715 | */ | |
fa365e4d | 716 | if (!BANK_USED(bank)) |
55b93c32 | 717 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
718 | } |
719 | ||
720 | /* | |
721 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
722 | * avoid missing GPIO interrupts for other lines in the bank. | |
723 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
724 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
725 | * If we wait to unmask individual GPIO lines in the bank after the | |
726 | * line's interrupt handler has been run, we may miss some nested | |
727 | * interrupts. | |
728 | */ | |
a0e827c6 | 729 | static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 730 | { |
92105bb7 | 731 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 732 | u32 isr; |
3513cdec | 733 | unsigned int bit; |
5e1c5ff4 | 734 | struct gpio_bank *bank; |
ea6dedd7 | 735 | int unmasked = 0; |
fb655f57 JMC |
736 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
737 | struct gpio_chip *chip = irq_get_handler_data(irq); | |
5e1c5ff4 | 738 | |
fb655f57 | 739 | chained_irq_enter(irqchip, desc); |
5e1c5ff4 | 740 | |
fb655f57 | 741 | bank = container_of(chip, struct gpio_bank, chip); |
eef4bec7 | 742 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 743 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
744 | |
745 | if (WARN_ON(!isr_reg)) | |
746 | goto exit; | |
747 | ||
e83507b7 | 748 | while (1) { |
6e60e79a | 749 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 750 | u32 enabled; |
6e60e79a | 751 | |
a0e827c6 | 752 | enabled = omap_get_gpio_irqbank_mask(bank); |
661553b9 | 753 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 754 | |
9ea14d8c | 755 | if (bank->level_mask) |
b144ff6f | 756 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
757 | |
758 | /* clear edge sensitive interrupts before handler(s) are | |
759 | called so that we don't miss any interrupt occurred while | |
760 | executing them */ | |
a0e827c6 JMC |
761 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
762 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
763 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); | |
6e60e79a TL |
764 | |
765 | /* if there is only edge sensitive GPIO pin interrupts | |
766 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
767 | if (!level_mask && !unmasked) { |
768 | unmasked = 1; | |
fb655f57 | 769 | chained_irq_exit(irqchip, desc); |
ea6dedd7 | 770 | } |
92105bb7 TL |
771 | |
772 | if (!isr) | |
773 | break; | |
774 | ||
3513cdec JH |
775 | while (isr) { |
776 | bit = __ffs(isr); | |
b1e9fec2 | 777 | isr &= ~(BIT(bit)); |
25db711d | 778 | |
4318f36b CM |
779 | /* |
780 | * Some chips can't respond to both rising and falling | |
781 | * at the same time. If this irq was requested with | |
782 | * both flags, we need to flip the ICR data for the IRQ | |
783 | * to respond to the IRQ for the opposite direction. | |
784 | * This will be indicated in the bank toggle_mask. | |
785 | */ | |
b1e9fec2 | 786 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 787 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 788 | |
fb655f57 JMC |
789 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
790 | bit)); | |
92105bb7 | 791 | } |
1a8bfa1e | 792 | } |
ea6dedd7 ID |
793 | /* if bank has any level sensitive GPIO pin interrupt |
794 | configured, we must unmask the bank interrupt only after | |
795 | handler(s) are executed in order to avoid spurious bank | |
796 | interrupt */ | |
b1cc4c55 | 797 | exit: |
ea6dedd7 | 798 | if (!unmasked) |
fb655f57 | 799 | chained_irq_exit(irqchip, desc); |
55b93c32 | 800 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
801 | } |
802 | ||
3d009c8c TL |
803 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
804 | { | |
805 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
806 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
807 | unsigned long flags; | |
808 | unsigned offset = GPIO_INDEX(bank, gpio); | |
809 | ||
810 | if (!BANK_USED(bank)) | |
811 | pm_runtime_get_sync(bank->dev); | |
812 | ||
813 | spin_lock_irqsave(&bank->lock, flags); | |
814 | omap_gpio_init_irq(bank, gpio, offset); | |
815 | spin_unlock_irqrestore(&bank->lock, flags); | |
816 | omap_gpio_unmask_irq(d); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
a0e827c6 | 821 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 822 | { |
a0e827c6 JMC |
823 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
824 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
85ec7b97 | 825 | unsigned long flags; |
fa365e4d | 826 | unsigned offset = GPIO_INDEX(bank, gpio); |
4196dd6b | 827 | |
85ec7b97 | 828 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 829 | bank->irq_usage &= ~(BIT(offset)); |
a0e827c6 JMC |
830 | omap_disable_gpio_module(bank, offset); |
831 | omap_reset_gpio(bank, gpio); | |
85ec7b97 | 832 | spin_unlock_irqrestore(&bank->lock, flags); |
fac7fa16 JMC |
833 | |
834 | /* | |
835 | * If this is the last IRQ to be freed in the bank, | |
836 | * disable the bank module. | |
837 | */ | |
838 | if (!BANK_USED(bank)) | |
839 | pm_runtime_put(bank->dev); | |
4196dd6b TL |
840 | } |
841 | ||
a0e827c6 | 842 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 843 | { |
a0e827c6 JMC |
844 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
845 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
5e1c5ff4 | 846 | |
a0e827c6 | 847 | omap_clear_gpio_irqstatus(bank, gpio); |
5e1c5ff4 TL |
848 | } |
849 | ||
a0e827c6 | 850 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 851 | { |
a0e827c6 JMC |
852 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
853 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
85ec7b97 | 854 | unsigned long flags; |
5e1c5ff4 | 855 | |
85ec7b97 | 856 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 JMC |
857 | omap_set_gpio_irqenable(bank, gpio, 0); |
858 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); | |
85ec7b97 | 859 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
860 | } |
861 | ||
a0e827c6 | 862 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 863 | { |
a0e827c6 JMC |
864 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
865 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
129fd223 | 866 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 867 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 868 | unsigned long flags; |
55b6019a | 869 | |
85ec7b97 | 870 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 871 | if (trigger) |
a0e827c6 | 872 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
873 | |
874 | /* For level-triggered GPIOs, the clearing must be done after | |
875 | * the HW source is cleared, thus after the handler has run */ | |
876 | if (bank->level_mask & irq_mask) { | |
a0e827c6 JMC |
877 | omap_set_gpio_irqenable(bank, gpio, 0); |
878 | omap_clear_gpio_irqstatus(bank, gpio); | |
b144ff6f | 879 | } |
5e1c5ff4 | 880 | |
a0e827c6 | 881 | omap_set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 882 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
883 | } |
884 | ||
e5c56ed3 DB |
885 | /*---------------------------------------------------------------------*/ |
886 | ||
79ee031f | 887 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 888 | { |
79ee031f | 889 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 890 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
891 | void __iomem *mask_reg = bank->base + |
892 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 893 | unsigned long flags; |
11a78b79 | 894 | |
a6472533 | 895 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 896 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 897 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
898 | |
899 | return 0; | |
900 | } | |
901 | ||
79ee031f | 902 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 903 | { |
79ee031f | 904 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 905 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
906 | void __iomem *mask_reg = bank->base + |
907 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 908 | unsigned long flags; |
11a78b79 | 909 | |
a6472533 | 910 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 911 | writel_relaxed(bank->context.wake_en, mask_reg); |
a6472533 | 912 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
913 | |
914 | return 0; | |
915 | } | |
916 | ||
47145210 | 917 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
918 | .suspend_noirq = omap_mpuio_suspend_noirq, |
919 | .resume_noirq = omap_mpuio_resume_noirq, | |
920 | }; | |
921 | ||
3c437ffd | 922 | /* use platform_driver for this. */ |
11a78b79 | 923 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
924 | .driver = { |
925 | .name = "mpuio", | |
79ee031f | 926 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
927 | }, |
928 | }; | |
929 | ||
930 | static struct platform_device omap_mpuio_device = { | |
931 | .name = "mpuio", | |
932 | .id = -1, | |
933 | .dev = { | |
934 | .driver = &omap_mpuio_driver.driver, | |
935 | } | |
936 | /* could list the /proc/iomem resources */ | |
937 | }; | |
938 | ||
a0e827c6 | 939 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 940 | { |
77640aab | 941 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 942 | |
11a78b79 DB |
943 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
944 | (void) platform_device_register(&omap_mpuio_device); | |
945 | } | |
946 | ||
e5c56ed3 | 947 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 948 | |
a0e827c6 | 949 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
950 | { |
951 | struct gpio_bank *bank; | |
952 | unsigned long flags; | |
953 | void __iomem *reg; | |
954 | int dir; | |
955 | ||
956 | bank = container_of(chip, struct gpio_bank, chip); | |
957 | reg = bank->base + bank->regs->direction; | |
958 | spin_lock_irqsave(&bank->lock, flags); | |
959 | dir = !!(readl_relaxed(reg) & BIT(offset)); | |
960 | spin_unlock_irqrestore(&bank->lock, flags); | |
961 | return dir; | |
962 | } | |
963 | ||
a0e827c6 | 964 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
965 | { |
966 | struct gpio_bank *bank; | |
967 | unsigned long flags; | |
968 | ||
969 | bank = container_of(chip, struct gpio_bank, chip); | |
970 | spin_lock_irqsave(&bank->lock, flags); | |
a0e827c6 | 971 | omap_set_gpio_direction(bank, offset, 1); |
52e31344 DB |
972 | spin_unlock_irqrestore(&bank->lock, flags); |
973 | return 0; | |
974 | } | |
975 | ||
a0e827c6 | 976 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 977 | { |
b37c45b8 | 978 | struct gpio_bank *bank; |
b37c45b8 | 979 | |
a8be8daf | 980 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 981 | |
b2b20045 | 982 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 983 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 984 | else |
a0e827c6 | 985 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
986 | } |
987 | ||
a0e827c6 | 988 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
989 | { |
990 | struct gpio_bank *bank; | |
991 | unsigned long flags; | |
992 | ||
993 | bank = container_of(chip, struct gpio_bank, chip); | |
994 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 995 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 996 | omap_set_gpio_direction(bank, offset, 0); |
52e31344 | 997 | spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 998 | return 0; |
52e31344 DB |
999 | } |
1000 | ||
a0e827c6 JMC |
1001 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1002 | unsigned debounce) | |
168ef3d9 FB |
1003 | { |
1004 | struct gpio_bank *bank; | |
1005 | unsigned long flags; | |
1006 | ||
1007 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 1008 | |
168ef3d9 | 1009 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 1010 | omap2_set_gpio_debounce(bank, offset, debounce); |
168ef3d9 FB |
1011 | spin_unlock_irqrestore(&bank->lock, flags); |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
a0e827c6 | 1016 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1017 | { |
1018 | struct gpio_bank *bank; | |
1019 | unsigned long flags; | |
1020 | ||
1021 | bank = container_of(chip, struct gpio_bank, chip); | |
1022 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1023 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1024 | spin_unlock_irqrestore(&bank->lock, flags); |
1025 | } | |
1026 | ||
1027 | /*---------------------------------------------------------------------*/ | |
1028 | ||
9a748053 | 1029 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1030 | { |
e5ff4440 | 1031 | static bool called; |
9f7065da TL |
1032 | u32 rev; |
1033 | ||
e5ff4440 | 1034 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1035 | return; |
1036 | ||
661553b9 | 1037 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1038 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1039 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1040 | |
1041 | called = true; | |
9f7065da TL |
1042 | } |
1043 | ||
03e128ca | 1044 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1045 | { |
ab985f0f TKD |
1046 | void __iomem *base = bank->base; |
1047 | u32 l = 0xffffffff; | |
2fae7fbe | 1048 | |
ab985f0f TKD |
1049 | if (bank->width == 16) |
1050 | l = 0xffff; | |
1051 | ||
d0d665a8 | 1052 | if (bank->is_mpuio) { |
661553b9 | 1053 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1054 | return; |
2fae7fbe | 1055 | } |
ab985f0f | 1056 | |
a0e827c6 JMC |
1057 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1058 | bank->regs->irqenable_inv); | |
1059 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1060 | !bank->regs->irqenable_inv); | |
ab985f0f | 1061 | if (bank->regs->debounce_en) |
661553b9 | 1062 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1063 | |
2dc983c5 | 1064 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1065 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1066 | /* Initialize interface clk ungated, module enabled */ |
1067 | if (bank->regs->ctrl) | |
661553b9 | 1068 | writel_relaxed(0, base + bank->regs->ctrl); |
34672013 TKD |
1069 | |
1070 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1071 | if (IS_ERR(bank->dbck)) | |
1072 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1073 | } |
1074 | ||
3836309d | 1075 | static void |
f8b46b58 KH |
1076 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1077 | unsigned int num) | |
1078 | { | |
1079 | struct irq_chip_generic *gc; | |
1080 | struct irq_chip_type *ct; | |
1081 | ||
1082 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1083 | handle_simple_irq); | |
83233749 TP |
1084 | if (!gc) { |
1085 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1086 | return; | |
1087 | } | |
1088 | ||
f8b46b58 KH |
1089 | ct = gc->chip_types; |
1090 | ||
1091 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1092 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1093 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
a0e827c6 | 1094 | ct->chip.irq_set_type = omap_gpio_irq_type; |
6ed87c5b TKD |
1095 | |
1096 | if (bank->regs->wkup_en) | |
a0e827c6 | 1097 | ct->chip.irq_set_wake = omap_gpio_wake_enable; |
f8b46b58 KH |
1098 | |
1099 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1100 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1101 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1102 | } | |
1103 | ||
46824e22 | 1104 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1105 | { |
77640aab | 1106 | int j; |
2fae7fbe | 1107 | static int gpio; |
fb655f57 | 1108 | int irq_base = 0; |
6ef7f385 | 1109 | int ret; |
2fae7fbe | 1110 | |
2fae7fbe VC |
1111 | /* |
1112 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1113 | * over to the generic ones | |
1114 | */ | |
1115 | bank->chip.request = omap_gpio_request; | |
1116 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1117 | bank->chip.get_direction = omap_gpio_get_direction; |
1118 | bank->chip.direction_input = omap_gpio_input; | |
1119 | bank->chip.get = omap_gpio_get; | |
1120 | bank->chip.direction_output = omap_gpio_output; | |
1121 | bank->chip.set_debounce = omap_gpio_debounce; | |
1122 | bank->chip.set = omap_gpio_set; | |
d0d665a8 | 1123 | if (bank->is_mpuio) { |
2fae7fbe | 1124 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1125 | if (bank->regs->wkup_en) |
1126 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1127 | bank->chip.base = OMAP_MPUIO(0); |
1128 | } else { | |
1129 | bank->chip.label = "gpio"; | |
1130 | bank->chip.base = gpio; | |
d5f46247 | 1131 | gpio += bank->width; |
2fae7fbe | 1132 | } |
d5f46247 | 1133 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1134 | |
6ef7f385 JMC |
1135 | ret = gpiochip_add(&bank->chip); |
1136 | if (ret) { | |
fb655f57 | 1137 | dev_err(bank->dev, "Could not register gpio chip %d\n", ret); |
6ef7f385 JMC |
1138 | return ret; |
1139 | } | |
2fae7fbe | 1140 | |
fb655f57 JMC |
1141 | #ifdef CONFIG_ARCH_OMAP1 |
1142 | /* | |
1143 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1144 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1145 | */ | |
1146 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1147 | if (irq_base < 0) { | |
1148 | dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); | |
1149 | return -ENODEV; | |
1150 | } | |
1151 | #endif | |
1152 | ||
46824e22 | 1153 | ret = gpiochip_irqchip_add(&bank->chip, irqc, |
a0e827c6 | 1154 | irq_base, omap_gpio_irq_handler, |
fb655f57 JMC |
1155 | IRQ_TYPE_NONE); |
1156 | ||
1157 | if (ret) { | |
1158 | dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); | |
da26d5d8 | 1159 | gpiochip_remove(&bank->chip); |
fb655f57 JMC |
1160 | return -ENODEV; |
1161 | } | |
1162 | ||
46824e22 | 1163 | gpiochip_set_chained_irqchip(&bank->chip, irqc, |
a0e827c6 | 1164 | bank->irq, omap_gpio_irq_handler); |
fb655f57 | 1165 | |
ede4d7a5 | 1166 | for (j = 0; j < bank->width; j++) { |
fb655f57 | 1167 | int irq = irq_find_mapping(bank->chip.irqdomain, j); |
d0d665a8 | 1168 | if (bank->is_mpuio) { |
ede4d7a5 | 1169 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
fb655f57 JMC |
1170 | irq_set_chip_and_handler(irq, NULL, NULL); |
1171 | set_irq_flags(irq, 0); | |
f8b46b58 | 1172 | } |
2fae7fbe | 1173 | } |
fb655f57 JMC |
1174 | |
1175 | return 0; | |
2fae7fbe VC |
1176 | } |
1177 | ||
384ebe1c BC |
1178 | static const struct of_device_id omap_gpio_match[]; |
1179 | ||
3836309d | 1180 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1181 | { |
862ff640 | 1182 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1183 | struct device_node *node = dev->of_node; |
1184 | const struct of_device_id *match; | |
f6817a2c | 1185 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1186 | struct resource *res; |
5e1c5ff4 | 1187 | struct gpio_bank *bank; |
46824e22 | 1188 | struct irq_chip *irqc; |
6ef7f385 | 1189 | int ret; |
5e1c5ff4 | 1190 | |
384ebe1c BC |
1191 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1192 | ||
e56aee18 | 1193 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1194 | if (!pdata) |
96751fcb | 1195 | return -EINVAL; |
5492fb1a | 1196 | |
086d585f | 1197 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1198 | if (!bank) { |
862ff640 | 1199 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1200 | return -ENOMEM; |
03e128ca | 1201 | } |
92105bb7 | 1202 | |
46824e22 NM |
1203 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1204 | if (!irqc) | |
1205 | return -ENOMEM; | |
1206 | ||
3d009c8c | 1207 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1208 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1209 | irqc->irq_ack = omap_gpio_ack_irq, | |
1210 | irqc->irq_mask = omap_gpio_mask_irq, | |
1211 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1212 | irqc->irq_set_type = omap_gpio_irq_type, | |
1213 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1214 | irqc->name = dev_name(&pdev->dev); | |
1215 | ||
77640aab VC |
1216 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1217 | if (unlikely(!res)) { | |
862ff640 | 1218 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1219 | return -ENODEV; |
44169075 | 1220 | } |
5e1c5ff4 | 1221 | |
77640aab | 1222 | bank->irq = res->start; |
862ff640 | 1223 | bank->dev = dev; |
fb655f57 | 1224 | bank->chip.dev = dev; |
77640aab | 1225 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1226 | bank->stride = pdata->bank_stride; |
d5f46247 | 1227 | bank->width = pdata->bank_width; |
d0d665a8 | 1228 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1229 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1230 | bank->regs = pdata->regs; |
384ebe1c BC |
1231 | #ifdef CONFIG_OF_GPIO |
1232 | bank->chip.of_node = of_node_get(node); | |
1233 | #endif | |
a2797bea JH |
1234 | if (node) { |
1235 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1236 | bank->loses_context = true; | |
1237 | } else { | |
1238 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1239 | |
1240 | if (bank->loses_context) | |
1241 | bank->get_context_loss_count = | |
1242 | pdata->get_context_loss_count; | |
384ebe1c BC |
1243 | } |
1244 | ||
fa87931a | 1245 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1246 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1247 | else |
a0e827c6 | 1248 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1249 | |
77640aab | 1250 | spin_lock_init(&bank->lock); |
9f7065da | 1251 | |
77640aab VC |
1252 | /* Static mapping, never released */ |
1253 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1254 | bank->base = devm_ioremap_resource(dev, res); |
1255 | if (IS_ERR(bank->base)) { | |
fb655f57 | 1256 | irq_domain_remove(bank->chip.irqdomain); |
717f70e3 | 1257 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1258 | } |
1259 | ||
065cd795 TKD |
1260 | platform_set_drvdata(pdev, bank); |
1261 | ||
77640aab | 1262 | pm_runtime_enable(bank->dev); |
55b93c32 | 1263 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1264 | pm_runtime_get_sync(bank->dev); |
1265 | ||
d0d665a8 | 1266 | if (bank->is_mpuio) |
a0e827c6 | 1267 | omap_mpuio_init(bank); |
ab985f0f | 1268 | |
03e128ca | 1269 | omap_gpio_mod_init(bank); |
6ef7f385 | 1270 | |
46824e22 | 1271 | ret = omap_gpio_chip_init(bank, irqc); |
6ef7f385 JMC |
1272 | if (ret) |
1273 | return ret; | |
1274 | ||
9a748053 | 1275 | omap_gpio_show_rev(bank); |
9f7065da | 1276 | |
55b93c32 TKD |
1277 | pm_runtime_put(bank->dev); |
1278 | ||
03e128ca | 1279 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1280 | |
879fe324 | 1281 | return 0; |
5e1c5ff4 TL |
1282 | } |
1283 | ||
55b93c32 TKD |
1284 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1285 | ||
ecb2312f | 1286 | #if defined(CONFIG_PM) |
60a3437d | 1287 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1288 | |
2dc983c5 | 1289 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1290 | { |
2dc983c5 TKD |
1291 | struct platform_device *pdev = to_platform_device(dev); |
1292 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1293 | u32 l1 = 0, l2 = 0; | |
1294 | unsigned long flags; | |
68942edb | 1295 | u32 wake_low, wake_hi; |
8865b9b6 | 1296 | |
2dc983c5 | 1297 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1298 | |
1299 | /* | |
1300 | * Only edges can generate a wakeup event to the PRCM. | |
1301 | * | |
1302 | * Therefore, ensure any wake-up capable GPIOs have | |
1303 | * edge-detection enabled before going idle to ensure a wakeup | |
1304 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1305 | * NDA TRM 25.5.3.1) | |
1306 | * | |
1307 | * The normal values will be restored upon ->runtime_resume() | |
1308 | * by writing back the values saved in bank->context. | |
1309 | */ | |
1310 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1311 | if (wake_low) | |
661553b9 | 1312 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1313 | bank->base + bank->regs->fallingdetect); |
1314 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1315 | if (wake_hi) | |
661553b9 | 1316 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1317 | bank->base + bank->regs->risingdetect); |
1318 | ||
b3c64bc3 KH |
1319 | if (!bank->enabled_non_wakeup_gpios) |
1320 | goto update_gpio_context_count; | |
1321 | ||
2dc983c5 TKD |
1322 | if (bank->power_mode != OFF_MODE) { |
1323 | bank->power_mode = 0; | |
41d87cbd | 1324 | goto update_gpio_context_count; |
2dc983c5 TKD |
1325 | } |
1326 | /* | |
1327 | * If going to OFF, remove triggering for all | |
1328 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1329 | * generated. See OMAP2420 Errata item 1.101. | |
1330 | */ | |
661553b9 | 1331 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1332 | bank->regs->datain); |
c6f31c9e TKD |
1333 | l1 = bank->context.fallingdetect; |
1334 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1335 | |
2dc983c5 TKD |
1336 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1337 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1338 | |
661553b9 VK |
1339 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1340 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1341 | |
2dc983c5 | 1342 | bank->workaround_enabled = true; |
3f1686a9 | 1343 | |
41d87cbd | 1344 | update_gpio_context_count: |
2dc983c5 TKD |
1345 | if (bank->get_context_loss_count) |
1346 | bank->context_loss_count = | |
60a3437d TKD |
1347 | bank->get_context_loss_count(bank->dev); |
1348 | ||
a0e827c6 | 1349 | omap_gpio_dbck_disable(bank); |
2dc983c5 | 1350 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1351 | |
2dc983c5 | 1352 | return 0; |
3ac4fa99 JY |
1353 | } |
1354 | ||
352a2d5b JH |
1355 | static void omap_gpio_init_context(struct gpio_bank *p); |
1356 | ||
2dc983c5 | 1357 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1358 | { |
2dc983c5 TKD |
1359 | struct platform_device *pdev = to_platform_device(dev); |
1360 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1361 | u32 l = 0, gen, gen0, gen1; |
1362 | unsigned long flags; | |
a2797bea | 1363 | int c; |
8865b9b6 | 1364 | |
2dc983c5 | 1365 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1366 | |
1367 | /* | |
1368 | * On the first resume during the probe, the context has not | |
1369 | * been initialised and so initialise it now. Also initialise | |
1370 | * the context loss count. | |
1371 | */ | |
1372 | if (bank->loses_context && !bank->context_valid) { | |
1373 | omap_gpio_init_context(bank); | |
1374 | ||
1375 | if (bank->get_context_loss_count) | |
1376 | bank->context_loss_count = | |
1377 | bank->get_context_loss_count(bank->dev); | |
1378 | } | |
1379 | ||
a0e827c6 | 1380 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1381 | |
1382 | /* | |
1383 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1384 | * GPIOs were set to edge trigger also in order to be able to | |
1385 | * generate a PRCM wakeup. Here we restore the | |
1386 | * pre-runtime_suspend() values for edge triggering. | |
1387 | */ | |
661553b9 | 1388 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1389 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1390 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1391 | bank->base + bank->regs->risingdetect); |
1392 | ||
a2797bea JH |
1393 | if (bank->loses_context) { |
1394 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1395 | omap_gpio_restore_context(bank); |
1396 | } else { | |
a2797bea JH |
1397 | c = bank->get_context_loss_count(bank->dev); |
1398 | if (c != bank->context_loss_count) { | |
1399 | omap_gpio_restore_context(bank); | |
1400 | } else { | |
1401 | spin_unlock_irqrestore(&bank->lock, flags); | |
1402 | return 0; | |
1403 | } | |
60a3437d | 1404 | } |
2dc983c5 | 1405 | } |
43ffcd9a | 1406 | |
1b128703 TKD |
1407 | if (!bank->workaround_enabled) { |
1408 | spin_unlock_irqrestore(&bank->lock, flags); | |
1409 | return 0; | |
1410 | } | |
1411 | ||
661553b9 | 1412 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1413 | |
2dc983c5 TKD |
1414 | /* |
1415 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1416 | * state. If so, generate an IRQ by software. This is | |
1417 | * horribly racy, but it's the best we can do to work around | |
1418 | * this silicon bug. | |
1419 | */ | |
1420 | l ^= bank->saved_datain; | |
1421 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1422 | |
2dc983c5 TKD |
1423 | /* |
1424 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1425 | * configured with falling edge only; and vice versa. | |
1426 | */ | |
c6f31c9e | 1427 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1428 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1429 | |
c6f31c9e | 1430 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1431 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1432 | |
2dc983c5 | 1433 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1434 | gen = l & (~(bank->context.fallingdetect) & |
1435 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1436 | /* Consider all GPIO IRQs needed to be updated */ |
1437 | gen |= gen0 | gen1; | |
82dbb9d3 | 1438 | |
2dc983c5 TKD |
1439 | if (gen) { |
1440 | u32 old0, old1; | |
82dbb9d3 | 1441 | |
661553b9 VK |
1442 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1443 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1444 | |
4e962e89 | 1445 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1446 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1447 | bank->regs->leveldetect0); |
661553b9 | 1448 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1449 | bank->regs->leveldetect1); |
2dc983c5 | 1450 | } |
9ea14d8c | 1451 | |
4e962e89 | 1452 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1453 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1454 | bank->regs->leveldetect0); |
661553b9 | 1455 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1456 | bank->regs->leveldetect1); |
3ac4fa99 | 1457 | } |
661553b9 VK |
1458 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1459 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1460 | } |
1461 | ||
1462 | bank->workaround_enabled = false; | |
1463 | spin_unlock_irqrestore(&bank->lock, flags); | |
1464 | ||
1465 | return 0; | |
1466 | } | |
ecb2312f | 1467 | #endif /* CONFIG_PM */ |
2dc983c5 TKD |
1468 | |
1469 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1470 | { | |
1471 | struct gpio_bank *bank; | |
1472 | ||
1473 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1474 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1475 | continue; |
1476 | ||
1477 | bank->power_mode = pwr_mode; | |
1478 | ||
2dc983c5 TKD |
1479 | pm_runtime_put_sync_suspend(bank->dev); |
1480 | } | |
1481 | } | |
1482 | ||
1483 | void omap2_gpio_resume_after_idle(void) | |
1484 | { | |
1485 | struct gpio_bank *bank; | |
1486 | ||
1487 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1488 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1489 | continue; |
1490 | ||
2dc983c5 | 1491 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1492 | } |
3ac4fa99 JY |
1493 | } |
1494 | ||
ecb2312f | 1495 | #if defined(CONFIG_PM) |
352a2d5b JH |
1496 | static void omap_gpio_init_context(struct gpio_bank *p) |
1497 | { | |
1498 | struct omap_gpio_reg_offs *regs = p->regs; | |
1499 | void __iomem *base = p->base; | |
1500 | ||
661553b9 VK |
1501 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1502 | p->context.oe = readl_relaxed(base + regs->direction); | |
1503 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1504 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1505 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1506 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1507 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1508 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1509 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1510 | |
1511 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1512 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1513 | else |
661553b9 | 1514 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1515 | |
1516 | p->context_valid = true; | |
1517 | } | |
1518 | ||
60a3437d | 1519 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1520 | { |
661553b9 | 1521 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1522 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1523 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1524 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1525 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1526 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1527 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1528 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1529 | bank->base + bank->regs->risingdetect); |
661553b9 | 1530 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1531 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1532 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1533 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1534 | bank->base + bank->regs->set_dataout); |
1535 | else | |
661553b9 | 1536 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1537 | bank->base + bank->regs->dataout); |
661553b9 | 1538 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1539 | |
ae547354 | 1540 | if (bank->dbck_enable_mask) { |
661553b9 | 1541 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1542 | bank->regs->debounce); |
661553b9 | 1543 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1544 | bank->base + bank->regs->debounce_en); |
1545 | } | |
ba805be5 | 1546 | |
661553b9 | 1547 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1548 | bank->base + bank->regs->irqenable); |
661553b9 | 1549 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1550 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1551 | } |
ecb2312f | 1552 | #endif /* CONFIG_PM */ |
55b93c32 | 1553 | #else |
2dc983c5 TKD |
1554 | #define omap_gpio_runtime_suspend NULL |
1555 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1556 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1557 | #endif |
1558 | ||
55b93c32 | 1559 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1560 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1561 | NULL) | |
55b93c32 TKD |
1562 | }; |
1563 | ||
384ebe1c BC |
1564 | #if defined(CONFIG_OF) |
1565 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1566 | .revision = OMAP24XX_GPIO_REVISION, | |
1567 | .direction = OMAP24XX_GPIO_OE, | |
1568 | .datain = OMAP24XX_GPIO_DATAIN, | |
1569 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1570 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1571 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1572 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1573 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1574 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1575 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1576 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1577 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1578 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1579 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1580 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1581 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1582 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1583 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1584 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1585 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1586 | }; | |
1587 | ||
1588 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1589 | .revision = OMAP4_GPIO_REVISION, | |
1590 | .direction = OMAP4_GPIO_OE, | |
1591 | .datain = OMAP4_GPIO_DATAIN, | |
1592 | .dataout = OMAP4_GPIO_DATAOUT, | |
1593 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1594 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1595 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1596 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1597 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1598 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1599 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1600 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1601 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1602 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1603 | .ctrl = OMAP4_GPIO_CTRL, | |
1604 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1605 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1606 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1607 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1608 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1609 | }; | |
1610 | ||
e9a65bb6 | 1611 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1612 | .regs = &omap2_gpio_regs, |
1613 | .bank_width = 32, | |
1614 | .dbck_flag = false, | |
1615 | }; | |
1616 | ||
e9a65bb6 | 1617 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1618 | .regs = &omap2_gpio_regs, |
1619 | .bank_width = 32, | |
1620 | .dbck_flag = true, | |
1621 | }; | |
1622 | ||
e9a65bb6 | 1623 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1624 | .regs = &omap4_gpio_regs, |
1625 | .bank_width = 32, | |
1626 | .dbck_flag = true, | |
1627 | }; | |
1628 | ||
1629 | static const struct of_device_id omap_gpio_match[] = { | |
1630 | { | |
1631 | .compatible = "ti,omap4-gpio", | |
1632 | .data = &omap4_pdata, | |
1633 | }, | |
1634 | { | |
1635 | .compatible = "ti,omap3-gpio", | |
1636 | .data = &omap3_pdata, | |
1637 | }, | |
1638 | { | |
1639 | .compatible = "ti,omap2-gpio", | |
1640 | .data = &omap2_pdata, | |
1641 | }, | |
1642 | { }, | |
1643 | }; | |
1644 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1645 | #endif | |
1646 | ||
77640aab VC |
1647 | static struct platform_driver omap_gpio_driver = { |
1648 | .probe = omap_gpio_probe, | |
1649 | .driver = { | |
1650 | .name = "omap_gpio", | |
55b93c32 | 1651 | .pm = &gpio_pm_ops, |
384ebe1c | 1652 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1653 | }, |
1654 | }; | |
1655 | ||
5e1c5ff4 | 1656 | /* |
77640aab VC |
1657 | * gpio driver register needs to be done before |
1658 | * machine_init functions access gpio APIs. | |
1659 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1660 | */ |
77640aab | 1661 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1662 | { |
77640aab | 1663 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1664 | } |
77640aab | 1665 | postcore_initcall(omap_gpio_drv_reg); |