Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
55b93c32 | 24 | #include <linux/pm.h> |
5e1c5ff4 | 25 | |
a09e64fb | 26 | #include <mach/hardware.h> |
5e1c5ff4 | 27 | #include <asm/irq.h> |
a09e64fb | 28 | #include <mach/irqs.h> |
1bc857f7 | 29 | #include <asm/gpio.h> |
5e1c5ff4 TL |
30 | #include <asm/mach/irq.h> |
31 | ||
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
47 | }; | |
48 | ||
5e1c5ff4 | 49 | struct gpio_bank { |
03e128ca | 50 | struct list_head node; |
9f7065da | 51 | unsigned long pbase; |
92105bb7 | 52 | void __iomem *base; |
5e1c5ff4 TL |
53 | u16 irq; |
54 | u16 virtual_irq_start; | |
92105bb7 TL |
55 | u32 suspend_wakeup; |
56 | u32 saved_wakeup; | |
3ac4fa99 JY |
57 | u32 non_wakeup_gpios; |
58 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 59 | struct gpio_regs context; |
3ac4fa99 JY |
60 | u32 saved_datain; |
61 | u32 saved_fallingdetect; | |
62 | u32 saved_risingdetect; | |
b144ff6f | 63 | u32 level_mask; |
4318f36b | 64 | u32 toggle_mask; |
5e1c5ff4 | 65 | spinlock_t lock; |
52e31344 | 66 | struct gpio_chip chip; |
89db9482 | 67 | struct clk *dbck; |
058af1ea | 68 | u32 mod_usage; |
8865b9b6 | 69 | u32 dbck_enable_mask; |
77640aab | 70 | struct device *dev; |
d0d665a8 | 71 | bool is_mpuio; |
77640aab | 72 | bool dbck_flag; |
0cde8d03 | 73 | bool loses_context; |
5de62b86 | 74 | int stride; |
d5f46247 | 75 | u32 width; |
60a3437d | 76 | int context_loss_count; |
03e128ca | 77 | u16 id; |
2dc983c5 TKD |
78 | int power_mode; |
79 | bool workaround_enabled; | |
fa87931a KH |
80 | |
81 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 82 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
83 | |
84 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
85 | }; |
86 | ||
129fd223 KH |
87 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
88 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 89 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 TL |
90 | |
91 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
92 | { | |
92105bb7 | 93 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
94 | u32 l; |
95 | ||
fa87931a | 96 | reg += bank->regs->direction; |
5e1c5ff4 TL |
97 | l = __raw_readl(reg); |
98 | if (is_input) | |
99 | l |= 1 << gpio; | |
100 | else | |
101 | l &= ~(1 << gpio); | |
102 | __raw_writel(l, reg); | |
103 | } | |
104 | ||
fa87931a KH |
105 | |
106 | /* set data out value using dedicate set/clear register */ | |
107 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 108 | { |
92105bb7 | 109 | void __iomem *reg = bank->base; |
fa87931a | 110 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 111 | |
fa87931a KH |
112 | if (enable) |
113 | reg += bank->regs->set_dataout; | |
114 | else | |
115 | reg += bank->regs->clr_dataout; | |
5e1c5ff4 | 116 | |
5e1c5ff4 TL |
117 | __raw_writel(l, reg); |
118 | } | |
119 | ||
fa87931a KH |
120 | /* set data out value using mask register */ |
121 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 122 | { |
fa87931a KH |
123 | void __iomem *reg = bank->base + bank->regs->dataout; |
124 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
125 | u32 l; | |
5e1c5ff4 | 126 | |
fa87931a KH |
127 | l = __raw_readl(reg); |
128 | if (enable) | |
129 | l |= gpio_bit; | |
130 | else | |
131 | l &= ~gpio_bit; | |
5e1c5ff4 | 132 | __raw_writel(l, reg); |
5e1c5ff4 TL |
133 | } |
134 | ||
b37c45b8 | 135 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
b37c45b8 | 136 | { |
fa87931a | 137 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 138 | |
fa87931a | 139 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
5e1c5ff4 | 140 | } |
b37c45b8 | 141 | |
b37c45b8 RQ |
142 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
143 | { | |
fa87931a | 144 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 145 | |
129fd223 | 146 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
147 | } |
148 | ||
ece9528e KH |
149 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
150 | { | |
151 | int l = __raw_readl(base + reg); | |
152 | ||
153 | if (set) | |
154 | l |= mask; | |
155 | else | |
156 | l &= ~mask; | |
157 | ||
158 | __raw_writel(l, base + reg); | |
159 | } | |
92105bb7 | 160 | |
168ef3d9 FB |
161 | /** |
162 | * _set_gpio_debounce - low level gpio debounce time | |
163 | * @bank: the gpio bank we're acting upon | |
164 | * @gpio: the gpio number on this @gpio | |
165 | * @debounce: debounce time to use | |
166 | * | |
167 | * OMAP's debounce time is in 31us steps so we need | |
168 | * to convert and round up to the closest unit. | |
169 | */ | |
170 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
171 | unsigned debounce) | |
172 | { | |
9942da0e | 173 | void __iomem *reg; |
168ef3d9 FB |
174 | u32 val; |
175 | u32 l; | |
176 | ||
77640aab VC |
177 | if (!bank->dbck_flag) |
178 | return; | |
179 | ||
168ef3d9 FB |
180 | if (debounce < 32) |
181 | debounce = 0x01; | |
182 | else if (debounce > 7936) | |
183 | debounce = 0xff; | |
184 | else | |
185 | debounce = (debounce / 0x1f) - 1; | |
186 | ||
129fd223 | 187 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 188 | |
9942da0e | 189 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
190 | __raw_writel(debounce, reg); |
191 | ||
9942da0e | 192 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
193 | val = __raw_readl(reg); |
194 | ||
195 | if (debounce) { | |
196 | val |= l; | |
77640aab | 197 | clk_enable(bank->dbck); |
168ef3d9 FB |
198 | } else { |
199 | val &= ~l; | |
77640aab | 200 | clk_disable(bank->dbck); |
168ef3d9 | 201 | } |
f7ec0b0b | 202 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
203 | |
204 | __raw_writel(val, reg); | |
205 | } | |
206 | ||
5e571f38 | 207 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
5eb3bb9c | 208 | int trigger) |
5e1c5ff4 | 209 | { |
3ac4fa99 | 210 | void __iomem *base = bank->base; |
92105bb7 TL |
211 | u32 gpio_bit = 1 << gpio; |
212 | ||
5e571f38 TKD |
213 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
214 | trigger & IRQ_TYPE_LEVEL_LOW); | |
215 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
216 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
217 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
218 | trigger & IRQ_TYPE_EDGE_RISING); | |
219 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
220 | trigger & IRQ_TYPE_EDGE_FALLING); | |
221 | ||
222 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) | |
223 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); | |
224 | ||
55b220ca | 225 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
226 | if (!bank->regs->irqctrl) { |
227 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
228 | if (bank->non_wakeup_gpios) { | |
229 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
230 | goto exit; | |
231 | } | |
232 | ||
699117a6 CW |
233 | /* |
234 | * Log the edge gpio and manually trigger the IRQ | |
235 | * after resume if the input level changes | |
236 | * to avoid irq lost during PER RET/OFF mode | |
237 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
238 | */ | |
239 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
240 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
241 | else | |
242 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
243 | } | |
5eb3bb9c | 244 | |
5e571f38 | 245 | exit: |
9ea14d8c TKD |
246 | bank->level_mask = |
247 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
248 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
249 | } |
250 | ||
9198bcd3 | 251 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
252 | /* |
253 | * This only applies to chips that can't do both rising and falling edge | |
254 | * detection at once. For all other chips, this function is a noop. | |
255 | */ | |
256 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
257 | { | |
258 | void __iomem *reg = bank->base; | |
259 | u32 l = 0; | |
260 | ||
5e571f38 | 261 | if (!bank->regs->irqctrl) |
4318f36b | 262 | return; |
5e571f38 TKD |
263 | |
264 | reg += bank->regs->irqctrl; | |
4318f36b CM |
265 | |
266 | l = __raw_readl(reg); | |
267 | if ((l >> gpio) & 1) | |
268 | l &= ~(1 << gpio); | |
269 | else | |
270 | l |= 1 << gpio; | |
271 | ||
272 | __raw_writel(l, reg); | |
273 | } | |
5e571f38 TKD |
274 | #else |
275 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 276 | #endif |
4318f36b | 277 | |
92105bb7 TL |
278 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
279 | { | |
280 | void __iomem *reg = bank->base; | |
5e571f38 | 281 | void __iomem *base = bank->base; |
92105bb7 | 282 | u32 l = 0; |
5e1c5ff4 | 283 | |
5e571f38 TKD |
284 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
285 | set_gpio_trigger(bank, gpio, trigger); | |
286 | } else if (bank->regs->irqctrl) { | |
287 | reg += bank->regs->irqctrl; | |
288 | ||
5e1c5ff4 | 289 | l = __raw_readl(reg); |
29501577 | 290 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 291 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 292 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 293 | l |= 1 << gpio; |
6cab4860 | 294 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 295 | l &= ~(1 << gpio); |
92105bb7 | 296 | else |
5e571f38 TKD |
297 | return -EINVAL; |
298 | ||
299 | __raw_writel(l, reg); | |
300 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 301 | if (gpio & 0x08) |
5e571f38 | 302 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 303 | else |
5e571f38 TKD |
304 | reg += bank->regs->edgectrl1; |
305 | ||
5e1c5ff4 TL |
306 | gpio &= 0x07; |
307 | l = __raw_readl(reg); | |
308 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 309 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 310 | l |= 2 << (gpio << 1); |
6cab4860 | 311 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 312 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
313 | |
314 | /* Enable wake-up during idle for dynamic tick */ | |
315 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
316 | __raw_writel(l, reg); | |
5e1c5ff4 | 317 | } |
92105bb7 | 318 | return 0; |
5e1c5ff4 TL |
319 | } |
320 | ||
e9191028 | 321 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
322 | { |
323 | struct gpio_bank *bank; | |
92105bb7 TL |
324 | unsigned gpio; |
325 | int retval; | |
a6472533 | 326 | unsigned long flags; |
92105bb7 | 327 | |
e9191028 LB |
328 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
329 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 330 | else |
e9191028 | 331 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 | 332 | |
e5c56ed3 | 333 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 334 | return -EINVAL; |
e5c56ed3 | 335 | |
9ea14d8c TKD |
336 | bank = irq_data_get_irq_chip_data(d); |
337 | ||
338 | if (!bank->regs->leveldetect0 && | |
339 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
340 | return -EINVAL; |
341 | ||
a6472533 | 342 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 343 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 344 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
345 | |
346 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 347 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 348 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 349 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 350 | |
92105bb7 | 351 | return retval; |
5e1c5ff4 TL |
352 | } |
353 | ||
354 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
355 | { | |
92105bb7 | 356 | void __iomem *reg = bank->base; |
5e1c5ff4 | 357 | |
eef4bec7 | 358 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 359 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
360 | |
361 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
362 | if (bank->regs->irqstatus2) { |
363 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 364 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 365 | } |
bedfd154 RQ |
366 | |
367 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
368 | __raw_readl(reg); | |
5e1c5ff4 TL |
369 | } |
370 | ||
371 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
372 | { | |
129fd223 | 373 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
374 | } |
375 | ||
ea6dedd7 ID |
376 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
377 | { | |
378 | void __iomem *reg = bank->base; | |
99c47707 | 379 | u32 l; |
c390aad0 | 380 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 381 | |
28f3b5a0 | 382 | reg += bank->regs->irqenable; |
99c47707 | 383 | l = __raw_readl(reg); |
28f3b5a0 | 384 | if (bank->regs->irqenable_inv) |
99c47707 ID |
385 | l = ~l; |
386 | l &= mask; | |
387 | return l; | |
ea6dedd7 ID |
388 | } |
389 | ||
28f3b5a0 | 390 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 391 | { |
92105bb7 | 392 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
393 | u32 l; |
394 | ||
28f3b5a0 KH |
395 | if (bank->regs->set_irqenable) { |
396 | reg += bank->regs->set_irqenable; | |
397 | l = gpio_mask; | |
398 | } else { | |
399 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 400 | l = __raw_readl(reg); |
28f3b5a0 KH |
401 | if (bank->regs->irqenable_inv) |
402 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
403 | else |
404 | l |= gpio_mask; | |
28f3b5a0 KH |
405 | } |
406 | ||
407 | __raw_writel(l, reg); | |
408 | } | |
409 | ||
410 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
411 | { | |
412 | void __iomem *reg = bank->base; | |
413 | u32 l; | |
414 | ||
415 | if (bank->regs->clr_irqenable) { | |
416 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 417 | l = gpio_mask; |
28f3b5a0 KH |
418 | } else { |
419 | reg += bank->regs->irqenable; | |
56739a69 | 420 | l = __raw_readl(reg); |
28f3b5a0 | 421 | if (bank->regs->irqenable_inv) |
56739a69 | 422 | l |= gpio_mask; |
92105bb7 | 423 | else |
28f3b5a0 | 424 | l &= ~gpio_mask; |
5e1c5ff4 | 425 | } |
28f3b5a0 | 426 | |
5e1c5ff4 TL |
427 | __raw_writel(l, reg); |
428 | } | |
429 | ||
430 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
431 | { | |
28f3b5a0 | 432 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
433 | } |
434 | ||
92105bb7 TL |
435 | /* |
436 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
437 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
438 | * to the target, system will wake up always on GPIO events. While | |
439 | * system is running all registered GPIO interrupts need to have wake-up | |
440 | * enabled. When system is suspended, only selected GPIO interrupts need | |
441 | * to have wake-up enabled. | |
442 | */ | |
443 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
444 | { | |
f64ad1a0 KH |
445 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
446 | unsigned long flags; | |
a6472533 | 447 | |
f64ad1a0 KH |
448 | if (bank->non_wakeup_gpios & gpio_bit) { |
449 | dev_err(bank->dev, | |
450 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); | |
92105bb7 TL |
451 | return -EINVAL; |
452 | } | |
f64ad1a0 KH |
453 | |
454 | spin_lock_irqsave(&bank->lock, flags); | |
455 | if (enable) | |
456 | bank->suspend_wakeup |= gpio_bit; | |
457 | else | |
458 | bank->suspend_wakeup &= ~gpio_bit; | |
459 | ||
460 | spin_unlock_irqrestore(&bank->lock, flags); | |
461 | ||
462 | return 0; | |
92105bb7 TL |
463 | } |
464 | ||
4196dd6b TL |
465 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
466 | { | |
129fd223 | 467 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
468 | _set_gpio_irqenable(bank, gpio, 0); |
469 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 470 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
471 | } |
472 | ||
92105bb7 | 473 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 474 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 475 | { |
e9191028 | 476 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
477 | struct gpio_bank *bank; |
478 | int retval; | |
479 | ||
e9191028 | 480 | bank = irq_data_get_irq_chip_data(d); |
f64ad1a0 | 481 | retval = _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
482 | |
483 | return retval; | |
484 | } | |
485 | ||
3ff164e1 | 486 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 487 | { |
3ff164e1 | 488 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 489 | unsigned long flags; |
52e31344 | 490 | |
55b93c32 TKD |
491 | /* |
492 | * If this is the first gpio_request for the bank, | |
493 | * enable the bank module. | |
494 | */ | |
495 | if (!bank->mod_usage) | |
496 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 497 | |
55b93c32 | 498 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
499 | /* Set trigger to none. You need to enable the desired trigger with |
500 | * request_irq() or set_irq_type(). | |
501 | */ | |
3ff164e1 | 502 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 503 | |
fad96ea8 C |
504 | if (bank->regs->pinctrl) { |
505 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 506 | |
92105bb7 | 507 | /* Claim the pin for MPU */ |
3ff164e1 | 508 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 509 | } |
fad96ea8 | 510 | |
c8eef65a C |
511 | if (bank->regs->ctrl && !bank->mod_usage) { |
512 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
513 | u32 ctrl; | |
514 | ||
515 | ctrl = __raw_readl(reg); | |
516 | /* Module is enabled, clocks are not gated */ | |
517 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
518 | __raw_writel(ctrl, reg); | |
058af1ea | 519 | } |
c8eef65a C |
520 | |
521 | bank->mod_usage |= 1 << offset; | |
522 | ||
a6472533 | 523 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
524 | |
525 | return 0; | |
526 | } | |
527 | ||
3ff164e1 | 528 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 529 | { |
3ff164e1 | 530 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 531 | void __iomem *base = bank->base; |
a6472533 | 532 | unsigned long flags; |
5e1c5ff4 | 533 | |
a6472533 | 534 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b TKD |
535 | |
536 | if (bank->regs->wkup_en) | |
9f096868 | 537 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b TKD |
538 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
539 | ||
c8eef65a C |
540 | bank->mod_usage &= ~(1 << offset); |
541 | ||
542 | if (bank->regs->ctrl && !bank->mod_usage) { | |
543 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
544 | u32 ctrl; | |
545 | ||
546 | ctrl = __raw_readl(reg); | |
547 | /* Module is disabled, clocks are gated */ | |
548 | ctrl |= GPIO_MOD_CTRL_BIT; | |
549 | __raw_writel(ctrl, reg); | |
058af1ea | 550 | } |
c8eef65a | 551 | |
3ff164e1 | 552 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 553 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
554 | |
555 | /* | |
556 | * If this is the last gpio to be freed in the bank, | |
557 | * disable the bank module. | |
558 | */ | |
559 | if (!bank->mod_usage) | |
560 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
561 | } |
562 | ||
563 | /* | |
564 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
565 | * avoid missing GPIO interrupts for other lines in the bank. | |
566 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
567 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
568 | * If we wait to unmask individual GPIO lines in the bank after the | |
569 | * line's interrupt handler has been run, we may miss some nested | |
570 | * interrupts. | |
571 | */ | |
10dd5ce2 | 572 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 573 | { |
92105bb7 | 574 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 575 | u32 isr; |
4318f36b | 576 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 577 | struct gpio_bank *bank; |
ea6dedd7 ID |
578 | u32 retrigger = 0; |
579 | int unmasked = 0; | |
ee144182 | 580 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 581 | |
ee144182 | 582 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 583 | |
6845664a | 584 | bank = irq_get_handler_data(irq); |
eef4bec7 | 585 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 586 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
587 | |
588 | if (WARN_ON(!isr_reg)) | |
589 | goto exit; | |
590 | ||
92105bb7 | 591 | while(1) { |
6e60e79a | 592 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 593 | u32 enabled; |
6e60e79a | 594 | |
ea6dedd7 ID |
595 | enabled = _get_gpio_irqbank_mask(bank); |
596 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 597 | |
9ea14d8c | 598 | if (bank->level_mask) |
b144ff6f | 599 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
600 | |
601 | /* clear edge sensitive interrupts before handler(s) are | |
602 | called so that we don't miss any interrupt occurred while | |
603 | executing them */ | |
28f3b5a0 | 604 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 605 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 606 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
607 | |
608 | /* if there is only edge sensitive GPIO pin interrupts | |
609 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
610 | if (!level_mask && !unmasked) { |
611 | unmasked = 1; | |
ee144182 | 612 | chained_irq_exit(chip, desc); |
ea6dedd7 | 613 | } |
92105bb7 | 614 | |
ea6dedd7 ID |
615 | isr |= retrigger; |
616 | retrigger = 0; | |
92105bb7 TL |
617 | if (!isr) |
618 | break; | |
619 | ||
620 | gpio_irq = bank->virtual_irq_start; | |
621 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 622 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 623 | |
92105bb7 TL |
624 | if (!(isr & 1)) |
625 | continue; | |
29454dde | 626 | |
4318f36b CM |
627 | /* |
628 | * Some chips can't respond to both rising and falling | |
629 | * at the same time. If this irq was requested with | |
630 | * both flags, we need to flip the ICR data for the IRQ | |
631 | * to respond to the IRQ for the opposite direction. | |
632 | * This will be indicated in the bank toggle_mask. | |
633 | */ | |
634 | if (bank->toggle_mask & (1 << gpio_index)) | |
635 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 636 | |
d8aa0251 | 637 | generic_handle_irq(gpio_irq); |
92105bb7 | 638 | } |
1a8bfa1e | 639 | } |
ea6dedd7 ID |
640 | /* if bank has any level sensitive GPIO pin interrupt |
641 | configured, we must unmask the bank interrupt only after | |
642 | handler(s) are executed in order to avoid spurious bank | |
643 | interrupt */ | |
b1cc4c55 | 644 | exit: |
ea6dedd7 | 645 | if (!unmasked) |
ee144182 | 646 | chained_irq_exit(chip, desc); |
55b93c32 | 647 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
648 | } |
649 | ||
e9191028 | 650 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 651 | { |
e9191028 LB |
652 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
653 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 654 | unsigned long flags; |
4196dd6b | 655 | |
85ec7b97 | 656 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 657 | _reset_gpio(bank, gpio); |
85ec7b97 | 658 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
659 | } |
660 | ||
e9191028 | 661 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 662 | { |
e9191028 LB |
663 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
664 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
665 | |
666 | _clear_gpio_irqstatus(bank, gpio); | |
667 | } | |
668 | ||
e9191028 | 669 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 670 | { |
e9191028 LB |
671 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
672 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 673 | unsigned long flags; |
5e1c5ff4 | 674 | |
85ec7b97 | 675 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 676 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 677 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 678 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
679 | } |
680 | ||
e9191028 | 681 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 682 | { |
e9191028 LB |
683 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
684 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 685 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 686 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 687 | unsigned long flags; |
55b6019a | 688 | |
85ec7b97 | 689 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 690 | if (trigger) |
129fd223 | 691 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
692 | |
693 | /* For level-triggered GPIOs, the clearing must be done after | |
694 | * the HW source is cleared, thus after the handler has run */ | |
695 | if (bank->level_mask & irq_mask) { | |
696 | _set_gpio_irqenable(bank, gpio, 0); | |
697 | _clear_gpio_irqstatus(bank, gpio); | |
698 | } | |
5e1c5ff4 | 699 | |
4de8c75b | 700 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 701 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
702 | } |
703 | ||
e5c56ed3 DB |
704 | static struct irq_chip gpio_irq_chip = { |
705 | .name = "GPIO", | |
e9191028 LB |
706 | .irq_shutdown = gpio_irq_shutdown, |
707 | .irq_ack = gpio_ack_irq, | |
708 | .irq_mask = gpio_mask_irq, | |
709 | .irq_unmask = gpio_unmask_irq, | |
710 | .irq_set_type = gpio_irq_type, | |
711 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
712 | }; |
713 | ||
714 | /*---------------------------------------------------------------------*/ | |
715 | ||
79ee031f | 716 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 717 | { |
79ee031f | 718 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 719 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
720 | void __iomem *mask_reg = bank->base + |
721 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 722 | unsigned long flags; |
11a78b79 | 723 | |
a6472533 | 724 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
725 | bank->saved_wakeup = __raw_readl(mask_reg); |
726 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 727 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
728 | |
729 | return 0; | |
730 | } | |
731 | ||
79ee031f | 732 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 733 | { |
79ee031f | 734 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 735 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
736 | void __iomem *mask_reg = bank->base + |
737 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 738 | unsigned long flags; |
11a78b79 | 739 | |
a6472533 | 740 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 741 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 742 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
743 | |
744 | return 0; | |
745 | } | |
746 | ||
47145210 | 747 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
748 | .suspend_noirq = omap_mpuio_suspend_noirq, |
749 | .resume_noirq = omap_mpuio_resume_noirq, | |
750 | }; | |
751 | ||
3c437ffd | 752 | /* use platform_driver for this. */ |
11a78b79 | 753 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
754 | .driver = { |
755 | .name = "mpuio", | |
79ee031f | 756 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
757 | }, |
758 | }; | |
759 | ||
760 | static struct platform_device omap_mpuio_device = { | |
761 | .name = "mpuio", | |
762 | .id = -1, | |
763 | .dev = { | |
764 | .driver = &omap_mpuio_driver.driver, | |
765 | } | |
766 | /* could list the /proc/iomem resources */ | |
767 | }; | |
768 | ||
03e128ca | 769 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 770 | { |
77640aab | 771 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 772 | |
11a78b79 DB |
773 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
774 | (void) platform_device_register(&omap_mpuio_device); | |
775 | } | |
776 | ||
e5c56ed3 | 777 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 778 | |
52e31344 DB |
779 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
780 | { | |
781 | struct gpio_bank *bank; | |
782 | unsigned long flags; | |
783 | ||
784 | bank = container_of(chip, struct gpio_bank, chip); | |
785 | spin_lock_irqsave(&bank->lock, flags); | |
786 | _set_gpio_direction(bank, offset, 1); | |
787 | spin_unlock_irqrestore(&bank->lock, flags); | |
788 | return 0; | |
789 | } | |
790 | ||
b37c45b8 RQ |
791 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
792 | { | |
fa87931a | 793 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 794 | |
b37c45b8 RQ |
795 | return __raw_readl(reg) & mask; |
796 | } | |
797 | ||
52e31344 DB |
798 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
799 | { | |
b37c45b8 RQ |
800 | struct gpio_bank *bank; |
801 | void __iomem *reg; | |
802 | int gpio; | |
803 | u32 mask; | |
804 | ||
805 | gpio = chip->base + offset; | |
a8be8daf | 806 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 807 | reg = bank->base; |
129fd223 | 808 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
809 | |
810 | if (gpio_is_input(bank, mask)) | |
811 | return _get_gpio_datain(bank, gpio); | |
812 | else | |
813 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
814 | } |
815 | ||
816 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
817 | { | |
818 | struct gpio_bank *bank; | |
819 | unsigned long flags; | |
820 | ||
821 | bank = container_of(chip, struct gpio_bank, chip); | |
822 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 823 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
824 | _set_gpio_direction(bank, offset, 0); |
825 | spin_unlock_irqrestore(&bank->lock, flags); | |
826 | return 0; | |
827 | } | |
828 | ||
168ef3d9 FB |
829 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
830 | unsigned debounce) | |
831 | { | |
832 | struct gpio_bank *bank; | |
833 | unsigned long flags; | |
834 | ||
835 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
836 | |
837 | if (!bank->dbck) { | |
838 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
839 | if (IS_ERR(bank->dbck)) | |
840 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
841 | } | |
842 | ||
168ef3d9 FB |
843 | spin_lock_irqsave(&bank->lock, flags); |
844 | _set_gpio_debounce(bank, offset, debounce); | |
845 | spin_unlock_irqrestore(&bank->lock, flags); | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
52e31344 DB |
850 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
851 | { | |
852 | struct gpio_bank *bank; | |
853 | unsigned long flags; | |
854 | ||
855 | bank = container_of(chip, struct gpio_bank, chip); | |
856 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 857 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
858 | spin_unlock_irqrestore(&bank->lock, flags); |
859 | } | |
860 | ||
a007b709 DB |
861 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
862 | { | |
863 | struct gpio_bank *bank; | |
864 | ||
865 | bank = container_of(chip, struct gpio_bank, chip); | |
866 | return bank->virtual_irq_start + offset; | |
867 | } | |
868 | ||
52e31344 DB |
869 | /*---------------------------------------------------------------------*/ |
870 | ||
9a748053 | 871 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 872 | { |
e5ff4440 | 873 | static bool called; |
9f7065da TL |
874 | u32 rev; |
875 | ||
e5ff4440 | 876 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
877 | return; |
878 | ||
e5ff4440 KH |
879 | rev = __raw_readw(bank->base + bank->regs->revision); |
880 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 881 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
882 | |
883 | called = true; | |
9f7065da TL |
884 | } |
885 | ||
8ba55c5c DB |
886 | /* This lock class tells lockdep that GPIO irqs are in a different |
887 | * category than their parents, so it won't report false recursion. | |
888 | */ | |
889 | static struct lock_class_key gpio_lock_class; | |
890 | ||
03e128ca | 891 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 892 | { |
ab985f0f TKD |
893 | void __iomem *base = bank->base; |
894 | u32 l = 0xffffffff; | |
2fae7fbe | 895 | |
ab985f0f TKD |
896 | if (bank->width == 16) |
897 | l = 0xffff; | |
898 | ||
d0d665a8 | 899 | if (bank->is_mpuio) { |
ab985f0f TKD |
900 | __raw_writel(l, bank->base + bank->regs->irqenable); |
901 | return; | |
2fae7fbe | 902 | } |
ab985f0f TKD |
903 | |
904 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
905 | _gpio_rmw(base, bank->regs->irqstatus, l, | |
906 | bank->regs->irqenable_inv == false); | |
907 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0); | |
908 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0); | |
909 | if (bank->regs->debounce_en) | |
910 | _gpio_rmw(base, bank->regs->debounce_en, 0, 1); | |
911 | ||
2dc983c5 TKD |
912 | /* Save OE default value (0xffffffff) in the context */ |
913 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
914 | /* Initialize interface clk ungated, module enabled */ |
915 | if (bank->regs->ctrl) | |
916 | _gpio_rmw(base, bank->regs->ctrl, 0, 1); | |
2fae7fbe VC |
917 | } |
918 | ||
f8b46b58 KH |
919 | static __init void |
920 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |
921 | unsigned int num) | |
922 | { | |
923 | struct irq_chip_generic *gc; | |
924 | struct irq_chip_type *ct; | |
925 | ||
926 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
927 | handle_simple_irq); | |
83233749 TP |
928 | if (!gc) { |
929 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
930 | return; | |
931 | } | |
932 | ||
f8b46b58 KH |
933 | ct = gc->chip_types; |
934 | ||
935 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
936 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
937 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
938 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
939 | |
940 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
941 | ct->chip.irq_set_wake = gpio_wake_enable, |
942 | ||
943 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
944 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
945 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
946 | } | |
947 | ||
d52b31de | 948 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 949 | { |
77640aab | 950 | int j; |
2fae7fbe VC |
951 | static int gpio; |
952 | ||
2fae7fbe VC |
953 | /* |
954 | * REVISIT eventually switch from OMAP-specific gpio structs | |
955 | * over to the generic ones | |
956 | */ | |
957 | bank->chip.request = omap_gpio_request; | |
958 | bank->chip.free = omap_gpio_free; | |
959 | bank->chip.direction_input = gpio_input; | |
960 | bank->chip.get = gpio_get; | |
961 | bank->chip.direction_output = gpio_output; | |
962 | bank->chip.set_debounce = gpio_debounce; | |
963 | bank->chip.set = gpio_set; | |
964 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 965 | if (bank->is_mpuio) { |
2fae7fbe | 966 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
967 | if (bank->regs->wkup_en) |
968 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
969 | bank->chip.base = OMAP_MPUIO(0); |
970 | } else { | |
971 | bank->chip.label = "gpio"; | |
972 | bank->chip.base = gpio; | |
d5f46247 | 973 | gpio += bank->width; |
2fae7fbe | 974 | } |
d5f46247 | 975 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
976 | |
977 | gpiochip_add(&bank->chip); | |
978 | ||
979 | for (j = bank->virtual_irq_start; | |
d5f46247 | 980 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 981 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 982 | irq_set_chip_data(j, bank); |
d0d665a8 | 983 | if (bank->is_mpuio) { |
f8b46b58 KH |
984 | omap_mpuio_alloc_gc(bank, j, bank->width); |
985 | } else { | |
6845664a | 986 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
987 | irq_set_handler(j, handle_simple_irq); |
988 | set_irq_flags(j, IRQF_VALID); | |
989 | } | |
2fae7fbe | 990 | } |
6845664a TG |
991 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
992 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
993 | } |
994 | ||
77640aab | 995 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 996 | { |
77640aab VC |
997 | struct omap_gpio_platform_data *pdata; |
998 | struct resource *res; | |
5e1c5ff4 | 999 | struct gpio_bank *bank; |
03e128ca | 1000 | int ret = 0; |
5e1c5ff4 | 1001 | |
03e128ca C |
1002 | if (!pdev->dev.platform_data) { |
1003 | ret = -EINVAL; | |
1004 | goto err_exit; | |
5492fb1a | 1005 | } |
5492fb1a | 1006 | |
03e128ca C |
1007 | bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); |
1008 | if (!bank) { | |
1009 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1010 | ret = -ENOMEM; | |
1011 | goto err_exit; | |
1012 | } | |
92105bb7 | 1013 | |
77640aab VC |
1014 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1015 | if (unlikely(!res)) { | |
03e128ca C |
1016 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", |
1017 | pdev->id); | |
1018 | ret = -ENODEV; | |
1019 | goto err_free; | |
44169075 | 1020 | } |
5e1c5ff4 | 1021 | |
77640aab | 1022 | bank->irq = res->start; |
03e128ca C |
1023 | bank->id = pdev->id; |
1024 | ||
1025 | pdata = pdev->dev.platform_data; | |
77640aab | 1026 | bank->virtual_irq_start = pdata->virtual_irq_start; |
77640aab VC |
1027 | bank->dev = &pdev->dev; |
1028 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1029 | bank->stride = pdata->bank_stride; |
d5f46247 | 1030 | bank->width = pdata->bank_width; |
d0d665a8 | 1031 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1032 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1033 | bank->loses_context = pdata->loses_context; |
60a3437d | 1034 | bank->get_context_loss_count = pdata->get_context_loss_count; |
fa87931a KH |
1035 | bank->regs = pdata->regs; |
1036 | ||
1037 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1038 | bank->set_dataout = _set_gpio_dataout_reg; | |
1039 | else | |
1040 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1041 | |
77640aab | 1042 | spin_lock_init(&bank->lock); |
9f7065da | 1043 | |
77640aab VC |
1044 | /* Static mapping, never released */ |
1045 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1046 | if (unlikely(!res)) { | |
03e128ca C |
1047 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", |
1048 | pdev->id); | |
1049 | ret = -ENODEV; | |
1050 | goto err_free; | |
77640aab | 1051 | } |
89db9482 | 1052 | |
77640aab VC |
1053 | bank->base = ioremap(res->start, resource_size(res)); |
1054 | if (!bank->base) { | |
03e128ca C |
1055 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", |
1056 | pdev->id); | |
1057 | ret = -ENOMEM; | |
1058 | goto err_free; | |
5e1c5ff4 TL |
1059 | } |
1060 | ||
065cd795 TKD |
1061 | platform_set_drvdata(pdev, bank); |
1062 | ||
77640aab | 1063 | pm_runtime_enable(bank->dev); |
55b93c32 | 1064 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1065 | pm_runtime_get_sync(bank->dev); |
1066 | ||
d0d665a8 | 1067 | if (bank->is_mpuio) |
ab985f0f TKD |
1068 | mpuio_init(bank); |
1069 | ||
03e128ca | 1070 | omap_gpio_mod_init(bank); |
77640aab | 1071 | omap_gpio_chip_init(bank); |
9a748053 | 1072 | omap_gpio_show_rev(bank); |
9f7065da | 1073 | |
55b93c32 TKD |
1074 | pm_runtime_put(bank->dev); |
1075 | ||
03e128ca | 1076 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1077 | |
03e128ca C |
1078 | return ret; |
1079 | ||
1080 | err_free: | |
1081 | kfree(bank); | |
1082 | err_exit: | |
1083 | return ret; | |
5e1c5ff4 TL |
1084 | } |
1085 | ||
55b93c32 TKD |
1086 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1087 | ||
1088 | #if defined(CONFIG_PM_SLEEP) | |
1089 | static int omap_gpio_suspend(struct device *dev) | |
92105bb7 | 1090 | { |
065cd795 TKD |
1091 | struct platform_device *pdev = to_platform_device(dev); |
1092 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1093 | void __iomem *base = bank->base; | |
1094 | void __iomem *wakeup_enable; | |
1095 | unsigned long flags; | |
92105bb7 | 1096 | |
065cd795 TKD |
1097 | if (!bank->mod_usage || !bank->loses_context) |
1098 | return 0; | |
92105bb7 | 1099 | |
065cd795 TKD |
1100 | if (!bank->regs->wkup_en || !bank->suspend_wakeup) |
1101 | return 0; | |
6ed87c5b | 1102 | |
065cd795 | 1103 | wakeup_enable = bank->base + bank->regs->wkup_en; |
92105bb7 | 1104 | |
065cd795 TKD |
1105 | spin_lock_irqsave(&bank->lock, flags); |
1106 | bank->saved_wakeup = __raw_readl(wakeup_enable); | |
1107 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); | |
1108 | _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1); | |
1109 | spin_unlock_irqrestore(&bank->lock, flags); | |
92105bb7 TL |
1110 | |
1111 | return 0; | |
1112 | } | |
1113 | ||
55b93c32 | 1114 | static int omap_gpio_resume(struct device *dev) |
92105bb7 | 1115 | { |
065cd795 TKD |
1116 | struct platform_device *pdev = to_platform_device(dev); |
1117 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1118 | void __iomem *base = bank->base; | |
1119 | unsigned long flags; | |
92105bb7 | 1120 | |
065cd795 TKD |
1121 | if (!bank->mod_usage || !bank->loses_context) |
1122 | return 0; | |
92105bb7 | 1123 | |
065cd795 TKD |
1124 | if (!bank->regs->wkup_en || !bank->saved_wakeup) |
1125 | return 0; | |
92105bb7 | 1126 | |
065cd795 TKD |
1127 | spin_lock_irqsave(&bank->lock, flags); |
1128 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); | |
1129 | _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1); | |
1130 | spin_unlock_irqrestore(&bank->lock, flags); | |
92105bb7 | 1131 | |
55b93c32 TKD |
1132 | return 0; |
1133 | } | |
1134 | #endif /* CONFIG_PM_SLEEP */ | |
3ac4fa99 | 1135 | |
2dc983c5 | 1136 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d TKD |
1137 | static void omap_gpio_save_context(struct gpio_bank *bank); |
1138 | static void omap_gpio_restore_context(struct gpio_bank *bank); | |
3ac4fa99 | 1139 | |
2dc983c5 | 1140 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1141 | { |
2dc983c5 TKD |
1142 | struct platform_device *pdev = to_platform_device(dev); |
1143 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1144 | u32 l1 = 0, l2 = 0; | |
1145 | unsigned long flags; | |
8865b9b6 | 1146 | |
2dc983c5 TKD |
1147 | spin_lock_irqsave(&bank->lock, flags); |
1148 | if (bank->power_mode != OFF_MODE) { | |
1149 | bank->power_mode = 0; | |
1150 | goto save_gpio_context; | |
1151 | } | |
1152 | /* | |
1153 | * If going to OFF, remove triggering for all | |
1154 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1155 | * generated. See OMAP2420 Errata item 1.101. | |
1156 | */ | |
1157 | if (!(bank->enabled_non_wakeup_gpios)) | |
1158 | goto save_gpio_context; | |
43ffcd9a | 1159 | |
2dc983c5 TKD |
1160 | bank->saved_datain = __raw_readl(bank->base + |
1161 | bank->regs->datain); | |
1162 | l1 = __raw_readl(bank->base + bank->regs->fallingdetect); | |
1163 | l2 = __raw_readl(bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1164 | |
2dc983c5 TKD |
1165 | bank->saved_fallingdetect = l1; |
1166 | bank->saved_risingdetect = l2; | |
1167 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1168 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1169 | |
2dc983c5 TKD |
1170 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1171 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1172 | |
2dc983c5 | 1173 | bank->workaround_enabled = true; |
3f1686a9 | 1174 | |
60a3437d | 1175 | save_gpio_context: |
2dc983c5 TKD |
1176 | if (bank->get_context_loss_count) |
1177 | bank->context_loss_count = | |
60a3437d TKD |
1178 | bank->get_context_loss_count(bank->dev); |
1179 | ||
2dc983c5 TKD |
1180 | omap_gpio_save_context(bank); |
1181 | spin_unlock_irqrestore(&bank->lock, flags); | |
55b93c32 | 1182 | |
2dc983c5 | 1183 | return 0; |
3ac4fa99 JY |
1184 | } |
1185 | ||
2dc983c5 | 1186 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1187 | { |
2dc983c5 TKD |
1188 | struct platform_device *pdev = to_platform_device(dev); |
1189 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1190 | int context_lost_cnt_after; | |
1191 | u32 l = 0, gen, gen0, gen1; | |
1192 | unsigned long flags; | |
8865b9b6 | 1193 | |
2dc983c5 TKD |
1194 | spin_lock_irqsave(&bank->lock, flags); |
1195 | if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { | |
1196 | spin_unlock_irqrestore(&bank->lock, flags); | |
1197 | return 0; | |
1198 | } | |
55b93c32 | 1199 | |
2dc983c5 TKD |
1200 | if (bank->get_context_loss_count) { |
1201 | context_lost_cnt_after = | |
1202 | bank->get_context_loss_count(bank->dev); | |
1203 | if (context_lost_cnt_after != bank->context_loss_count || | |
1204 | !context_lost_cnt_after) { | |
1205 | omap_gpio_restore_context(bank); | |
1206 | } else { | |
1207 | spin_unlock_irqrestore(&bank->lock, flags); | |
1208 | return 0; | |
60a3437d | 1209 | } |
2dc983c5 | 1210 | } |
43ffcd9a | 1211 | |
2dc983c5 TKD |
1212 | __raw_writel(bank->saved_fallingdetect, |
1213 | bank->base + bank->regs->fallingdetect); | |
1214 | __raw_writel(bank->saved_risingdetect, | |
1215 | bank->base + bank->regs->risingdetect); | |
1216 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1217 | |
2dc983c5 TKD |
1218 | /* |
1219 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1220 | * state. If so, generate an IRQ by software. This is | |
1221 | * horribly racy, but it's the best we can do to work around | |
1222 | * this silicon bug. | |
1223 | */ | |
1224 | l ^= bank->saved_datain; | |
1225 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1226 | |
2dc983c5 TKD |
1227 | /* |
1228 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1229 | * configured with falling edge only; and vice versa. | |
1230 | */ | |
1231 | gen0 = l & bank->saved_fallingdetect; | |
1232 | gen0 &= bank->saved_datain; | |
82dbb9d3 | 1233 | |
2dc983c5 TKD |
1234 | gen1 = l & bank->saved_risingdetect; |
1235 | gen1 &= ~(bank->saved_datain); | |
82dbb9d3 | 1236 | |
2dc983c5 TKD |
1237 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
1238 | gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect)); | |
1239 | /* Consider all GPIO IRQs needed to be updated */ | |
1240 | gen |= gen0 | gen1; | |
82dbb9d3 | 1241 | |
2dc983c5 TKD |
1242 | if (gen) { |
1243 | u32 old0, old1; | |
82dbb9d3 | 1244 | |
2dc983c5 TKD |
1245 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1246 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1247 | |
2dc983c5 TKD |
1248 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
1249 | __raw_writel(old0 | gen, bank->base + | |
9ea14d8c | 1250 | bank->regs->leveldetect0); |
2dc983c5 | 1251 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1252 | bank->regs->leveldetect1); |
2dc983c5 | 1253 | } |
9ea14d8c | 1254 | |
2dc983c5 TKD |
1255 | if (cpu_is_omap44xx()) { |
1256 | __raw_writel(old0 | l, bank->base + | |
9ea14d8c | 1257 | bank->regs->leveldetect0); |
2dc983c5 | 1258 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1259 | bank->regs->leveldetect1); |
3ac4fa99 | 1260 | } |
2dc983c5 TKD |
1261 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1262 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1263 | } | |
1264 | ||
1265 | bank->workaround_enabled = false; | |
1266 | spin_unlock_irqrestore(&bank->lock, flags); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | #endif /* CONFIG_PM_RUNTIME */ | |
1271 | ||
1272 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1273 | { | |
1274 | struct gpio_bank *bank; | |
1275 | ||
1276 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
1277 | int j; | |
1278 | ||
1279 | if (!bank->mod_usage || !bank->loses_context) | |
1280 | continue; | |
1281 | ||
1282 | bank->power_mode = pwr_mode; | |
1283 | ||
1284 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) | |
1285 | clk_disable(bank->dbck); | |
1286 | ||
1287 | pm_runtime_put_sync_suspend(bank->dev); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | void omap2_gpio_resume_after_idle(void) | |
1292 | { | |
1293 | struct gpio_bank *bank; | |
1294 | ||
1295 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
1296 | int j; | |
1297 | ||
1298 | if (!bank->mod_usage || !bank->loses_context) | |
1299 | continue; | |
1300 | ||
1301 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) | |
1302 | clk_enable(bank->dbck); | |
1303 | ||
1304 | pm_runtime_get_sync(bank->dev); | |
3ac4fa99 | 1305 | } |
3ac4fa99 JY |
1306 | } |
1307 | ||
2dc983c5 | 1308 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1309 | static void omap_gpio_save_context(struct gpio_bank *bank) |
40c670f0 | 1310 | { |
60a3437d | 1311 | bank->context.irqenable1 = |
ae10f233 | 1312 | __raw_readl(bank->base + bank->regs->irqenable); |
60a3437d | 1313 | bank->context.irqenable2 = |
ae10f233 | 1314 | __raw_readl(bank->base + bank->regs->irqenable2); |
60a3437d | 1315 | bank->context.wake_en = |
ae10f233 TKD |
1316 | __raw_readl(bank->base + bank->regs->wkup_en); |
1317 | bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl); | |
1318 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
60a3437d | 1319 | bank->context.leveldetect0 = |
ae10f233 | 1320 | __raw_readl(bank->base + bank->regs->leveldetect0); |
60a3437d | 1321 | bank->context.leveldetect1 = |
ae10f233 | 1322 | __raw_readl(bank->base + bank->regs->leveldetect1); |
60a3437d | 1323 | bank->context.risingdetect = |
ae10f233 | 1324 | __raw_readl(bank->base + bank->regs->risingdetect); |
60a3437d | 1325 | bank->context.fallingdetect = |
ae10f233 TKD |
1326 | __raw_readl(bank->base + bank->regs->fallingdetect); |
1327 | bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout); | |
40c670f0 RN |
1328 | } |
1329 | ||
60a3437d | 1330 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1331 | { |
60a3437d | 1332 | __raw_writel(bank->context.irqenable1, |
ae10f233 | 1333 | bank->base + bank->regs->irqenable); |
60a3437d | 1334 | __raw_writel(bank->context.irqenable2, |
ae10f233 | 1335 | bank->base + bank->regs->irqenable2); |
60a3437d | 1336 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1337 | bank->base + bank->regs->wkup_en); |
1338 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1339 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); | |
60a3437d | 1340 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1341 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1342 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1343 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1344 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1345 | bank->base + bank->regs->risingdetect); |
60a3437d | 1346 | __raw_writel(bank->context.fallingdetect, |
ae10f233 TKD |
1347 | bank->base + bank->regs->fallingdetect); |
1348 | __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout); | |
40c670f0 | 1349 | } |
2dc983c5 | 1350 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 TKD |
1351 | #else |
1352 | #define omap_gpio_suspend NULL | |
1353 | #define omap_gpio_resume NULL | |
2dc983c5 TKD |
1354 | #define omap_gpio_runtime_suspend NULL |
1355 | #define omap_gpio_runtime_resume NULL | |
40c670f0 RN |
1356 | #endif |
1357 | ||
55b93c32 TKD |
1358 | static const struct dev_pm_ops gpio_pm_ops = { |
1359 | SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) | |
2dc983c5 TKD |
1360 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1361 | NULL) | |
55b93c32 TKD |
1362 | }; |
1363 | ||
77640aab VC |
1364 | static struct platform_driver omap_gpio_driver = { |
1365 | .probe = omap_gpio_probe, | |
1366 | .driver = { | |
1367 | .name = "omap_gpio", | |
55b93c32 | 1368 | .pm = &gpio_pm_ops, |
77640aab VC |
1369 | }, |
1370 | }; | |
1371 | ||
5e1c5ff4 | 1372 | /* |
77640aab VC |
1373 | * gpio driver register needs to be done before |
1374 | * machine_init functions access gpio APIs. | |
1375 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1376 | */ |
77640aab | 1377 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1378 | { |
77640aab | 1379 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1380 | } |
77640aab | 1381 | postcore_initcall(omap_gpio_drv_reg); |