Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5e1c5ff4 | 2 | /* |
5e1c5ff4 TL |
3 | * Support functions for OMAP GPIO |
4 | * | |
92105bb7 | 5 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 6 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 7 | * |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
5e1c5ff4 TL |
10 | */ |
11 | ||
5e1c5ff4 TL |
12 | #include <linux/init.h> |
13 | #include <linux/module.h> | |
5e1c5ff4 | 14 | #include <linux/interrupt.h> |
39575d11 | 15 | #include <linux/seq_file.h> |
3c437ffd | 16 | #include <linux/syscore_ops.h> |
92105bb7 | 17 | #include <linux/err.h> |
f8ce2547 | 18 | #include <linux/clk.h> |
fced80c7 | 19 | #include <linux/io.h> |
b764a586 | 20 | #include <linux/cpu_pm.h> |
96751fcb | 21 | #include <linux/device.h> |
77640aab | 22 | #include <linux/pm_runtime.h> |
55b93c32 | 23 | #include <linux/pm.h> |
384ebe1c BC |
24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | |
b7351b07 | 26 | #include <linux/gpio/driver.h> |
9370084e | 27 | #include <linux/bitops.h> |
4b25408f | 28 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 29 | |
e85ec6c3 | 30 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 31 | |
6d62e216 | 32 | struct gpio_regs { |
ddd8d94c | 33 | u32 sysconfig; |
6d62e216 C |
34 | u32 irqenable1; |
35 | u32 irqenable2; | |
36 | u32 wake_en; | |
37 | u32 ctrl; | |
38 | u32 oe; | |
39 | u32 leveldetect0; | |
40 | u32 leveldetect1; | |
41 | u32 risingdetect; | |
42 | u32 fallingdetect; | |
43 | u32 dataout; | |
ae547354 NM |
44 | u32 debounce; |
45 | u32 debounce_en; | |
6d62e216 C |
46 | }; |
47 | ||
5e1c5ff4 | 48 | struct gpio_bank { |
92105bb7 | 49 | void __iomem *base; |
18bd49c4 | 50 | const struct omap_gpio_reg_offs *regs; |
39575d11 | 51 | struct device *dev; |
18bd49c4 | 52 | |
30cefeac | 53 | int irq; |
3ac4fa99 JY |
54 | u32 non_wakeup_gpios; |
55 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 56 | struct gpio_regs context; |
3ac4fa99 | 57 | u32 saved_datain; |
b144ff6f | 58 | u32 level_mask; |
4318f36b | 59 | u32 toggle_mask; |
4dbada2b | 60 | raw_spinlock_t lock; |
450fa54c | 61 | raw_spinlock_t wa_lock; |
52e31344 | 62 | struct gpio_chip chip; |
89db9482 | 63 | struct clk *dbck; |
b764a586 TL |
64 | struct notifier_block nb; |
65 | unsigned int is_suspended:1; | |
f02a0398 | 66 | unsigned int needs_resume:1; |
058af1ea | 67 | u32 mod_usage; |
fa365e4d | 68 | u32 irq_usage; |
8865b9b6 | 69 | u32 dbck_enable_mask; |
72f83af9 | 70 | bool dbck_enabled; |
d0d665a8 | 71 | bool is_mpuio; |
77640aab | 72 | bool dbck_flag; |
0cde8d03 | 73 | bool loses_context; |
352a2d5b | 74 | bool context_valid; |
5de62b86 | 75 | int stride; |
d5f46247 | 76 | u32 width; |
60a3437d | 77 | int context_loss_count; |
fa87931a | 78 | |
04ebcbd8 | 79 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 80 | int (*get_context_loss_count)(struct device *dev); |
5e1c5ff4 TL |
81 | }; |
82 | ||
c8eef65a | 83 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 84 | |
fa365e4d | 85 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 86 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 87 | |
3d009c8c TL |
88 | static void omap_gpio_unmask_irq(struct irq_data *d); |
89 | ||
a0e827c6 | 90 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 91 | { |
fb655f57 | 92 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 93 | return gpiochip_get_data(chip); |
25db711d BC |
94 | } |
95 | ||
8ee1de65 | 96 | static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) |
5e1c5ff4 | 97 | { |
8ee1de65 | 98 | u32 val = readl_relaxed(reg); |
5e1c5ff4 | 99 | |
8ee1de65 RK |
100 | if (set) |
101 | val |= mask; | |
5e1c5ff4 | 102 | else |
8ee1de65 RK |
103 | val &= ~mask; |
104 | ||
105 | writel_relaxed(val, reg); | |
106 | ||
107 | return val; | |
108 | } | |
109 | ||
110 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, | |
111 | int is_input) | |
112 | { | |
113 | bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, | |
114 | BIT(gpio), is_input); | |
5e1c5ff4 TL |
115 | } |
116 | ||
fa87931a KH |
117 | |
118 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 119 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 120 | int enable) |
5e1c5ff4 | 121 | { |
92105bb7 | 122 | void __iomem *reg = bank->base; |
04ebcbd8 | 123 | u32 l = BIT(offset); |
5e1c5ff4 | 124 | |
2c836f7e | 125 | if (enable) { |
fa87931a | 126 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
127 | bank->context.dataout |= l; |
128 | } else { | |
fa87931a | 129 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
130 | bank->context.dataout &= ~l; |
131 | } | |
5e1c5ff4 | 132 | |
661553b9 | 133 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
134 | } |
135 | ||
fa87931a | 136 | /* set data out value using mask register */ |
04ebcbd8 | 137 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 138 | int enable) |
5e1c5ff4 | 139 | { |
8ee1de65 RK |
140 | bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, |
141 | BIT(offset), enable); | |
ece9528e | 142 | } |
92105bb7 | 143 | |
a0e827c6 | 144 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
145 | { |
146 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 147 | clk_enable(bank->dbck); |
72f83af9 | 148 | bank->dbck_enabled = true; |
9e303f22 | 149 | |
661553b9 | 150 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 151 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
152 | } |
153 | } | |
154 | ||
a0e827c6 | 155 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
156 | { |
157 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
158 | /* |
159 | * Disable debounce before cutting it's clock. If debounce is | |
160 | * enabled but the clock is not, GPIO module seems to be unable | |
161 | * to detect events and generate interrupts at least on OMAP3. | |
162 | */ | |
661553b9 | 163 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 164 | |
5d9452e7 | 165 | clk_disable(bank->dbck); |
72f83af9 TKD |
166 | bank->dbck_enabled = false; |
167 | } | |
168 | } | |
169 | ||
168ef3d9 | 170 | /** |
a0e827c6 | 171 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 172 | * @bank: the gpio bank we're acting upon |
4a58d229 | 173 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
174 | * @debounce: debounce time to use |
175 | * | |
e85ec6c3 GS |
176 | * OMAP's debounce time is in 31us steps |
177 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
178 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
179 | * |
180 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 181 | */ |
83977443 DR |
182 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
183 | unsigned debounce) | |
168ef3d9 | 184 | { |
168ef3d9 FB |
185 | u32 val; |
186 | u32 l; | |
e85ec6c3 | 187 | bool enable = !!debounce; |
168ef3d9 | 188 | |
77640aab | 189 | if (!bank->dbck_flag) |
83977443 | 190 | return -ENOTSUPP; |
77640aab | 191 | |
e85ec6c3 GS |
192 | if (enable) { |
193 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
194 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
195 | return -EINVAL; | |
e85ec6c3 | 196 | } |
168ef3d9 | 197 | |
4a58d229 | 198 | l = BIT(offset); |
168ef3d9 | 199 | |
5d9452e7 | 200 | clk_enable(bank->dbck); |
754dfd79 | 201 | writel_relaxed(debounce, bank->base + bank->regs->debounce); |
168ef3d9 | 202 | |
8ee1de65 | 203 | val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); |
f7ec0b0b | 204 | bank->dbck_enable_mask = val; |
168ef3d9 | 205 | |
5d9452e7 | 206 | clk_disable(bank->dbck); |
6fd9c421 TKD |
207 | /* |
208 | * Enable debounce clock per module. | |
209 | * This call is mandatory because in omap_gpio_request() when | |
210 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
211 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
212 | * used within _gpio_dbck_enable() is still not initialized at | |
213 | * that point. Therefore we have to enable dbck here. | |
214 | */ | |
a0e827c6 | 215 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
216 | if (bank->dbck_enable_mask) { |
217 | bank->context.debounce = debounce; | |
218 | bank->context.debounce_en = val; | |
219 | } | |
83977443 DR |
220 | |
221 | return 0; | |
168ef3d9 FB |
222 | } |
223 | ||
c9c55d92 | 224 | /** |
a0e827c6 | 225 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 226 | * @bank: the gpio bank we're acting upon |
4a58d229 | 227 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
228 | * |
229 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
230 | * this is the only gpio in this bank using debounce, then clear the debounce | |
231 | * time too. The debounce clock will also be disabled when calling this function | |
232 | * if this is the only gpio in the bank using debounce. | |
233 | */ | |
4a58d229 | 234 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 235 | { |
4a58d229 | 236 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
237 | |
238 | if (!bank->dbck_flag) | |
239 | return; | |
240 | ||
241 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
242 | return; | |
243 | ||
244 | bank->dbck_enable_mask &= ~gpio_bit; | |
245 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 246 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
247 | bank->base + bank->regs->debounce_en); |
248 | ||
249 | if (!bank->dbck_enable_mask) { | |
250 | bank->context.debounce = 0; | |
661553b9 | 251 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 252 | bank->regs->debounce); |
5d9452e7 | 253 | clk_disable(bank->dbck); |
c9c55d92 JH |
254 | bank->dbck_enabled = false; |
255 | } | |
256 | } | |
257 | ||
da38ef3e TL |
258 | /* |
259 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
260 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
261 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
262 | * are capable waking up the system from off mode. | |
263 | */ | |
264 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
265 | { | |
266 | u32 no_wake = bank->non_wakeup_gpios; | |
267 | ||
268 | if (no_wake) | |
269 | return !!(~no_wake & gpio_mask); | |
270 | ||
271 | return false; | |
272 | } | |
273 | ||
a0e827c6 | 274 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 275 | unsigned trigger) |
5e1c5ff4 | 276 | { |
3ac4fa99 | 277 | void __iomem *base = bank->base; |
b1e9fec2 | 278 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 279 | |
8ee1de65 | 280 | omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, |
a0e827c6 | 281 | trigger & IRQ_TYPE_LEVEL_LOW); |
8ee1de65 | 282 | omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, |
a0e827c6 | 283 | trigger & IRQ_TYPE_LEVEL_HIGH); |
e6818d29 RK |
284 | |
285 | /* | |
286 | * We need the edge detection enabled for to allow the GPIO block | |
287 | * to be woken from idle state. Set the appropriate edge detection | |
288 | * in addition to the level detection. | |
289 | */ | |
8ee1de65 | 290 | omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, |
e6818d29 | 291 | trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); |
8ee1de65 | 292 | omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, |
e6818d29 | 293 | trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); |
5e571f38 | 294 | |
41d87cbd | 295 | bank->context.leveldetect0 = |
661553b9 | 296 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 297 | bank->context.leveldetect1 = |
661553b9 | 298 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 299 | bank->context.risingdetect = |
661553b9 | 300 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 301 | bank->context.fallingdetect = |
661553b9 | 302 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd | 303 | |
a0e881e2 RK |
304 | bank->level_mask = bank->context.leveldetect0 | |
305 | bank->context.leveldetect1; | |
5e571f38 | 306 | |
55b220ca | 307 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 308 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
309 | /* |
310 | * Log the edge gpio and manually trigger the IRQ | |
311 | * after resume if the input level changes | |
312 | * to avoid irq lost during PER RET/OFF mode | |
313 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
314 | */ | |
315 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
316 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
317 | else | |
318 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
319 | } | |
92105bb7 TL |
320 | } |
321 | ||
4318f36b CM |
322 | /* |
323 | * This only applies to chips that can't do both rising and falling edge | |
324 | * detection at once. For all other chips, this function is a noop. | |
325 | */ | |
a0e827c6 | 326 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b | 327 | { |
a47b9158 RK |
328 | if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { |
329 | void __iomem *reg = bank->base + bank->regs->irqctrl; | |
5e571f38 | 330 | |
a47b9158 RK |
331 | writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); |
332 | } | |
4318f36b CM |
333 | } |
334 | ||
a0e827c6 JMC |
335 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
336 | unsigned trigger) | |
92105bb7 TL |
337 | { |
338 | void __iomem *reg = bank->base; | |
339 | u32 l = 0; | |
5e1c5ff4 | 340 | |
5e571f38 | 341 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 342 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
343 | } else if (bank->regs->irqctrl) { |
344 | reg += bank->regs->irqctrl; | |
345 | ||
661553b9 | 346 | l = readl_relaxed(reg); |
29501577 | 347 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 348 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 349 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 350 | l |= BIT(gpio); |
6cab4860 | 351 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 352 | l &= ~(BIT(gpio)); |
92105bb7 | 353 | else |
5e571f38 TKD |
354 | return -EINVAL; |
355 | ||
661553b9 | 356 | writel_relaxed(l, reg); |
5e571f38 | 357 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 358 | if (gpio & 0x08) |
5e571f38 | 359 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 360 | else |
5e571f38 TKD |
361 | reg += bank->regs->edgectrl1; |
362 | ||
5e1c5ff4 | 363 | gpio &= 0x07; |
661553b9 | 364 | l = readl_relaxed(reg); |
5e1c5ff4 | 365 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 366 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 367 | l |= 2 << (gpio << 1); |
6cab4860 | 368 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 369 | l |= BIT(gpio << 1); |
661553b9 | 370 | writel_relaxed(l, reg); |
5e1c5ff4 | 371 | } |
92105bb7 | 372 | return 0; |
5e1c5ff4 TL |
373 | } |
374 | ||
a0e827c6 | 375 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
376 | { |
377 | if (bank->regs->pinctrl) { | |
378 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
379 | ||
380 | /* Claim the pin for MPU */ | |
b1e9fec2 | 381 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
382 | } |
383 | ||
384 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
385 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
386 | u32 ctrl; | |
387 | ||
661553b9 | 388 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
389 | /* Module is enabled, clocks are not gated */ |
390 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 391 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
392 | bank->context.ctrl = ctrl; |
393 | } | |
394 | } | |
395 | ||
a0e827c6 | 396 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 | 397 | { |
fac7fa16 JMC |
398 | if (bank->regs->ctrl && !BANK_USED(bank)) { |
399 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
400 | u32 ctrl; | |
401 | ||
661553b9 | 402 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
403 | /* Module is disabled, clocks are gated */ |
404 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 405 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
406 | bank->context.ctrl = ctrl; |
407 | } | |
408 | } | |
409 | ||
b2b20045 | 410 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
411 | { |
412 | void __iomem *reg = bank->base + bank->regs->direction; | |
413 | ||
b2b20045 | 414 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
415 | } |
416 | ||
37e14ecf | 417 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
418 | { |
419 | if (!LINE_USED(bank->mod_usage, offset)) { | |
420 | omap_enable_gpio_module(bank, offset); | |
421 | omap_set_gpio_direction(bank, offset, 1); | |
422 | } | |
37e14ecf | 423 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
424 | } |
425 | ||
a0e827c6 | 426 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 427 | { |
a0e827c6 | 428 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 429 | int retval; |
a6472533 | 430 | unsigned long flags; |
ea5fbe8d | 431 | unsigned offset = d->hwirq; |
92105bb7 | 432 | |
e5c56ed3 | 433 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 434 | return -EINVAL; |
e5c56ed3 | 435 | |
9ea14d8c TKD |
436 | if (!bank->regs->leveldetect0 && |
437 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
438 | return -EINVAL; |
439 | ||
4dbada2b | 440 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 441 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 442 | if (retval) { |
627c89b4 | 443 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 444 | goto error; |
977bd8a9 | 445 | } |
37e14ecf | 446 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 447 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 448 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
449 | retval = -EINVAL; |
450 | goto error; | |
fac7fa16 | 451 | } |
4dbada2b | 452 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
453 | |
454 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 455 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 456 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
457 | /* |
458 | * Edge IRQs are already cleared/acked in irq_handler and | |
459 | * not need to be masked, as result handle_edge_irq() | |
460 | * logic is excessed here and may cause lose of interrupts. | |
461 | * So just use handle_simple_irq. | |
462 | */ | |
463 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 464 | |
1562e461 GS |
465 | return 0; |
466 | ||
467 | error: | |
92105bb7 | 468 | return retval; |
5e1c5ff4 TL |
469 | } |
470 | ||
a0e827c6 | 471 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 472 | { |
92105bb7 | 473 | void __iomem *reg = bank->base; |
5e1c5ff4 | 474 | |
eef4bec7 | 475 | reg += bank->regs->irqstatus; |
661553b9 | 476 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
477 | |
478 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
479 | if (bank->regs->irqstatus2) { |
480 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 481 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 482 | } |
bedfd154 RQ |
483 | |
484 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 485 | readl_relaxed(reg); |
5e1c5ff4 TL |
486 | } |
487 | ||
9943f261 GS |
488 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
489 | unsigned offset) | |
5e1c5ff4 | 490 | { |
9943f261 | 491 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
492 | } |
493 | ||
a0e827c6 | 494 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
495 | { |
496 | void __iomem *reg = bank->base; | |
99c47707 | 497 | u32 l; |
b1e9fec2 | 498 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 499 | |
28f3b5a0 | 500 | reg += bank->regs->irqenable; |
661553b9 | 501 | l = readl_relaxed(reg); |
28f3b5a0 | 502 | if (bank->regs->irqenable_inv) |
99c47707 ID |
503 | l = ~l; |
504 | l &= mask; | |
505 | return l; | |
ea6dedd7 ID |
506 | } |
507 | ||
31b2d7f7 RK |
508 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
509 | unsigned offset, int enable) | |
5e1c5ff4 | 510 | { |
92105bb7 | 511 | void __iomem *reg = bank->base; |
31b2d7f7 | 512 | u32 gpio_mask = BIT(offset); |
5e1c5ff4 | 513 | |
31b2d7f7 RK |
514 | if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { |
515 | if (enable) { | |
516 | reg += bank->regs->set_irqenable; | |
517 | bank->context.irqenable1 |= gpio_mask; | |
518 | } else { | |
519 | reg += bank->regs->clr_irqenable; | |
520 | bank->context.irqenable1 &= ~gpio_mask; | |
521 | } | |
522 | writel_relaxed(gpio_mask, reg); | |
28f3b5a0 | 523 | } else { |
31b2d7f7 RK |
524 | bank->context.irqenable1 = |
525 | omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, | |
526 | enable ^ bank->regs->irqenable_inv); | |
28f3b5a0 KH |
527 | } |
528 | ||
40fd422a RK |
529 | /* |
530 | * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM | |
531 | * note requiring correlation between the IRQ enable registers and | |
532 | * the wakeup registers. In any case, we want wakeup from idle | |
533 | * enabled for the GPIOs which support this feature. | |
534 | */ | |
535 | if (bank->regs->wkup_en && | |
536 | (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { | |
537 | bank->context.wake_en = | |
538 | omap_gpio_rmw(bank->base + bank->regs->wkup_en, | |
539 | gpio_mask, enable); | |
5e1c5ff4 | 540 | } |
5e1c5ff4 TL |
541 | } |
542 | ||
92105bb7 | 543 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 544 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 545 | { |
a0e827c6 | 546 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 547 | |
0c0451e7 | 548 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
549 | } |
550 | ||
5e1c5ff4 TL |
551 | /* |
552 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
553 | * avoid missing GPIO interrupts for other lines in the bank. | |
554 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
555 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
556 | * If we wait to unmask individual GPIO lines in the bank after the | |
557 | * line's interrupt handler has been run, we may miss some nested | |
558 | * interrupts. | |
559 | */ | |
450fa54c | 560 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 561 | { |
92105bb7 | 562 | void __iomem *isr_reg = NULL; |
395373c7 | 563 | u32 enabled, isr, edge; |
3513cdec | 564 | unsigned int bit; |
450fa54c GS |
565 | struct gpio_bank *bank = gpiobank; |
566 | unsigned long wa_lock_flags; | |
235f1eb1 | 567 | unsigned long lock_flags; |
5e1c5ff4 | 568 | |
eef4bec7 | 569 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
570 | if (WARN_ON(!isr_reg)) |
571 | goto exit; | |
572 | ||
5284521a TL |
573 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
574 | "gpio irq%i while runtime suspended?\n", irq)) | |
575 | return IRQ_NONE; | |
450fa54c | 576 | |
e83507b7 | 577 | while (1) { |
235f1eb1 GS |
578 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
579 | ||
a0e827c6 | 580 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 581 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 582 | |
395373c7 RK |
583 | /* |
584 | * Clear edge sensitive interrupts before calling handler(s) | |
585 | * so subsequent edge transitions are not missed while the | |
586 | * handlers are running. | |
587 | */ | |
588 | edge = isr & ~bank->level_mask; | |
589 | if (edge) | |
590 | omap_clear_gpio_irqbank(bank, edge); | |
6e60e79a | 591 | |
235f1eb1 GS |
592 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
593 | ||
92105bb7 TL |
594 | if (!isr) |
595 | break; | |
596 | ||
3513cdec JH |
597 | while (isr) { |
598 | bit = __ffs(isr); | |
b1e9fec2 | 599 | isr &= ~(BIT(bit)); |
25db711d | 600 | |
235f1eb1 | 601 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
602 | /* |
603 | * Some chips can't respond to both rising and falling | |
604 | * at the same time. If this irq was requested with | |
605 | * both flags, we need to flip the ICR data for the IRQ | |
606 | * to respond to the IRQ for the opposite direction. | |
607 | * This will be indicated in the bank toggle_mask. | |
608 | */ | |
b1e9fec2 | 609 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 610 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 611 | |
235f1eb1 GS |
612 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
613 | ||
450fa54c GS |
614 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
615 | ||
dbd1c54f | 616 | generic_handle_domain_irq(bank->chip.irq.domain, bit); |
450fa54c GS |
617 | |
618 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
619 | wa_lock_flags); | |
92105bb7 | 620 | } |
1a8bfa1e | 621 | } |
b1cc4c55 | 622 | exit: |
450fa54c | 623 | return IRQ_HANDLED; |
5e1c5ff4 TL |
624 | } |
625 | ||
3d009c8c TL |
626 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
627 | { | |
628 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 629 | unsigned long flags; |
37e14ecf | 630 | unsigned offset = d->hwirq; |
3d009c8c | 631 | |
4dbada2b | 632 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
633 | |
634 | if (!LINE_USED(bank->mod_usage, offset)) | |
635 | omap_set_gpio_direction(bank, offset, 1); | |
121dcb76 GS |
636 | omap_enable_gpio_module(bank, offset); |
637 | bank->irq_usage |= BIT(offset); | |
638 | ||
4dbada2b | 639 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
640 | omap_gpio_unmask_irq(d); |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
a0e827c6 | 645 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 646 | { |
a0e827c6 | 647 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 648 | unsigned long flags; |
9943f261 | 649 | unsigned offset = d->hwirq; |
4196dd6b | 650 | |
4dbada2b | 651 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 652 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 | 653 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 RK |
654 | omap_clear_gpio_irqstatus(bank, offset); |
655 | omap_set_gpio_irqenable(bank, offset, 0); | |
6e96c1b5 GS |
656 | if (!LINE_USED(bank->mod_usage, offset)) |
657 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 658 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 659 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
660 | } |
661 | ||
662 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
663 | { | |
664 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
665 | ||
46748073 | 666 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
667 | } |
668 | ||
669 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
670 | { | |
671 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 672 | |
46748073 | 673 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
674 | } |
675 | ||
a0e827c6 | 676 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 677 | { |
a0e827c6 | 678 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 679 | unsigned offset = d->hwirq; |
85ec7b97 | 680 | unsigned long flags; |
5e1c5ff4 | 681 | |
4dbada2b | 682 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 | 683 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
c859e0d4 | 684 | omap_set_gpio_irqenable(bank, offset, 0); |
4dbada2b | 685 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
39575d11 | 686 | gpiochip_disable_irq(&bank->chip, offset); |
5e1c5ff4 TL |
687 | } |
688 | ||
a0e827c6 | 689 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 690 | { |
a0e827c6 | 691 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 692 | unsigned offset = d->hwirq; |
8c04a176 | 693 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 694 | unsigned long flags; |
55b6019a | 695 | |
39575d11 | 696 | gpiochip_enable_irq(&bank->chip, offset); |
4dbada2b | 697 | raw_spin_lock_irqsave(&bank->lock, flags); |
d01849f7 RK |
698 | omap_set_gpio_irqenable(bank, offset, 1); |
699 | ||
700 | /* | |
701 | * For level-triggered GPIOs, clearing must be done after the source | |
702 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
703 | * after enabing the interrupt to clear the wakeup status. | |
704 | */ | |
c859e0d4 RK |
705 | if (bank->regs->leveldetect0 && bank->regs->wkup_en && |
706 | trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
9943f261 | 707 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 708 | |
c859e0d4 RK |
709 | if (trigger) |
710 | omap_set_gpio_triggering(bank, offset, trigger); | |
711 | ||
4dbada2b | 712 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
713 | } |
714 | ||
39575d11 LW |
715 | static void omap_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) |
716 | { | |
717 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
718 | ||
719 | seq_printf(p, dev_name(bank->dev)); | |
720 | } | |
721 | ||
722 | static const struct irq_chip omap_gpio_irq_chip = { | |
723 | .irq_startup = omap_gpio_irq_startup, | |
724 | .irq_shutdown = omap_gpio_irq_shutdown, | |
725 | .irq_mask = omap_gpio_mask_irq, | |
726 | .irq_unmask = omap_gpio_unmask_irq, | |
727 | .irq_set_type = omap_gpio_irq_type, | |
728 | .irq_set_wake = omap_gpio_wake_enable, | |
729 | .irq_bus_lock = omap_gpio_irq_bus_lock, | |
730 | .irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
731 | .irq_print_chip = omap_gpio_irq_print_chip, | |
732 | .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, | |
733 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
734 | }; | |
735 | ||
736 | static const struct irq_chip omap_gpio_irq_chip_nowake = { | |
737 | .irq_startup = omap_gpio_irq_startup, | |
738 | .irq_shutdown = omap_gpio_irq_shutdown, | |
739 | .irq_mask = omap_gpio_mask_irq, | |
740 | .irq_unmask = omap_gpio_unmask_irq, | |
741 | .irq_set_type = omap_gpio_irq_type, | |
742 | .irq_bus_lock = omap_gpio_irq_bus_lock, | |
743 | .irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
744 | .irq_print_chip = omap_gpio_irq_print_chip, | |
745 | .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, | |
746 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
747 | }; | |
748 | ||
e5c56ed3 DB |
749 | /*---------------------------------------------------------------------*/ |
750 | ||
79ee031f | 751 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 752 | { |
a3f4f728 | 753 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
754 | void __iomem *mask_reg = bank->base + |
755 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 756 | unsigned long flags; |
11a78b79 | 757 | |
4dbada2b | 758 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 759 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 760 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
761 | |
762 | return 0; | |
763 | } | |
764 | ||
79ee031f | 765 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 766 | { |
a3f4f728 | 767 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
768 | void __iomem *mask_reg = bank->base + |
769 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 770 | unsigned long flags; |
11a78b79 | 771 | |
4dbada2b | 772 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 773 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 774 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
775 | |
776 | return 0; | |
777 | } | |
778 | ||
47145210 | 779 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
780 | .suspend_noirq = omap_mpuio_suspend_noirq, |
781 | .resume_noirq = omap_mpuio_resume_noirq, | |
782 | }; | |
783 | ||
3c437ffd | 784 | /* use platform_driver for this. */ |
11a78b79 | 785 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
786 | .driver = { |
787 | .name = "mpuio", | |
79ee031f | 788 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
789 | }, |
790 | }; | |
791 | ||
792 | static struct platform_device omap_mpuio_device = { | |
793 | .name = "mpuio", | |
794 | .id = -1, | |
795 | .dev = { | |
796 | .driver = &omap_mpuio_driver.driver, | |
797 | } | |
798 | /* could list the /proc/iomem resources */ | |
799 | }; | |
800 | ||
a0e827c6 | 801 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 802 | { |
77640aab | 803 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 804 | |
11a78b79 DB |
805 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
806 | (void) platform_device_register(&omap_mpuio_device); | |
807 | } | |
808 | ||
e5c56ed3 | 809 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 810 | |
dfbc6c7a | 811 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
9370084e | 812 | { |
dfbc6c7a RK |
813 | struct gpio_bank *bank = gpiochip_get_data(chip); |
814 | unsigned long flags; | |
815 | ||
816 | pm_runtime_get_sync(chip->parent); | |
817 | ||
818 | raw_spin_lock_irqsave(&bank->lock, flags); | |
819 | omap_enable_gpio_module(bank, offset); | |
820 | bank->mod_usage |= BIT(offset); | |
821 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
826 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |
827 | { | |
828 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
9370084e | 829 | unsigned long flags; |
9370084e | 830 | |
4dbada2b | 831 | raw_spin_lock_irqsave(&bank->lock, flags); |
dfbc6c7a RK |
832 | bank->mod_usage &= ~(BIT(offset)); |
833 | if (!LINE_USED(bank->irq_usage, offset)) { | |
834 | omap_set_gpio_direction(bank, offset, 1); | |
835 | omap_clear_gpio_debounce(bank, offset); | |
836 | } | |
837 | omap_disable_gpio_module(bank, offset); | |
4dbada2b | 838 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
dfbc6c7a RK |
839 | |
840 | pm_runtime_put(chip->parent); | |
841 | } | |
842 | ||
a0e827c6 | 843 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e | 844 | { |
40bb2273 | 845 | struct gpio_bank *bank = gpiochip_get_data(chip); |
9370084e | 846 | |
e42615ec MV |
847 | if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset)) |
848 | return GPIO_LINE_DIRECTION_IN; | |
849 | ||
850 | return GPIO_LINE_DIRECTION_OUT; | |
9370084e YY |
851 | } |
852 | ||
a0e827c6 | 853 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
854 | { |
855 | struct gpio_bank *bank; | |
856 | unsigned long flags; | |
857 | ||
d99f7aec | 858 | bank = gpiochip_get_data(chip); |
4dbada2b | 859 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 860 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 861 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
862 | return 0; |
863 | } | |
864 | ||
a0e827c6 | 865 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 866 | { |
5ca5f92c RK |
867 | struct gpio_bank *bank = gpiochip_get_data(chip); |
868 | void __iomem *reg; | |
b37c45b8 | 869 | |
b2b20045 | 870 | if (omap_gpio_is_input(bank, offset)) |
5ca5f92c | 871 | reg = bank->base + bank->regs->datain; |
b37c45b8 | 872 | else |
5ca5f92c RK |
873 | reg = bank->base + bank->regs->dataout; |
874 | ||
875 | return (readl_relaxed(reg) & BIT(offset)) != 0; | |
52e31344 DB |
876 | } |
877 | ||
a0e827c6 | 878 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
879 | { |
880 | struct gpio_bank *bank; | |
881 | unsigned long flags; | |
882 | ||
d99f7aec | 883 | bank = gpiochip_get_data(chip); |
4dbada2b | 884 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 885 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 886 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 887 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 888 | return 0; |
52e31344 DB |
889 | } |
890 | ||
442af140 JK |
891 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
892 | unsigned long *bits) | |
893 | { | |
894 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
6653dd88 RK |
895 | void __iomem *base = bank->base; |
896 | u32 direction, m, val = 0; | |
442af140 | 897 | |
6653dd88 | 898 | direction = readl_relaxed(base + bank->regs->direction); |
442af140 | 899 | |
6653dd88 RK |
900 | m = direction & *mask; |
901 | if (m) | |
902 | val |= readl_relaxed(base + bank->regs->datain) & m; | |
442af140 | 903 | |
6653dd88 RK |
904 | m = ~direction & *mask; |
905 | if (m) | |
906 | val |= readl_relaxed(base + bank->regs->dataout) & m; | |
442af140 | 907 | |
6653dd88 | 908 | *bits = val; |
442af140 JK |
909 | |
910 | return 0; | |
911 | } | |
912 | ||
a0e827c6 JMC |
913 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
914 | unsigned debounce) | |
168ef3d9 FB |
915 | { |
916 | struct gpio_bank *bank; | |
917 | unsigned long flags; | |
83977443 | 918 | int ret; |
168ef3d9 | 919 | |
d99f7aec | 920 | bank = gpiochip_get_data(chip); |
77640aab | 921 | |
4dbada2b | 922 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 923 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 924 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 925 | |
83977443 DR |
926 | if (ret) |
927 | dev_info(chip->parent, | |
928 | "Could not set line %u debounce to %u microseconds (%d)", | |
929 | offset, debounce, ret); | |
930 | ||
931 | return ret; | |
168ef3d9 FB |
932 | } |
933 | ||
2956b5d9 MW |
934 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
935 | unsigned long config) | |
936 | { | |
937 | u32 debounce; | |
75dec567 DF |
938 | int ret = -ENOTSUPP; |
939 | ||
bde8c0e6 DF |
940 | switch (pinconf_to_config_param(config)) { |
941 | case PIN_CONFIG_BIAS_DISABLE: | |
942 | case PIN_CONFIG_BIAS_PULL_UP: | |
943 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
75dec567 | 944 | ret = gpiochip_generic_config(chip, offset, config); |
bde8c0e6 DF |
945 | break; |
946 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
75dec567 DF |
947 | debounce = pinconf_to_config_argument(config); |
948 | ret = omap_gpio_debounce(chip, offset, debounce); | |
bde8c0e6 DF |
949 | break; |
950 | default: | |
951 | break; | |
75dec567 | 952 | } |
2956b5d9 | 953 | |
75dec567 | 954 | return ret; |
2956b5d9 MW |
955 | } |
956 | ||
a0e827c6 | 957 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
958 | { |
959 | struct gpio_bank *bank; | |
960 | unsigned long flags; | |
961 | ||
d99f7aec | 962 | bank = gpiochip_get_data(chip); |
4dbada2b | 963 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 964 | bank->set_dataout(bank, offset, value); |
4dbada2b | 965 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
966 | } |
967 | ||
442af140 JK |
968 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
969 | unsigned long *bits) | |
970 | { | |
971 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
8ba70595 | 972 | void __iomem *reg = bank->base + bank->regs->dataout; |
442af140 | 973 | unsigned long flags; |
8ba70595 | 974 | u32 l; |
442af140 JK |
975 | |
976 | raw_spin_lock_irqsave(&bank->lock, flags); | |
8ba70595 RK |
977 | l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); |
978 | writel_relaxed(l, reg); | |
979 | bank->context.dataout = l; | |
442af140 JK |
980 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
981 | } | |
982 | ||
52e31344 DB |
983 | /*---------------------------------------------------------------------*/ |
984 | ||
e4b2ae7a | 985 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 986 | { |
e5ff4440 | 987 | static bool called; |
9f7065da TL |
988 | u32 rev; |
989 | ||
e5ff4440 | 990 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
991 | return; |
992 | ||
661553b9 | 993 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 994 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 995 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
996 | |
997 | called = true; | |
9f7065da TL |
998 | } |
999 | ||
03e128ca | 1000 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1001 | { |
ab985f0f TKD |
1002 | void __iomem *base = bank->base; |
1003 | u32 l = 0xffffffff; | |
2fae7fbe | 1004 | |
ab985f0f TKD |
1005 | if (bank->width == 16) |
1006 | l = 0xffff; | |
1007 | ||
d0d665a8 | 1008 | if (bank->is_mpuio) { |
661553b9 | 1009 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1010 | return; |
2fae7fbe | 1011 | } |
ab985f0f | 1012 | |
8ee1de65 | 1013 | omap_gpio_rmw(base + bank->regs->irqenable, l, |
a0e827c6 | 1014 | bank->regs->irqenable_inv); |
8ee1de65 | 1015 | omap_gpio_rmw(base + bank->regs->irqstatus, l, |
a0e827c6 | 1016 | !bank->regs->irqenable_inv); |
ab985f0f | 1017 | if (bank->regs->debounce_en) |
661553b9 | 1018 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1019 | |
2dc983c5 | 1020 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1021 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1022 | /* Initialize interface clk ungated, module enabled */ |
1023 | if (bank->regs->ctrl) | |
661553b9 | 1024 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1025 | } |
1026 | ||
39575d11 | 1027 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev) |
2fae7fbe | 1028 | { |
81930328 | 1029 | struct gpio_irq_chip *irq; |
2fae7fbe | 1030 | static int gpio; |
088413bc | 1031 | const char *label; |
6ef7f385 | 1032 | int ret; |
2fae7fbe | 1033 | |
2fae7fbe VC |
1034 | /* |
1035 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1036 | * over to the generic ones | |
1037 | */ | |
1038 | bank->chip.request = omap_gpio_request; | |
1039 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1040 | bank->chip.get_direction = omap_gpio_get_direction; |
1041 | bank->chip.direction_input = omap_gpio_input; | |
1042 | bank->chip.get = omap_gpio_get; | |
442af140 | 1043 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1044 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1045 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1046 | bank->chip.set = omap_gpio_set; |
442af140 | 1047 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1048 | if (bank->is_mpuio) { |
2fae7fbe | 1049 | bank->chip.label = "mpuio"; |
6ed87c5b | 1050 | if (bank->regs->wkup_en) |
58383c78 | 1051 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1052 | bank->chip.base = OMAP_MPUIO(0); |
1053 | } else { | |
088413bc LW |
1054 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1055 | gpio, gpio + bank->width - 1); | |
1056 | if (!label) | |
1057 | return -ENOMEM; | |
1058 | bank->chip.label = label; | |
92bf78b3 | 1059 | bank->chip.base = -1; |
2fae7fbe | 1060 | } |
d5f46247 | 1061 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1062 | |
39575d11 | 1063 | irq = &bank->chip.irq; |
d2d05c65 | 1064 | /* MPUIO is a bit different, reading IRQ status clears it */ |
693de831 | 1065 | if (bank->is_mpuio && !bank->regs->wkup_en) |
39575d11 LW |
1066 | gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip_nowake); |
1067 | else | |
1068 | gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip); | |
81930328 GS |
1069 | irq->handler = handle_bad_irq; |
1070 | irq->default_type = IRQ_TYPE_NONE; | |
1071 | irq->num_parents = 1; | |
1072 | irq->parents = &bank->irq; | |
fb655f57 | 1073 | |
81930328 | 1074 | ret = gpiochip_add_data(&bank->chip, bank); |
2ae136a3 GS |
1075 | if (ret) |
1076 | return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n"); | |
fb655f57 | 1077 | |
989c78f2 | 1078 | irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev); |
7b1e5dc8 GS |
1079 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1080 | omap_gpio_irq_handler, | |
1081 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1082 | if (ret) |
1083 | gpiochip_remove(&bank->chip); | |
1084 | ||
81930328 GS |
1085 | if (!bank->is_mpuio) |
1086 | gpio += bank->width; | |
1087 | ||
450fa54c | 1088 | return ret; |
2fae7fbe VC |
1089 | } |
1090 | ||
7c68571f | 1091 | static void omap_gpio_init_context(struct gpio_bank *p) |
b764a586 | 1092 | { |
18bd49c4 | 1093 | const struct omap_gpio_reg_offs *regs = p->regs; |
7c68571f | 1094 | void __iomem *base = p->base; |
b764a586 | 1095 | |
ddd8d94c | 1096 | p->context.sysconfig = readl_relaxed(base + regs->sysconfig); |
7c68571f AB |
1097 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1098 | p->context.oe = readl_relaxed(base + regs->direction); | |
1099 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1100 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1101 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1102 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1103 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1104 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1105 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
9a302781 | 1106 | p->context.dataout = readl_relaxed(base + regs->dataout); |
b764a586 | 1107 | |
7c68571f | 1108 | p->context_valid = true; |
b764a586 TL |
1109 | } |
1110 | ||
7c68571f | 1111 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
5e1c5ff4 | 1112 | { |
18bd49c4 | 1113 | const struct omap_gpio_reg_offs *regs = bank->regs; |
9c7f798d RK |
1114 | void __iomem *base = bank->base; |
1115 | ||
ddd8d94c | 1116 | writel_relaxed(bank->context.sysconfig, base + regs->sysconfig); |
9c7f798d RK |
1117 | writel_relaxed(bank->context.wake_en, base + regs->wkup_en); |
1118 | writel_relaxed(bank->context.ctrl, base + regs->ctrl); | |
1119 | writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); | |
1120 | writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); | |
1121 | writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); | |
1122 | writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); | |
1123 | writel_relaxed(bank->context.dataout, base + regs->dataout); | |
1124 | writel_relaxed(bank->context.oe, base + regs->direction); | |
9f7065da | 1125 | |
7c68571f | 1126 | if (bank->dbck_enable_mask) { |
9c7f798d | 1127 | writel_relaxed(bank->context.debounce, base + regs->debounce); |
7c68571f | 1128 | writel_relaxed(bank->context.debounce_en, |
9c7f798d | 1129 | base + regs->debounce_en); |
b764a586 TL |
1130 | } |
1131 | ||
9c7f798d RK |
1132 | writel_relaxed(bank->context.irqenable1, base + regs->irqenable); |
1133 | writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); | |
cac089f9 TL |
1134 | } |
1135 | ||
b764a586 | 1136 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1137 | { |
b764a586 | 1138 | struct device *dev = bank->chip.parent; |
21e2118f | 1139 | void __iomem *base = bank->base; |
7ffa0816 | 1140 | u32 mask, nowake; |
21e2118f TL |
1141 | |
1142 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1143 | |
ddd8d94c TL |
1144 | /* Save syconfig, it's runtime value can be different from init value */ |
1145 | if (bank->loses_context) | |
1146 | bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig); | |
1147 | ||
b3c64bc3 KH |
1148 | if (!bank->enabled_non_wakeup_gpios) |
1149 | goto update_gpio_context_count; | |
1150 | ||
7ffa0816 TL |
1151 | /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */ |
1152 | mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; | |
1153 | mask &= ~bank->context.risingdetect; | |
1154 | bank->saved_datain |= mask; | |
1155 | ||
1156 | /* Check for pending EDGE_RISING, ignore EDGE_BOTH */ | |
1157 | mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; | |
1158 | mask &= ~bank->context.fallingdetect; | |
1159 | bank->saved_datain &= ~mask; | |
1160 | ||
b764a586 | 1161 | if (!may_lose_context) |
41d87cbd | 1162 | goto update_gpio_context_count; |
b764a586 | 1163 | |
2dc983c5 | 1164 | /* |
21e2118f | 1165 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1166 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1167 | * generated. See OMAP2420 Errata item 1.101. | |
1168 | */ | |
21e2118f TL |
1169 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1170 | nowake = bank->enabled_non_wakeup_gpios; | |
8ee1de65 RK |
1171 | omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); |
1172 | omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); | |
21e2118f | 1173 | } |
3f1686a9 | 1174 | |
41d87cbd | 1175 | update_gpio_context_count: |
2dc983c5 TKD |
1176 | if (bank->get_context_loss_count) |
1177 | bank->context_loss_count = | |
7b1e5dc8 | 1178 | bank->get_context_loss_count(dev); |
60a3437d | 1179 | |
a0e827c6 | 1180 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1181 | } |
1182 | ||
b764a586 | 1183 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1184 | { |
b764a586 | 1185 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1186 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1187 | int c; |
8865b9b6 | 1188 | |
352a2d5b JH |
1189 | /* |
1190 | * On the first resume during the probe, the context has not | |
1191 | * been initialised and so initialise it now. Also initialise | |
1192 | * the context loss count. | |
1193 | */ | |
1194 | if (bank->loses_context && !bank->context_valid) { | |
1195 | omap_gpio_init_context(bank); | |
1196 | ||
1197 | if (bank->get_context_loss_count) | |
1198 | bank->context_loss_count = | |
7b1e5dc8 | 1199 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1200 | } |
1201 | ||
a0e827c6 | 1202 | omap_gpio_dbck_enable(bank); |
68942edb | 1203 | |
a2797bea JH |
1204 | if (bank->loses_context) { |
1205 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1206 | omap_gpio_restore_context(bank); |
1207 | } else { | |
7b1e5dc8 | 1208 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1209 | if (c != bank->context_loss_count) { |
1210 | omap_gpio_restore_context(bank); | |
1211 | } else { | |
b764a586 | 1212 | return; |
a2797bea | 1213 | } |
60a3437d | 1214 | } |
21e2118f TL |
1215 | } else { |
1216 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1217 | writel_relaxed(bank->context.fallingdetect, | |
1218 | bank->base + bank->regs->fallingdetect); | |
1219 | writel_relaxed(bank->context.risingdetect, | |
1220 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1221 | } |
43ffcd9a | 1222 | |
661553b9 | 1223 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1224 | |
2dc983c5 TKD |
1225 | /* |
1226 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1227 | * state. If so, generate an IRQ by software. This is | |
1228 | * horribly racy, but it's the best we can do to work around | |
1229 | * this silicon bug. | |
1230 | */ | |
1231 | l ^= bank->saved_datain; | |
1232 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1233 | |
2dc983c5 TKD |
1234 | /* |
1235 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1236 | * configured with falling edge only; and vice versa. | |
1237 | */ | |
c6f31c9e | 1238 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1239 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1240 | |
c6f31c9e | 1241 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1242 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1243 | |
2dc983c5 | 1244 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1245 | gen = l & (~(bank->context.fallingdetect) & |
1246 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1247 | /* Consider all GPIO IRQs needed to be updated */ |
1248 | gen |= gen0 | gen1; | |
82dbb9d3 | 1249 | |
2dc983c5 TKD |
1250 | if (gen) { |
1251 | u32 old0, old1; | |
82dbb9d3 | 1252 | |
661553b9 VK |
1253 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1254 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1255 | |
4e962e89 | 1256 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1257 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1258 | bank->regs->leveldetect0); |
661553b9 | 1259 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1260 | bank->regs->leveldetect1); |
2dc983c5 | 1261 | } |
9ea14d8c | 1262 | |
4e962e89 | 1263 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1264 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1265 | bank->regs->leveldetect0); |
661553b9 | 1266 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1267 | bank->regs->leveldetect1); |
3ac4fa99 | 1268 | } |
661553b9 VK |
1269 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1270 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1271 | } |
2dc983c5 | 1272 | } |
2dc983c5 | 1273 | |
7c68571f AB |
1274 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, |
1275 | unsigned long cmd, void *v) | |
352a2d5b | 1276 | { |
7c68571f AB |
1277 | struct gpio_bank *bank; |
1278 | unsigned long flags; | |
43582265 TL |
1279 | int ret = NOTIFY_OK; |
1280 | u32 isr, mask; | |
352a2d5b | 1281 | |
7c68571f | 1282 | bank = container_of(nb, struct gpio_bank, nb); |
352a2d5b | 1283 | |
7c68571f | 1284 | raw_spin_lock_irqsave(&bank->lock, flags); |
43582265 TL |
1285 | if (bank->is_suspended) |
1286 | goto out_unlock; | |
1287 | ||
7c68571f AB |
1288 | switch (cmd) { |
1289 | case CPU_CLUSTER_PM_ENTER: | |
43582265 TL |
1290 | mask = omap_get_gpio_irqbank_mask(bank); |
1291 | isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask; | |
1292 | if (isr) { | |
1293 | ret = NOTIFY_BAD; | |
7c68571f | 1294 | break; |
43582265 | 1295 | } |
7c68571f AB |
1296 | omap_gpio_idle(bank, true); |
1297 | break; | |
1298 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1299 | case CPU_CLUSTER_PM_EXIT: | |
7c68571f AB |
1300 | omap_gpio_unidle(bank); |
1301 | break; | |
1302 | } | |
43582265 TL |
1303 | |
1304 | out_unlock: | |
7c68571f | 1305 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
352a2d5b | 1306 | |
43582265 | 1307 | return ret; |
b764a586 TL |
1308 | } |
1309 | ||
18bd49c4 | 1310 | static const struct omap_gpio_reg_offs omap2_gpio_regs = { |
384ebe1c | 1311 | .revision = OMAP24XX_GPIO_REVISION, |
ddd8d94c | 1312 | .sysconfig = OMAP24XX_GPIO_SYSCONFIG, |
384ebe1c BC |
1313 | .direction = OMAP24XX_GPIO_OE, |
1314 | .datain = OMAP24XX_GPIO_DATAIN, | |
1315 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1316 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1317 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1318 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1319 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1320 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1321 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1322 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1323 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1324 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1325 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1326 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1327 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1328 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1329 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1330 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1331 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1332 | }; | |
1333 | ||
18bd49c4 | 1334 | static const struct omap_gpio_reg_offs omap4_gpio_regs = { |
384ebe1c | 1335 | .revision = OMAP4_GPIO_REVISION, |
ddd8d94c | 1336 | .sysconfig = OMAP4_GPIO_SYSCONFIG, |
384ebe1c BC |
1337 | .direction = OMAP4_GPIO_OE, |
1338 | .datain = OMAP4_GPIO_DATAIN, | |
1339 | .dataout = OMAP4_GPIO_DATAOUT, | |
1340 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1341 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1342 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1343 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
64ea3e90 RK |
1344 | .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, |
1345 | .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, | |
384ebe1c BC |
1346 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, |
1347 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1348 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1349 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1350 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1351 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1352 | .ctrl = OMAP4_GPIO_CTRL, | |
1353 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1354 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1355 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1356 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1357 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1358 | }; | |
1359 | ||
e9a65bb6 | 1360 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1361 | .regs = &omap2_gpio_regs, |
1362 | .bank_width = 32, | |
1363 | .dbck_flag = false, | |
1364 | }; | |
1365 | ||
e9a65bb6 | 1366 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1367 | .regs = &omap2_gpio_regs, |
1368 | .bank_width = 32, | |
1369 | .dbck_flag = true, | |
1370 | }; | |
1371 | ||
e9a65bb6 | 1372 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1373 | .regs = &omap4_gpio_regs, |
1374 | .bank_width = 32, | |
1375 | .dbck_flag = true, | |
1376 | }; | |
1377 | ||
1378 | static const struct of_device_id omap_gpio_match[] = { | |
1379 | { | |
1380 | .compatible = "ti,omap4-gpio", | |
1381 | .data = &omap4_pdata, | |
1382 | }, | |
1383 | { | |
1384 | .compatible = "ti,omap3-gpio", | |
1385 | .data = &omap3_pdata, | |
1386 | }, | |
1387 | { | |
1388 | .compatible = "ti,omap2-gpio", | |
1389 | .data = &omap2_pdata, | |
1390 | }, | |
1391 | { }, | |
1392 | }; | |
1393 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
7c68571f AB |
1394 | |
1395 | static int omap_gpio_probe(struct platform_device *pdev) | |
1396 | { | |
1397 | struct device *dev = &pdev->dev; | |
1398 | struct device_node *node = dev->of_node; | |
7c68571f | 1399 | const struct omap_gpio_platform_data *pdata; |
7c68571f | 1400 | struct gpio_bank *bank; |
7c68571f AB |
1401 | int ret; |
1402 | ||
ca40daf3 | 1403 | pdata = device_get_match_data(dev); |
7c68571f | 1404 | |
ca40daf3 | 1405 | pdata = pdata ?: dev_get_platdata(dev); |
7c68571f AB |
1406 | if (!pdata) |
1407 | return -EINVAL; | |
1408 | ||
1409 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
1410 | if (!bank) | |
1411 | return -ENOMEM; | |
1412 | ||
39575d11 | 1413 | bank->dev = dev; |
7c68571f AB |
1414 | |
1415 | bank->irq = platform_get_irq(pdev, 0); | |
1416 | if (bank->irq <= 0) { | |
1417 | if (!bank->irq) | |
1418 | bank->irq = -ENXIO; | |
4e7ed696 | 1419 | return dev_err_probe(dev, bank->irq, "can't get irq resource\n"); |
7c68571f AB |
1420 | } |
1421 | ||
1422 | bank->chip.parent = dev; | |
1423 | bank->chip.owner = THIS_MODULE; | |
1424 | bank->dbck_flag = pdata->dbck_flag; | |
7c68571f AB |
1425 | bank->stride = pdata->bank_stride; |
1426 | bank->width = pdata->bank_width; | |
1427 | bank->is_mpuio = pdata->is_mpuio; | |
1428 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; | |
1429 | bank->regs = pdata->regs; | |
384ebe1c | 1430 | |
7c68571f AB |
1431 | if (node) { |
1432 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1433 | bank->loses_context = true; | |
1434 | } else { | |
1435 | bank->loses_context = pdata->loses_context; | |
1436 | ||
1437 | if (bank->loses_context) | |
1438 | bank->get_context_loss_count = | |
1439 | pdata->get_context_loss_count; | |
1440 | } | |
1441 | ||
8ba70595 | 1442 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
7c68571f | 1443 | bank->set_dataout = omap_set_gpio_dataout_reg; |
8ba70595 | 1444 | else |
7c68571f | 1445 | bank->set_dataout = omap_set_gpio_dataout_mask; |
7c68571f | 1446 | |
7c68571f AB |
1447 | raw_spin_lock_init(&bank->lock); |
1448 | raw_spin_lock_init(&bank->wa_lock); | |
1449 | ||
1450 | /* Static mapping, never released */ | |
58f57f86 | 1451 | bank->base = devm_platform_ioremap_resource(pdev, 0); |
7c68571f AB |
1452 | if (IS_ERR(bank->base)) { |
1453 | return PTR_ERR(bank->base); | |
1454 | } | |
1455 | ||
1456 | if (bank->dbck_flag) { | |
1457 | bank->dbck = devm_clk_get(dev, "dbclk"); | |
1458 | if (IS_ERR(bank->dbck)) { | |
1459 | dev_err(dev, | |
1460 | "Could not get gpio dbck. Disable debounce\n"); | |
1461 | bank->dbck_flag = false; | |
1462 | } else { | |
1463 | clk_prepare(bank->dbck); | |
1464 | } | |
1465 | } | |
1466 | ||
1467 | platform_set_drvdata(pdev, bank); | |
1468 | ||
1469 | pm_runtime_enable(dev); | |
1470 | pm_runtime_get_sync(dev); | |
1471 | ||
1472 | if (bank->is_mpuio) | |
1473 | omap_mpuio_init(bank); | |
1474 | ||
1475 | omap_gpio_mod_init(bank); | |
1476 | ||
39575d11 | 1477 | ret = omap_gpio_chip_init(bank, dev); |
7c68571f AB |
1478 | if (ret) { |
1479 | pm_runtime_put_sync(dev); | |
1480 | pm_runtime_disable(dev); | |
1481 | if (bank->dbck_flag) | |
1482 | clk_unprepare(bank->dbck); | |
1483 | return ret; | |
1484 | } | |
1485 | ||
1486 | omap_gpio_show_rev(bank); | |
1487 | ||
e6818d29 RK |
1488 | bank->nb.notifier_call = gpio_omap_cpu_notifier; |
1489 | cpu_pm_register_notifier(&bank->nb); | |
7c68571f AB |
1490 | |
1491 | pm_runtime_put(dev); | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | static int omap_gpio_remove(struct platform_device *pdev) | |
1497 | { | |
1498 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1499 | ||
e6818d29 | 1500 | cpu_pm_unregister_notifier(&bank->nb); |
7c68571f AB |
1501 | gpiochip_remove(&bank->chip); |
1502 | pm_runtime_disable(&pdev->dev); | |
1503 | if (bank->dbck_flag) | |
1504 | clk_unprepare(bank->dbck); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) | |
1510 | { | |
1511 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1512 | unsigned long flags; | |
7c68571f AB |
1513 | |
1514 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1515 | omap_gpio_idle(bank, true); |
1516 | bank->is_suspended = true; | |
7c68571f AB |
1517 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1518 | ||
044e499a | 1519 | return 0; |
7c68571f AB |
1520 | } |
1521 | ||
1522 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1523 | { | |
1524 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1525 | unsigned long flags; | |
7c68571f AB |
1526 | |
1527 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1528 | omap_gpio_unidle(bank); |
1529 | bank->is_suspended = false; | |
7c68571f AB |
1530 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1531 | ||
044e499a | 1532 | return 0; |
7c68571f AB |
1533 | } |
1534 | ||
d3f99f91 | 1535 | static int __maybe_unused omap_gpio_suspend(struct device *dev) |
f02a0398 TL |
1536 | { |
1537 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1538 | ||
1539 | if (bank->is_suspended) | |
1540 | return 0; | |
1541 | ||
1542 | bank->needs_resume = 1; | |
1543 | ||
1544 | return omap_gpio_runtime_suspend(dev); | |
1545 | } | |
1546 | ||
d3f99f91 | 1547 | static int __maybe_unused omap_gpio_resume(struct device *dev) |
f02a0398 TL |
1548 | { |
1549 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1550 | ||
1551 | if (!bank->needs_resume) | |
1552 | return 0; | |
1553 | ||
1554 | bank->needs_resume = 0; | |
1555 | ||
1556 | return omap_gpio_runtime_resume(dev); | |
1557 | } | |
1558 | ||
7c68571f AB |
1559 | static const struct dev_pm_ops gpio_pm_ops = { |
1560 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, | |
1561 | NULL) | |
f02a0398 | 1562 | SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) |
7c68571f AB |
1563 | }; |
1564 | ||
77640aab VC |
1565 | static struct platform_driver omap_gpio_driver = { |
1566 | .probe = omap_gpio_probe, | |
cac089f9 | 1567 | .remove = omap_gpio_remove, |
77640aab VC |
1568 | .driver = { |
1569 | .name = "omap_gpio", | |
55b93c32 | 1570 | .pm = &gpio_pm_ops, |
7c68571f | 1571 | .of_match_table = omap_gpio_match, |
77640aab VC |
1572 | }, |
1573 | }; | |
1574 | ||
5e1c5ff4 | 1575 | /* |
77640aab VC |
1576 | * gpio driver register needs to be done before |
1577 | * machine_init functions access gpio APIs. | |
1578 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1579 | */ |
77640aab | 1580 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1581 | { |
77640aab | 1582 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1583 | } |
77640aab | 1584 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1585 | |
1586 | static void __exit omap_gpio_exit(void) | |
1587 | { | |
1588 | platform_driver_unregister(&omap_gpio_driver); | |
1589 | } | |
1590 | module_exit(omap_gpio_exit); | |
1591 | ||
1592 | MODULE_DESCRIPTION("omap gpio driver"); | |
1593 | MODULE_ALIAS("platform:gpio-omap"); | |
1594 | MODULE_LICENSE("GPL v2"); |