Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
b764a586 | 22 | #include <linux/cpu_pm.h> |
96751fcb | 23 | #include <linux/device.h> |
77640aab | 24 | #include <linux/pm_runtime.h> |
55b93c32 | 25 | #include <linux/pm.h> |
384ebe1c BC |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
b7351b07 | 28 | #include <linux/gpio/driver.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
b764a586 | 34 | #define OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER BIT(2) |
ec0daae6 TL |
35 | #define OMAP_GPIO_QUIRK_DEFERRED_WKUP_EN BIT(1) |
36 | ||
6d62e216 C |
37 | struct gpio_regs { |
38 | u32 irqenable1; | |
39 | u32 irqenable2; | |
40 | u32 wake_en; | |
41 | u32 ctrl; | |
42 | u32 oe; | |
43 | u32 leveldetect0; | |
44 | u32 leveldetect1; | |
45 | u32 risingdetect; | |
46 | u32 fallingdetect; | |
47 | u32 dataout; | |
ae547354 NM |
48 | u32 debounce; |
49 | u32 debounce_en; | |
6d62e216 C |
50 | }; |
51 | ||
ec0daae6 TL |
52 | struct gpio_bank; |
53 | ||
54 | struct gpio_omap_funcs { | |
55 | void (*idle_enable_level_quirk)(struct gpio_bank *bank); | |
56 | void (*idle_disable_level_quirk)(struct gpio_bank *bank); | |
57 | }; | |
58 | ||
5e1c5ff4 | 59 | struct gpio_bank { |
03e128ca | 60 | struct list_head node; |
92105bb7 | 61 | void __iomem *base; |
30cefeac | 62 | int irq; |
3ac4fa99 JY |
63 | u32 non_wakeup_gpios; |
64 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 65 | struct gpio_regs context; |
ec0daae6 | 66 | struct gpio_omap_funcs funcs; |
3ac4fa99 | 67 | u32 saved_datain; |
b144ff6f | 68 | u32 level_mask; |
4318f36b | 69 | u32 toggle_mask; |
4dbada2b | 70 | raw_spinlock_t lock; |
450fa54c | 71 | raw_spinlock_t wa_lock; |
52e31344 | 72 | struct gpio_chip chip; |
89db9482 | 73 | struct clk *dbck; |
b764a586 TL |
74 | struct notifier_block nb; |
75 | unsigned int is_suspended:1; | |
058af1ea | 76 | u32 mod_usage; |
fa365e4d | 77 | u32 irq_usage; |
8865b9b6 | 78 | u32 dbck_enable_mask; |
72f83af9 | 79 | bool dbck_enabled; |
d0d665a8 | 80 | bool is_mpuio; |
77640aab | 81 | bool dbck_flag; |
0cde8d03 | 82 | bool loses_context; |
352a2d5b | 83 | bool context_valid; |
5de62b86 | 84 | int stride; |
d5f46247 | 85 | u32 width; |
60a3437d | 86 | int context_loss_count; |
2dc983c5 | 87 | bool workaround_enabled; |
ec0daae6 | 88 | u32 quirks; |
fa87931a | 89 | |
04ebcbd8 | 90 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
442af140 JK |
91 | void (*set_dataout_multiple)(struct gpio_bank *bank, |
92 | unsigned long *mask, unsigned long *bits); | |
60a3437d | 93 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
94 | |
95 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
96 | }; |
97 | ||
c8eef65a | 98 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 99 | |
fa365e4d | 100 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 101 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 102 | |
3d009c8c TL |
103 | static void omap_gpio_unmask_irq(struct irq_data *d); |
104 | ||
a0e827c6 | 105 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 106 | { |
fb655f57 | 107 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 108 | return gpiochip_get_data(chip); |
25db711d BC |
109 | } |
110 | ||
a0e827c6 JMC |
111 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
112 | int is_input) | |
5e1c5ff4 | 113 | { |
92105bb7 | 114 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
115 | u32 l; |
116 | ||
fa87931a | 117 | reg += bank->regs->direction; |
661553b9 | 118 | l = readl_relaxed(reg); |
5e1c5ff4 | 119 | if (is_input) |
b1e9fec2 | 120 | l |= BIT(gpio); |
5e1c5ff4 | 121 | else |
b1e9fec2 | 122 | l &= ~(BIT(gpio)); |
661553b9 | 123 | writel_relaxed(l, reg); |
41d87cbd | 124 | bank->context.oe = l; |
5e1c5ff4 TL |
125 | } |
126 | ||
fa87931a KH |
127 | |
128 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 129 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 130 | int enable) |
5e1c5ff4 | 131 | { |
92105bb7 | 132 | void __iomem *reg = bank->base; |
04ebcbd8 | 133 | u32 l = BIT(offset); |
5e1c5ff4 | 134 | |
2c836f7e | 135 | if (enable) { |
fa87931a | 136 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
137 | bank->context.dataout |= l; |
138 | } else { | |
fa87931a | 139 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
140 | bank->context.dataout &= ~l; |
141 | } | |
5e1c5ff4 | 142 | |
661553b9 | 143 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
144 | } |
145 | ||
fa87931a | 146 | /* set data out value using mask register */ |
04ebcbd8 | 147 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 148 | int enable) |
5e1c5ff4 | 149 | { |
fa87931a | 150 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 151 | u32 gpio_bit = BIT(offset); |
fa87931a | 152 | u32 l; |
5e1c5ff4 | 153 | |
661553b9 | 154 | l = readl_relaxed(reg); |
fa87931a KH |
155 | if (enable) |
156 | l |= gpio_bit; | |
157 | else | |
158 | l &= ~gpio_bit; | |
661553b9 | 159 | writel_relaxed(l, reg); |
41d87cbd | 160 | bank->context.dataout = l; |
5e1c5ff4 TL |
161 | } |
162 | ||
a0e827c6 | 163 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 164 | { |
fa87931a | 165 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 166 | |
b1e9fec2 | 167 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 168 | } |
b37c45b8 | 169 | |
a0e827c6 | 170 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 171 | { |
fa87931a | 172 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 173 | |
b1e9fec2 | 174 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
175 | } |
176 | ||
442af140 JK |
177 | /* set multiple data out values using dedicate set/clear register */ |
178 | static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, | |
179 | unsigned long *mask, | |
180 | unsigned long *bits) | |
181 | { | |
182 | void __iomem *reg = bank->base; | |
183 | u32 l; | |
184 | ||
185 | l = *bits & *mask; | |
186 | writel_relaxed(l, reg + bank->regs->set_dataout); | |
187 | bank->context.dataout |= l; | |
188 | ||
189 | l = ~*bits & *mask; | |
190 | writel_relaxed(l, reg + bank->regs->clr_dataout); | |
191 | bank->context.dataout &= ~l; | |
192 | } | |
193 | ||
194 | /* set multiple data out values using mask register */ | |
195 | static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, | |
196 | unsigned long *mask, | |
197 | unsigned long *bits) | |
198 | { | |
199 | void __iomem *reg = bank->base + bank->regs->dataout; | |
200 | u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); | |
201 | ||
202 | writel_relaxed(l, reg); | |
203 | bank->context.dataout = l; | |
204 | } | |
205 | ||
206 | static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank, | |
207 | unsigned long *mask) | |
208 | { | |
209 | void __iomem *reg = bank->base + bank->regs->datain; | |
210 | ||
211 | return readl_relaxed(reg) & *mask; | |
212 | } | |
213 | ||
214 | static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank, | |
215 | unsigned long *mask) | |
216 | { | |
217 | void __iomem *reg = bank->base + bank->regs->dataout; | |
218 | ||
219 | return readl_relaxed(reg) & *mask; | |
220 | } | |
221 | ||
a0e827c6 | 222 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 223 | { |
661553b9 | 224 | int l = readl_relaxed(base + reg); |
ece9528e | 225 | |
862ff640 | 226 | if (set) |
ece9528e KH |
227 | l |= mask; |
228 | else | |
229 | l &= ~mask; | |
230 | ||
661553b9 | 231 | writel_relaxed(l, base + reg); |
ece9528e | 232 | } |
92105bb7 | 233 | |
a0e827c6 | 234 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
235 | { |
236 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 237 | clk_enable(bank->dbck); |
72f83af9 | 238 | bank->dbck_enabled = true; |
9e303f22 | 239 | |
661553b9 | 240 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 241 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
242 | } |
243 | } | |
244 | ||
a0e827c6 | 245 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
246 | { |
247 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
248 | /* |
249 | * Disable debounce before cutting it's clock. If debounce is | |
250 | * enabled but the clock is not, GPIO module seems to be unable | |
251 | * to detect events and generate interrupts at least on OMAP3. | |
252 | */ | |
661553b9 | 253 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 254 | |
5d9452e7 | 255 | clk_disable(bank->dbck); |
72f83af9 TKD |
256 | bank->dbck_enabled = false; |
257 | } | |
258 | } | |
259 | ||
168ef3d9 | 260 | /** |
a0e827c6 | 261 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 262 | * @bank: the gpio bank we're acting upon |
4a58d229 | 263 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
264 | * @debounce: debounce time to use |
265 | * | |
e85ec6c3 GS |
266 | * OMAP's debounce time is in 31us steps |
267 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
268 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
269 | * |
270 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 271 | */ |
83977443 DR |
272 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
273 | unsigned debounce) | |
168ef3d9 | 274 | { |
9942da0e | 275 | void __iomem *reg; |
168ef3d9 FB |
276 | u32 val; |
277 | u32 l; | |
e85ec6c3 | 278 | bool enable = !!debounce; |
168ef3d9 | 279 | |
77640aab | 280 | if (!bank->dbck_flag) |
83977443 | 281 | return -ENOTSUPP; |
77640aab | 282 | |
e85ec6c3 GS |
283 | if (enable) { |
284 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
285 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
286 | return -EINVAL; | |
e85ec6c3 | 287 | } |
168ef3d9 | 288 | |
4a58d229 | 289 | l = BIT(offset); |
168ef3d9 | 290 | |
5d9452e7 | 291 | clk_enable(bank->dbck); |
9942da0e | 292 | reg = bank->base + bank->regs->debounce; |
661553b9 | 293 | writel_relaxed(debounce, reg); |
168ef3d9 | 294 | |
9942da0e | 295 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 296 | val = readl_relaxed(reg); |
168ef3d9 | 297 | |
e85ec6c3 | 298 | if (enable) |
168ef3d9 | 299 | val |= l; |
6fd9c421 | 300 | else |
168ef3d9 | 301 | val &= ~l; |
f7ec0b0b | 302 | bank->dbck_enable_mask = val; |
168ef3d9 | 303 | |
661553b9 | 304 | writel_relaxed(val, reg); |
5d9452e7 | 305 | clk_disable(bank->dbck); |
6fd9c421 TKD |
306 | /* |
307 | * Enable debounce clock per module. | |
308 | * This call is mandatory because in omap_gpio_request() when | |
309 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
310 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
311 | * used within _gpio_dbck_enable() is still not initialized at | |
312 | * that point. Therefore we have to enable dbck here. | |
313 | */ | |
a0e827c6 | 314 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
315 | if (bank->dbck_enable_mask) { |
316 | bank->context.debounce = debounce; | |
317 | bank->context.debounce_en = val; | |
318 | } | |
83977443 DR |
319 | |
320 | return 0; | |
168ef3d9 FB |
321 | } |
322 | ||
c9c55d92 | 323 | /** |
a0e827c6 | 324 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 325 | * @bank: the gpio bank we're acting upon |
4a58d229 | 326 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
327 | * |
328 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
329 | * this is the only gpio in this bank using debounce, then clear the debounce | |
330 | * time too. The debounce clock will also be disabled when calling this function | |
331 | * if this is the only gpio in the bank using debounce. | |
332 | */ | |
4a58d229 | 333 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 334 | { |
4a58d229 | 335 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
336 | |
337 | if (!bank->dbck_flag) | |
338 | return; | |
339 | ||
340 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
341 | return; | |
342 | ||
343 | bank->dbck_enable_mask &= ~gpio_bit; | |
344 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 345 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
346 | bank->base + bank->regs->debounce_en); |
347 | ||
348 | if (!bank->dbck_enable_mask) { | |
349 | bank->context.debounce = 0; | |
661553b9 | 350 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 351 | bank->regs->debounce); |
5d9452e7 | 352 | clk_disable(bank->dbck); |
c9c55d92 JH |
353 | bank->dbck_enabled = false; |
354 | } | |
355 | } | |
356 | ||
a0e827c6 | 357 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 358 | unsigned trigger) |
5e1c5ff4 | 359 | { |
3ac4fa99 | 360 | void __iomem *base = bank->base; |
b1e9fec2 | 361 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 362 | |
a0e827c6 JMC |
363 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
364 | trigger & IRQ_TYPE_LEVEL_LOW); | |
365 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
366 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
367 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
368 | trigger & IRQ_TYPE_EDGE_RISING); | |
369 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
370 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 371 | |
41d87cbd | 372 | bank->context.leveldetect0 = |
661553b9 | 373 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 374 | bank->context.leveldetect1 = |
661553b9 | 375 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 376 | bank->context.risingdetect = |
661553b9 | 377 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 378 | bank->context.fallingdetect = |
661553b9 | 379 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
380 | |
381 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
ec0daae6 TL |
382 | /* Defer wkup_en register update until we idle? */ |
383 | if (bank->quirks & OMAP_GPIO_QUIRK_DEFERRED_WKUP_EN) { | |
384 | if (trigger) | |
385 | bank->context.wake_en |= gpio_bit; | |
386 | else | |
387 | bank->context.wake_en &= ~gpio_bit; | |
388 | } else { | |
389 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, | |
390 | trigger != 0); | |
391 | bank->context.wake_en = | |
392 | readl_relaxed(bank->base + bank->regs->wkup_en); | |
393 | } | |
41d87cbd | 394 | } |
5e571f38 | 395 | |
55b220ca | 396 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
397 | if (!bank->regs->irqctrl) { |
398 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
399 | if (bank->non_wakeup_gpios) { | |
400 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
401 | goto exit; | |
402 | } | |
403 | ||
699117a6 CW |
404 | /* |
405 | * Log the edge gpio and manually trigger the IRQ | |
406 | * after resume if the input level changes | |
407 | * to avoid irq lost during PER RET/OFF mode | |
408 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
409 | */ | |
410 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
411 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
412 | else | |
413 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
414 | } | |
5eb3bb9c | 415 | |
5e571f38 | 416 | exit: |
9ea14d8c | 417 | bank->level_mask = |
661553b9 VK |
418 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
419 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
420 | } |
421 | ||
9198bcd3 | 422 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
423 | /* |
424 | * This only applies to chips that can't do both rising and falling edge | |
425 | * detection at once. For all other chips, this function is a noop. | |
426 | */ | |
a0e827c6 | 427 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
428 | { |
429 | void __iomem *reg = bank->base; | |
430 | u32 l = 0; | |
431 | ||
5e571f38 | 432 | if (!bank->regs->irqctrl) |
4318f36b | 433 | return; |
5e571f38 TKD |
434 | |
435 | reg += bank->regs->irqctrl; | |
4318f36b | 436 | |
661553b9 | 437 | l = readl_relaxed(reg); |
4318f36b | 438 | if ((l >> gpio) & 1) |
b1e9fec2 | 439 | l &= ~(BIT(gpio)); |
4318f36b | 440 | else |
b1e9fec2 | 441 | l |= BIT(gpio); |
4318f36b | 442 | |
661553b9 | 443 | writel_relaxed(l, reg); |
4318f36b | 444 | } |
5e571f38 | 445 | #else |
a0e827c6 | 446 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 447 | #endif |
4318f36b | 448 | |
a0e827c6 JMC |
449 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
450 | unsigned trigger) | |
92105bb7 TL |
451 | { |
452 | void __iomem *reg = bank->base; | |
5e571f38 | 453 | void __iomem *base = bank->base; |
92105bb7 | 454 | u32 l = 0; |
5e1c5ff4 | 455 | |
5e571f38 | 456 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 457 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
458 | } else if (bank->regs->irqctrl) { |
459 | reg += bank->regs->irqctrl; | |
460 | ||
661553b9 | 461 | l = readl_relaxed(reg); |
29501577 | 462 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 463 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 464 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 465 | l |= BIT(gpio); |
6cab4860 | 466 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 467 | l &= ~(BIT(gpio)); |
92105bb7 | 468 | else |
5e571f38 TKD |
469 | return -EINVAL; |
470 | ||
661553b9 | 471 | writel_relaxed(l, reg); |
5e571f38 | 472 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 473 | if (gpio & 0x08) |
5e571f38 | 474 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 475 | else |
5e571f38 TKD |
476 | reg += bank->regs->edgectrl1; |
477 | ||
5e1c5ff4 | 478 | gpio &= 0x07; |
661553b9 | 479 | l = readl_relaxed(reg); |
5e1c5ff4 | 480 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 481 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 482 | l |= 2 << (gpio << 1); |
6cab4860 | 483 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 484 | l |= BIT(gpio << 1); |
5e571f38 TKD |
485 | |
486 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 487 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 488 | bank->context.wake_en = |
661553b9 VK |
489 | readl_relaxed(bank->base + bank->regs->wkup_en); |
490 | writel_relaxed(l, reg); | |
5e1c5ff4 | 491 | } |
92105bb7 | 492 | return 0; |
5e1c5ff4 TL |
493 | } |
494 | ||
a0e827c6 | 495 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
496 | { |
497 | if (bank->regs->pinctrl) { | |
498 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
499 | ||
500 | /* Claim the pin for MPU */ | |
b1e9fec2 | 501 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
502 | } |
503 | ||
504 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
505 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
506 | u32 ctrl; | |
507 | ||
661553b9 | 508 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
509 | /* Module is enabled, clocks are not gated */ |
510 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 511 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
512 | bank->context.ctrl = ctrl; |
513 | } | |
514 | } | |
515 | ||
a0e827c6 | 516 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
517 | { |
518 | void __iomem *base = bank->base; | |
519 | ||
520 | if (bank->regs->wkup_en && | |
521 | !LINE_USED(bank->mod_usage, offset) && | |
522 | !LINE_USED(bank->irq_usage, offset)) { | |
523 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 524 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 525 | bank->context.wake_en = |
661553b9 | 526 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
527 | } |
528 | ||
529 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
530 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
531 | u32 ctrl; | |
532 | ||
661553b9 | 533 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
534 | /* Module is disabled, clocks are gated */ |
535 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 536 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
537 | bank->context.ctrl = ctrl; |
538 | } | |
539 | } | |
540 | ||
b2b20045 | 541 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
542 | { |
543 | void __iomem *reg = bank->base + bank->regs->direction; | |
544 | ||
b2b20045 | 545 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
546 | } |
547 | ||
37e14ecf | 548 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
549 | { |
550 | if (!LINE_USED(bank->mod_usage, offset)) { | |
551 | omap_enable_gpio_module(bank, offset); | |
552 | omap_set_gpio_direction(bank, offset, 1); | |
553 | } | |
37e14ecf | 554 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
555 | } |
556 | ||
a0e827c6 | 557 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 558 | { |
a0e827c6 | 559 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 560 | int retval; |
a6472533 | 561 | unsigned long flags; |
ea5fbe8d | 562 | unsigned offset = d->hwirq; |
92105bb7 | 563 | |
e5c56ed3 | 564 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 565 | return -EINVAL; |
e5c56ed3 | 566 | |
9ea14d8c TKD |
567 | if (!bank->regs->leveldetect0 && |
568 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
569 | return -EINVAL; |
570 | ||
4dbada2b | 571 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 572 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 573 | if (retval) { |
627c89b4 | 574 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 575 | goto error; |
977bd8a9 | 576 | } |
37e14ecf | 577 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 578 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 579 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
580 | retval = -EINVAL; |
581 | goto error; | |
fac7fa16 | 582 | } |
4dbada2b | 583 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
584 | |
585 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 586 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 587 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
588 | /* |
589 | * Edge IRQs are already cleared/acked in irq_handler and | |
590 | * not need to be masked, as result handle_edge_irq() | |
591 | * logic is excessed here and may cause lose of interrupts. | |
592 | * So just use handle_simple_irq. | |
593 | */ | |
594 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 595 | |
1562e461 GS |
596 | return 0; |
597 | ||
598 | error: | |
92105bb7 | 599 | return retval; |
5e1c5ff4 TL |
600 | } |
601 | ||
a0e827c6 | 602 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 603 | { |
92105bb7 | 604 | void __iomem *reg = bank->base; |
5e1c5ff4 | 605 | |
eef4bec7 | 606 | reg += bank->regs->irqstatus; |
661553b9 | 607 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
608 | |
609 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
610 | if (bank->regs->irqstatus2) { |
611 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 612 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 613 | } |
bedfd154 RQ |
614 | |
615 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 616 | readl_relaxed(reg); |
5e1c5ff4 TL |
617 | } |
618 | ||
9943f261 GS |
619 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
620 | unsigned offset) | |
5e1c5ff4 | 621 | { |
9943f261 | 622 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
623 | } |
624 | ||
a0e827c6 | 625 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
626 | { |
627 | void __iomem *reg = bank->base; | |
99c47707 | 628 | u32 l; |
b1e9fec2 | 629 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 630 | |
28f3b5a0 | 631 | reg += bank->regs->irqenable; |
661553b9 | 632 | l = readl_relaxed(reg); |
28f3b5a0 | 633 | if (bank->regs->irqenable_inv) |
99c47707 ID |
634 | l = ~l; |
635 | l &= mask; | |
636 | return l; | |
ea6dedd7 ID |
637 | } |
638 | ||
a0e827c6 | 639 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 640 | { |
92105bb7 | 641 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
642 | u32 l; |
643 | ||
28f3b5a0 KH |
644 | if (bank->regs->set_irqenable) { |
645 | reg += bank->regs->set_irqenable; | |
646 | l = gpio_mask; | |
2a900eb7 | 647 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
648 | } else { |
649 | reg += bank->regs->irqenable; | |
661553b9 | 650 | l = readl_relaxed(reg); |
28f3b5a0 KH |
651 | if (bank->regs->irqenable_inv) |
652 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
653 | else |
654 | l |= gpio_mask; | |
2a900eb7 | 655 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
656 | } |
657 | ||
661553b9 | 658 | writel_relaxed(l, reg); |
28f3b5a0 KH |
659 | } |
660 | ||
a0e827c6 | 661 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
662 | { |
663 | void __iomem *reg = bank->base; | |
664 | u32 l; | |
665 | ||
666 | if (bank->regs->clr_irqenable) { | |
667 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 668 | l = gpio_mask; |
2a900eb7 | 669 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
670 | } else { |
671 | reg += bank->regs->irqenable; | |
661553b9 | 672 | l = readl_relaxed(reg); |
28f3b5a0 | 673 | if (bank->regs->irqenable_inv) |
56739a69 | 674 | l |= gpio_mask; |
92105bb7 | 675 | else |
28f3b5a0 | 676 | l &= ~gpio_mask; |
2a900eb7 | 677 | bank->context.irqenable1 = l; |
5e1c5ff4 | 678 | } |
28f3b5a0 | 679 | |
661553b9 | 680 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
681 | } |
682 | ||
9943f261 GS |
683 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
684 | unsigned offset, int enable) | |
5e1c5ff4 | 685 | { |
8276536c | 686 | if (enable) |
9943f261 | 687 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 688 | else |
9943f261 | 689 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
690 | } |
691 | ||
92105bb7 | 692 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 693 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 694 | { |
a0e827c6 | 695 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 696 | |
0c0451e7 | 697 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
698 | } |
699 | ||
3ff164e1 | 700 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 701 | { |
d99f7aec | 702 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 703 | unsigned long flags; |
52e31344 | 704 | |
46748073 | 705 | pm_runtime_get_sync(chip->parent); |
92105bb7 | 706 | |
4dbada2b | 707 | raw_spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 708 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 709 | bank->mod_usage |= BIT(offset); |
4dbada2b | 710 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
711 | |
712 | return 0; | |
713 | } | |
714 | ||
3ff164e1 | 715 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 716 | { |
d99f7aec | 717 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 718 | unsigned long flags; |
5e1c5ff4 | 719 | |
4dbada2b | 720 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 721 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
722 | if (!LINE_USED(bank->irq_usage, offset)) { |
723 | omap_set_gpio_direction(bank, offset, 1); | |
724 | omap_clear_gpio_debounce(bank, offset); | |
725 | } | |
a0e827c6 | 726 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 727 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 728 | |
46748073 | 729 | pm_runtime_put(chip->parent); |
5e1c5ff4 TL |
730 | } |
731 | ||
732 | /* | |
733 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
734 | * avoid missing GPIO interrupts for other lines in the bank. | |
735 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
736 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
737 | * If we wait to unmask individual GPIO lines in the bank after the | |
738 | * line's interrupt handler has been run, we may miss some nested | |
739 | * interrupts. | |
740 | */ | |
450fa54c | 741 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 742 | { |
92105bb7 | 743 | void __iomem *isr_reg = NULL; |
80ac93c2 | 744 | u32 enabled, isr, level_mask; |
3513cdec | 745 | unsigned int bit; |
450fa54c GS |
746 | struct gpio_bank *bank = gpiobank; |
747 | unsigned long wa_lock_flags; | |
235f1eb1 | 748 | unsigned long lock_flags; |
5e1c5ff4 | 749 | |
eef4bec7 | 750 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
751 | if (WARN_ON(!isr_reg)) |
752 | goto exit; | |
753 | ||
5284521a TL |
754 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
755 | "gpio irq%i while runtime suspended?\n", irq)) | |
756 | return IRQ_NONE; | |
450fa54c | 757 | |
e83507b7 | 758 | while (1) { |
235f1eb1 GS |
759 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
760 | ||
a0e827c6 | 761 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 762 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 763 | |
9ea14d8c | 764 | if (bank->level_mask) |
b144ff6f | 765 | level_mask = bank->level_mask & enabled; |
80ac93c2 GS |
766 | else |
767 | level_mask = 0; | |
6e60e79a TL |
768 | |
769 | /* clear edge sensitive interrupts before handler(s) are | |
770 | called so that we don't miss any interrupt occurred while | |
771 | executing them */ | |
80ac93c2 GS |
772 | if (isr & ~level_mask) |
773 | omap_clear_gpio_irqbank(bank, isr & ~level_mask); | |
6e60e79a | 774 | |
235f1eb1 GS |
775 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
776 | ||
92105bb7 TL |
777 | if (!isr) |
778 | break; | |
779 | ||
3513cdec JH |
780 | while (isr) { |
781 | bit = __ffs(isr); | |
b1e9fec2 | 782 | isr &= ~(BIT(bit)); |
25db711d | 783 | |
235f1eb1 | 784 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
785 | /* |
786 | * Some chips can't respond to both rising and falling | |
787 | * at the same time. If this irq was requested with | |
788 | * both flags, we need to flip the ICR data for the IRQ | |
789 | * to respond to the IRQ for the opposite direction. | |
790 | * This will be indicated in the bank toggle_mask. | |
791 | */ | |
b1e9fec2 | 792 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 793 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 794 | |
235f1eb1 GS |
795 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
796 | ||
450fa54c GS |
797 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
798 | ||
f0fbe7bc | 799 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 800 | bit)); |
450fa54c GS |
801 | |
802 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
803 | wa_lock_flags); | |
92105bb7 | 804 | } |
1a8bfa1e | 805 | } |
b1cc4c55 | 806 | exit: |
450fa54c | 807 | return IRQ_HANDLED; |
5e1c5ff4 TL |
808 | } |
809 | ||
3d009c8c TL |
810 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
811 | { | |
812 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 813 | unsigned long flags; |
37e14ecf | 814 | unsigned offset = d->hwirq; |
3d009c8c | 815 | |
4dbada2b | 816 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
817 | |
818 | if (!LINE_USED(bank->mod_usage, offset)) | |
819 | omap_set_gpio_direction(bank, offset, 1); | |
820 | else if (!omap_gpio_is_input(bank, offset)) | |
821 | goto err; | |
822 | omap_enable_gpio_module(bank, offset); | |
823 | bank->irq_usage |= BIT(offset); | |
824 | ||
4dbada2b | 825 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
826 | omap_gpio_unmask_irq(d); |
827 | ||
828 | return 0; | |
121dcb76 | 829 | err: |
4dbada2b | 830 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 831 | return -EINVAL; |
3d009c8c TL |
832 | } |
833 | ||
a0e827c6 | 834 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 835 | { |
a0e827c6 | 836 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 837 | unsigned long flags; |
9943f261 | 838 | unsigned offset = d->hwirq; |
4196dd6b | 839 | |
4dbada2b | 840 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 841 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
842 | omap_set_gpio_irqenable(bank, offset, 0); |
843 | omap_clear_gpio_irqstatus(bank, offset); | |
844 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
845 | if (!LINE_USED(bank->mod_usage, offset)) | |
846 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 847 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 848 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
849 | } |
850 | ||
851 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
852 | { | |
853 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
854 | ||
46748073 | 855 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
856 | } |
857 | ||
858 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
859 | { | |
860 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 861 | |
46748073 | 862 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
863 | } |
864 | ||
a0e827c6 | 865 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 866 | { |
a0e827c6 | 867 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 868 | unsigned offset = d->hwirq; |
5e1c5ff4 | 869 | |
9943f261 | 870 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
871 | } |
872 | ||
a0e827c6 | 873 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 874 | { |
a0e827c6 | 875 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 876 | unsigned offset = d->hwirq; |
85ec7b97 | 877 | unsigned long flags; |
5e1c5ff4 | 878 | |
4dbada2b | 879 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
880 | omap_set_gpio_irqenable(bank, offset, 0); |
881 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
4dbada2b | 882 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
883 | } |
884 | ||
a0e827c6 | 885 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 886 | { |
a0e827c6 | 887 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 888 | unsigned offset = d->hwirq; |
8c04a176 | 889 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 890 | unsigned long flags; |
55b6019a | 891 | |
4dbada2b | 892 | raw_spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 893 | if (trigger) |
9943f261 | 894 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f KH |
895 | |
896 | /* For level-triggered GPIOs, the clearing must be done after | |
897 | * the HW source is cleared, thus after the handler has run */ | |
9943f261 GS |
898 | if (bank->level_mask & BIT(offset)) { |
899 | omap_set_gpio_irqenable(bank, offset, 0); | |
900 | omap_clear_gpio_irqstatus(bank, offset); | |
b144ff6f | 901 | } |
5e1c5ff4 | 902 | |
9943f261 | 903 | omap_set_gpio_irqenable(bank, offset, 1); |
4dbada2b | 904 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
905 | } |
906 | ||
ec0daae6 TL |
907 | /* |
908 | * Only edges can generate a wakeup event to the PRCM. | |
909 | * | |
910 | * Therefore, ensure any wake-up capable GPIOs have | |
911 | * edge-detection enabled before going idle to ensure a wakeup | |
912 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
913 | * NDA TRM 25.5.3.1) | |
914 | * | |
915 | * The normal values will be restored upon ->runtime_resume() | |
916 | * by writing back the values saved in bank->context. | |
917 | */ | |
918 | static void __maybe_unused | |
919 | omap2_gpio_enable_level_quirk(struct gpio_bank *bank) | |
920 | { | |
921 | u32 wake_low, wake_hi; | |
922 | ||
923 | /* Enable additional edge detection for level gpios for idle */ | |
924 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
925 | if (wake_low) | |
926 | writel_relaxed(wake_low | bank->context.fallingdetect, | |
927 | bank->base + bank->regs->fallingdetect); | |
928 | ||
929 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
930 | if (wake_hi) | |
931 | writel_relaxed(wake_hi | bank->context.risingdetect, | |
932 | bank->base + bank->regs->risingdetect); | |
933 | } | |
934 | ||
935 | static void __maybe_unused | |
936 | omap2_gpio_disable_level_quirk(struct gpio_bank *bank) | |
937 | { | |
938 | /* Disable edge detection for level gpios after idle */ | |
939 | writel_relaxed(bank->context.fallingdetect, | |
940 | bank->base + bank->regs->fallingdetect); | |
941 | writel_relaxed(bank->context.risingdetect, | |
942 | bank->base + bank->regs->risingdetect); | |
943 | } | |
944 | ||
945 | /* | |
946 | * On omap4 and later SoC variants a level interrupt with wkup_en | |
947 | * enabled blocks the GPIO functional clock from idling until the GPIO | |
948 | * instance has been reset. To avoid that, we must set wkup_en only for | |
949 | * idle for level interrupts, and clear level registers for the duration | |
950 | * of idle. The level interrupts will be still there on wakeup by their | |
951 | * nature. | |
952 | */ | |
953 | static void __maybe_unused | |
954 | omap4_gpio_enable_level_quirk(struct gpio_bank *bank) | |
955 | { | |
956 | /* Update wake register for idle, edge bits might be already set */ | |
957 | writel_relaxed(bank->context.wake_en, | |
958 | bank->base + bank->regs->wkup_en); | |
959 | ||
960 | /* Clear level registers for idle */ | |
961 | writel_relaxed(0, bank->base + bank->regs->leveldetect0); | |
962 | writel_relaxed(0, bank->base + bank->regs->leveldetect1); | |
963 | } | |
964 | ||
965 | static void __maybe_unused | |
966 | omap4_gpio_disable_level_quirk(struct gpio_bank *bank) | |
967 | { | |
968 | /* Restore level registers after idle */ | |
969 | writel_relaxed(bank->context.leveldetect0, | |
970 | bank->base + bank->regs->leveldetect0); | |
971 | writel_relaxed(bank->context.leveldetect1, | |
972 | bank->base + bank->regs->leveldetect1); | |
973 | ||
974 | /* Clear saved wkup_en for level, it will be set for next idle again */ | |
975 | bank->context.wake_en &= ~(bank->context.leveldetect0 | | |
976 | bank->context.leveldetect1); | |
977 | ||
978 | /* Update wake with only edge configuration */ | |
979 | writel_relaxed(bank->context.wake_en, | |
980 | bank->base + bank->regs->wkup_en); | |
981 | } | |
982 | ||
e5c56ed3 DB |
983 | /*---------------------------------------------------------------------*/ |
984 | ||
79ee031f | 985 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 986 | { |
79ee031f | 987 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 988 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
989 | void __iomem *mask_reg = bank->base + |
990 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 991 | unsigned long flags; |
11a78b79 | 992 | |
4dbada2b | 993 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 994 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 995 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
996 | |
997 | return 0; | |
998 | } | |
999 | ||
79ee031f | 1000 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1001 | { |
79ee031f | 1002 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1003 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1004 | void __iomem *mask_reg = bank->base + |
1005 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1006 | unsigned long flags; |
11a78b79 | 1007 | |
4dbada2b | 1008 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 1009 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 1010 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1011 | |
1012 | return 0; | |
1013 | } | |
1014 | ||
47145210 | 1015 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1016 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1017 | .resume_noirq = omap_mpuio_resume_noirq, | |
1018 | }; | |
1019 | ||
3c437ffd | 1020 | /* use platform_driver for this. */ |
11a78b79 | 1021 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
1022 | .driver = { |
1023 | .name = "mpuio", | |
79ee031f | 1024 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1025 | }, |
1026 | }; | |
1027 | ||
1028 | static struct platform_device omap_mpuio_device = { | |
1029 | .name = "mpuio", | |
1030 | .id = -1, | |
1031 | .dev = { | |
1032 | .driver = &omap_mpuio_driver.driver, | |
1033 | } | |
1034 | /* could list the /proc/iomem resources */ | |
1035 | }; | |
1036 | ||
a0e827c6 | 1037 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 1038 | { |
77640aab | 1039 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 1040 | |
11a78b79 DB |
1041 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1042 | (void) platform_device_register(&omap_mpuio_device); | |
1043 | } | |
1044 | ||
e5c56ed3 | 1045 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 1046 | |
a0e827c6 | 1047 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
1048 | { |
1049 | struct gpio_bank *bank; | |
1050 | unsigned long flags; | |
1051 | void __iomem *reg; | |
1052 | int dir; | |
1053 | ||
d99f7aec | 1054 | bank = gpiochip_get_data(chip); |
9370084e | 1055 | reg = bank->base + bank->regs->direction; |
4dbada2b | 1056 | raw_spin_lock_irqsave(&bank->lock, flags); |
9370084e | 1057 | dir = !!(readl_relaxed(reg) & BIT(offset)); |
4dbada2b | 1058 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
9370084e YY |
1059 | return dir; |
1060 | } | |
1061 | ||
a0e827c6 | 1062 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
1063 | { |
1064 | struct gpio_bank *bank; | |
1065 | unsigned long flags; | |
1066 | ||
d99f7aec | 1067 | bank = gpiochip_get_data(chip); |
4dbada2b | 1068 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 1069 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 1070 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1071 | return 0; |
1072 | } | |
1073 | ||
a0e827c6 | 1074 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 1075 | { |
b37c45b8 | 1076 | struct gpio_bank *bank; |
b37c45b8 | 1077 | |
d99f7aec | 1078 | bank = gpiochip_get_data(chip); |
b37c45b8 | 1079 | |
b2b20045 | 1080 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 1081 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 1082 | else |
a0e827c6 | 1083 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
1084 | } |
1085 | ||
a0e827c6 | 1086 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1087 | { |
1088 | struct gpio_bank *bank; | |
1089 | unsigned long flags; | |
1090 | ||
d99f7aec | 1091 | bank = gpiochip_get_data(chip); |
4dbada2b | 1092 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1093 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 1094 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 1095 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 1096 | return 0; |
52e31344 DB |
1097 | } |
1098 | ||
442af140 JK |
1099 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
1100 | unsigned long *bits) | |
1101 | { | |
1102 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1103 | void __iomem *reg = bank->base + bank->regs->direction; | |
1104 | unsigned long in = readl_relaxed(reg), l; | |
1105 | ||
1106 | *bits = 0; | |
1107 | ||
1108 | l = in & *mask; | |
1109 | if (l) | |
1110 | *bits |= omap_get_gpio_datain_multiple(bank, &l); | |
1111 | ||
1112 | l = ~in & *mask; | |
1113 | if (l) | |
1114 | *bits |= omap_get_gpio_dataout_multiple(bank, &l); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
a0e827c6 JMC |
1119 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1120 | unsigned debounce) | |
168ef3d9 FB |
1121 | { |
1122 | struct gpio_bank *bank; | |
1123 | unsigned long flags; | |
83977443 | 1124 | int ret; |
168ef3d9 | 1125 | |
d99f7aec | 1126 | bank = gpiochip_get_data(chip); |
77640aab | 1127 | |
4dbada2b | 1128 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 1129 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 1130 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 1131 | |
83977443 DR |
1132 | if (ret) |
1133 | dev_info(chip->parent, | |
1134 | "Could not set line %u debounce to %u microseconds (%d)", | |
1135 | offset, debounce, ret); | |
1136 | ||
1137 | return ret; | |
168ef3d9 FB |
1138 | } |
1139 | ||
2956b5d9 MW |
1140 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
1141 | unsigned long config) | |
1142 | { | |
1143 | u32 debounce; | |
1144 | ||
1145 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
1146 | return -ENOTSUPP; | |
1147 | ||
1148 | debounce = pinconf_to_config_argument(config); | |
1149 | return omap_gpio_debounce(chip, offset, debounce); | |
1150 | } | |
1151 | ||
a0e827c6 | 1152 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1153 | { |
1154 | struct gpio_bank *bank; | |
1155 | unsigned long flags; | |
1156 | ||
d99f7aec | 1157 | bank = gpiochip_get_data(chip); |
4dbada2b | 1158 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1159 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1160 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1161 | } |
1162 | ||
442af140 JK |
1163 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
1164 | unsigned long *bits) | |
1165 | { | |
1166 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1167 | unsigned long flags; | |
1168 | ||
1169 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1170 | bank->set_dataout_multiple(bank, mask, bits); | |
1171 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1172 | } | |
1173 | ||
52e31344 DB |
1174 | /*---------------------------------------------------------------------*/ |
1175 | ||
e4b2ae7a | 1176 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1177 | { |
e5ff4440 | 1178 | static bool called; |
9f7065da TL |
1179 | u32 rev; |
1180 | ||
e5ff4440 | 1181 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1182 | return; |
1183 | ||
661553b9 | 1184 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1185 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1186 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1187 | |
1188 | called = true; | |
9f7065da TL |
1189 | } |
1190 | ||
03e128ca | 1191 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1192 | { |
ab985f0f TKD |
1193 | void __iomem *base = bank->base; |
1194 | u32 l = 0xffffffff; | |
2fae7fbe | 1195 | |
ab985f0f TKD |
1196 | if (bank->width == 16) |
1197 | l = 0xffff; | |
1198 | ||
d0d665a8 | 1199 | if (bank->is_mpuio) { |
661553b9 | 1200 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1201 | return; |
2fae7fbe | 1202 | } |
ab985f0f | 1203 | |
a0e827c6 JMC |
1204 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1205 | bank->regs->irqenable_inv); | |
1206 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1207 | !bank->regs->irqenable_inv); | |
ab985f0f | 1208 | if (bank->regs->debounce_en) |
661553b9 | 1209 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1210 | |
2dc983c5 | 1211 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1212 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1213 | /* Initialize interface clk ungated, module enabled */ |
1214 | if (bank->regs->ctrl) | |
661553b9 | 1215 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1216 | } |
1217 | ||
46824e22 | 1218 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1219 | { |
81930328 | 1220 | struct gpio_irq_chip *irq; |
2fae7fbe | 1221 | static int gpio; |
088413bc | 1222 | const char *label; |
fb655f57 | 1223 | int irq_base = 0; |
6ef7f385 | 1224 | int ret; |
2fae7fbe | 1225 | |
2fae7fbe VC |
1226 | /* |
1227 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1228 | * over to the generic ones | |
1229 | */ | |
1230 | bank->chip.request = omap_gpio_request; | |
1231 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1232 | bank->chip.get_direction = omap_gpio_get_direction; |
1233 | bank->chip.direction_input = omap_gpio_input; | |
1234 | bank->chip.get = omap_gpio_get; | |
442af140 | 1235 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1236 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1237 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1238 | bank->chip.set = omap_gpio_set; |
442af140 | 1239 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1240 | if (bank->is_mpuio) { |
2fae7fbe | 1241 | bank->chip.label = "mpuio"; |
6ed87c5b | 1242 | if (bank->regs->wkup_en) |
58383c78 | 1243 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1244 | bank->chip.base = OMAP_MPUIO(0); |
1245 | } else { | |
088413bc LW |
1246 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1247 | gpio, gpio + bank->width - 1); | |
1248 | if (!label) | |
1249 | return -ENOMEM; | |
1250 | bank->chip.label = label; | |
2fae7fbe | 1251 | bank->chip.base = gpio; |
2fae7fbe | 1252 | } |
d5f46247 | 1253 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1254 | |
fb655f57 JMC |
1255 | #ifdef CONFIG_ARCH_OMAP1 |
1256 | /* | |
1257 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1258 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1259 | */ | |
2ed36f30 BG |
1260 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1261 | -1, 0, bank->width, 0); | |
fb655f57 | 1262 | if (irq_base < 0) { |
7b1e5dc8 | 1263 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1264 | return -ENODEV; |
1265 | } | |
1266 | #endif | |
1267 | ||
d2d05c65 TL |
1268 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1269 | if (bank->is_mpuio) { | |
1270 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
d2d05c65 TL |
1271 | if (!bank->regs->wkup_en) |
1272 | irqc->irq_set_wake = NULL; | |
1273 | } | |
1274 | ||
81930328 GS |
1275 | irq = &bank->chip.irq; |
1276 | irq->chip = irqc; | |
1277 | irq->handler = handle_bad_irq; | |
1278 | irq->default_type = IRQ_TYPE_NONE; | |
1279 | irq->num_parents = 1; | |
1280 | irq->parents = &bank->irq; | |
1281 | irq->first = irq_base; | |
fb655f57 | 1282 | |
81930328 | 1283 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1284 | if (ret) { |
7b1e5dc8 | 1285 | dev_err(bank->chip.parent, |
81930328 GS |
1286 | "Could not register gpio chip %d\n", ret); |
1287 | return ret; | |
fb655f57 JMC |
1288 | } |
1289 | ||
7b1e5dc8 GS |
1290 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1291 | omap_gpio_irq_handler, | |
1292 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1293 | if (ret) |
1294 | gpiochip_remove(&bank->chip); | |
1295 | ||
81930328 GS |
1296 | if (!bank->is_mpuio) |
1297 | gpio += bank->width; | |
1298 | ||
450fa54c | 1299 | return ret; |
2fae7fbe VC |
1300 | } |
1301 | ||
b764a586 TL |
1302 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context); |
1303 | static void omap_gpio_unidle(struct gpio_bank *bank); | |
1304 | ||
1305 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, | |
1306 | unsigned long cmd, void *v) | |
1307 | { | |
1308 | struct gpio_bank *bank; | |
b764a586 TL |
1309 | unsigned long flags; |
1310 | ||
1311 | bank = container_of(nb, struct gpio_bank, nb); | |
b764a586 TL |
1312 | |
1313 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1314 | switch (cmd) { | |
1315 | case CPU_CLUSTER_PM_ENTER: | |
1316 | if (bank->is_suspended) | |
1317 | break; | |
1318 | omap_gpio_idle(bank, true); | |
1319 | break; | |
1320 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1321 | case CPU_CLUSTER_PM_EXIT: | |
1322 | if (bank->is_suspended) | |
1323 | break; | |
1324 | omap_gpio_unidle(bank); | |
1325 | break; | |
1326 | } | |
1327 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1328 | ||
1329 | return NOTIFY_OK; | |
1330 | } | |
1331 | ||
384ebe1c BC |
1332 | static const struct of_device_id omap_gpio_match[]; |
1333 | ||
3836309d | 1334 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1335 | { |
862ff640 | 1336 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1337 | struct device_node *node = dev->of_node; |
1338 | const struct of_device_id *match; | |
f6817a2c | 1339 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1340 | struct resource *res; |
5e1c5ff4 | 1341 | struct gpio_bank *bank; |
46824e22 | 1342 | struct irq_chip *irqc; |
6ef7f385 | 1343 | int ret; |
5e1c5ff4 | 1344 | |
384ebe1c BC |
1345 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1346 | ||
e56aee18 | 1347 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1348 | if (!pdata) |
96751fcb | 1349 | return -EINVAL; |
5492fb1a | 1350 | |
f97364c9 | 1351 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); |
9117d40b | 1352 | if (!bank) |
96751fcb | 1353 | return -ENOMEM; |
92105bb7 | 1354 | |
46824e22 NM |
1355 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1356 | if (!irqc) | |
1357 | return -ENOMEM; | |
1358 | ||
3d009c8c | 1359 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1360 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1361 | irqc->irq_ack = omap_gpio_ack_irq, | |
1362 | irqc->irq_mask = omap_gpio_mask_irq, | |
1363 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1364 | irqc->irq_set_type = omap_gpio_irq_type, | |
1365 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
aca82d1c GS |
1366 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, |
1367 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
46824e22 | 1368 | irqc->name = dev_name(&pdev->dev); |
0c0451e7 | 1369 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; |
46748073 | 1370 | irqc->parent_device = dev; |
46824e22 | 1371 | |
89d18e3a GS |
1372 | bank->irq = platform_get_irq(pdev, 0); |
1373 | if (bank->irq <= 0) { | |
1374 | if (!bank->irq) | |
1375 | bank->irq = -ENXIO; | |
1376 | if (bank->irq != -EPROBE_DEFER) | |
1377 | dev_err(dev, | |
1378 | "can't get irq resource ret=%d\n", bank->irq); | |
1379 | return bank->irq; | |
44169075 | 1380 | } |
5e1c5ff4 | 1381 | |
58383c78 | 1382 | bank->chip.parent = dev; |
c23837ce | 1383 | bank->chip.owner = THIS_MODULE; |
77640aab | 1384 | bank->dbck_flag = pdata->dbck_flag; |
ec0daae6 | 1385 | bank->quirks = pdata->quirks; |
5de62b86 | 1386 | bank->stride = pdata->bank_stride; |
d5f46247 | 1387 | bank->width = pdata->bank_width; |
d0d665a8 | 1388 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1389 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1390 | bank->regs = pdata->regs; |
384ebe1c BC |
1391 | #ifdef CONFIG_OF_GPIO |
1392 | bank->chip.of_node = of_node_get(node); | |
1393 | #endif | |
ec0daae6 | 1394 | |
a2797bea JH |
1395 | if (node) { |
1396 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1397 | bank->loses_context = true; | |
1398 | } else { | |
1399 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1400 | |
1401 | if (bank->loses_context) | |
1402 | bank->get_context_loss_count = | |
1403 | pdata->get_context_loss_count; | |
384ebe1c BC |
1404 | } |
1405 | ||
442af140 | 1406 | if (bank->regs->set_dataout && bank->regs->clr_dataout) { |
a0e827c6 | 1407 | bank->set_dataout = omap_set_gpio_dataout_reg; |
442af140 JK |
1408 | bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; |
1409 | } else { | |
a0e827c6 | 1410 | bank->set_dataout = omap_set_gpio_dataout_mask; |
442af140 JK |
1411 | bank->set_dataout_multiple = |
1412 | omap_set_gpio_dataout_mask_multiple; | |
1413 | } | |
9f7065da | 1414 | |
ec0daae6 TL |
1415 | if (bank->quirks & OMAP_GPIO_QUIRK_DEFERRED_WKUP_EN) { |
1416 | bank->funcs.idle_enable_level_quirk = | |
1417 | omap4_gpio_enable_level_quirk; | |
1418 | bank->funcs.idle_disable_level_quirk = | |
1419 | omap4_gpio_disable_level_quirk; | |
b764a586 | 1420 | } else if (bank->quirks & OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER) { |
ec0daae6 TL |
1421 | bank->funcs.idle_enable_level_quirk = |
1422 | omap2_gpio_enable_level_quirk; | |
1423 | bank->funcs.idle_disable_level_quirk = | |
1424 | omap2_gpio_disable_level_quirk; | |
1425 | } | |
1426 | ||
4dbada2b | 1427 | raw_spin_lock_init(&bank->lock); |
450fa54c | 1428 | raw_spin_lock_init(&bank->wa_lock); |
9f7065da | 1429 | |
77640aab VC |
1430 | /* Static mapping, never released */ |
1431 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1432 | bank->base = devm_ioremap_resource(dev, res); |
1433 | if (IS_ERR(bank->base)) { | |
717f70e3 | 1434 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1435 | } |
1436 | ||
5d9452e7 | 1437 | if (bank->dbck_flag) { |
7b1e5dc8 | 1438 | bank->dbck = devm_clk_get(dev, "dbclk"); |
5d9452e7 | 1439 | if (IS_ERR(bank->dbck)) { |
7b1e5dc8 | 1440 | dev_err(dev, |
5d9452e7 GS |
1441 | "Could not get gpio dbck. Disable debounce\n"); |
1442 | bank->dbck_flag = false; | |
1443 | } else { | |
1444 | clk_prepare(bank->dbck); | |
1445 | } | |
1446 | } | |
1447 | ||
065cd795 TKD |
1448 | platform_set_drvdata(pdev, bank); |
1449 | ||
7b1e5dc8 | 1450 | pm_runtime_enable(dev); |
7b1e5dc8 | 1451 | pm_runtime_get_sync(dev); |
77640aab | 1452 | |
d0d665a8 | 1453 | if (bank->is_mpuio) |
a0e827c6 | 1454 | omap_mpuio_init(bank); |
ab985f0f | 1455 | |
03e128ca | 1456 | omap_gpio_mod_init(bank); |
6ef7f385 | 1457 | |
46824e22 | 1458 | ret = omap_gpio_chip_init(bank, irqc); |
5e606abe | 1459 | if (ret) { |
7b1e5dc8 GS |
1460 | pm_runtime_put_sync(dev); |
1461 | pm_runtime_disable(dev); | |
e2c3c196 AY |
1462 | if (bank->dbck_flag) |
1463 | clk_unprepare(bank->dbck); | |
6ef7f385 | 1464 | return ret; |
5e606abe | 1465 | } |
6ef7f385 | 1466 | |
9a748053 | 1467 | omap_gpio_show_rev(bank); |
9f7065da | 1468 | |
b764a586 TL |
1469 | if (bank->funcs.idle_enable_level_quirk && |
1470 | bank->funcs.idle_disable_level_quirk) { | |
1471 | bank->nb.notifier_call = gpio_omap_cpu_notifier; | |
1472 | cpu_pm_register_notifier(&bank->nb); | |
1473 | } | |
1474 | ||
7b1e5dc8 | 1475 | pm_runtime_put(dev); |
55b93c32 | 1476 | |
879fe324 | 1477 | return 0; |
5e1c5ff4 TL |
1478 | } |
1479 | ||
cac089f9 TL |
1480 | static int omap_gpio_remove(struct platform_device *pdev) |
1481 | { | |
1482 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1483 | ||
b764a586 TL |
1484 | if (bank->nb.notifier_call) |
1485 | cpu_pm_unregister_notifier(&bank->nb); | |
cac089f9 TL |
1486 | list_del(&bank->node); |
1487 | gpiochip_remove(&bank->chip); | |
7b1e5dc8 | 1488 | pm_runtime_disable(&pdev->dev); |
5d9452e7 GS |
1489 | if (bank->dbck_flag) |
1490 | clk_unprepare(bank->dbck); | |
cac089f9 TL |
1491 | |
1492 | return 0; | |
1493 | } | |
1494 | ||
60a3437d | 1495 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1496 | |
b764a586 | 1497 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1498 | { |
b764a586 | 1499 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1500 | u32 l1 = 0, l2 = 0; |
68942edb | 1501 | |
ec0daae6 TL |
1502 | if (bank->funcs.idle_enable_level_quirk) |
1503 | bank->funcs.idle_enable_level_quirk(bank); | |
68942edb | 1504 | |
b3c64bc3 KH |
1505 | if (!bank->enabled_non_wakeup_gpios) |
1506 | goto update_gpio_context_count; | |
1507 | ||
b764a586 | 1508 | if (!may_lose_context) |
41d87cbd | 1509 | goto update_gpio_context_count; |
b764a586 | 1510 | |
2dc983c5 TKD |
1511 | /* |
1512 | * If going to OFF, remove triggering for all | |
1513 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1514 | * generated. See OMAP2420 Errata item 1.101. | |
1515 | */ | |
661553b9 | 1516 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1517 | bank->regs->datain); |
c6f31c9e TKD |
1518 | l1 = bank->context.fallingdetect; |
1519 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1520 | |
2dc983c5 TKD |
1521 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1522 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1523 | |
661553b9 VK |
1524 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1525 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1526 | |
2dc983c5 | 1527 | bank->workaround_enabled = true; |
3f1686a9 | 1528 | |
41d87cbd | 1529 | update_gpio_context_count: |
2dc983c5 TKD |
1530 | if (bank->get_context_loss_count) |
1531 | bank->context_loss_count = | |
7b1e5dc8 | 1532 | bank->get_context_loss_count(dev); |
60a3437d | 1533 | |
a0e827c6 | 1534 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1535 | } |
1536 | ||
352a2d5b JH |
1537 | static void omap_gpio_init_context(struct gpio_bank *p); |
1538 | ||
b764a586 | 1539 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1540 | { |
b764a586 | 1541 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1542 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1543 | int c; |
8865b9b6 | 1544 | |
352a2d5b JH |
1545 | /* |
1546 | * On the first resume during the probe, the context has not | |
1547 | * been initialised and so initialise it now. Also initialise | |
1548 | * the context loss count. | |
1549 | */ | |
1550 | if (bank->loses_context && !bank->context_valid) { | |
1551 | omap_gpio_init_context(bank); | |
1552 | ||
1553 | if (bank->get_context_loss_count) | |
1554 | bank->context_loss_count = | |
7b1e5dc8 | 1555 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1556 | } |
1557 | ||
a0e827c6 | 1558 | omap_gpio_dbck_enable(bank); |
68942edb | 1559 | |
ec0daae6 TL |
1560 | if (bank->funcs.idle_disable_level_quirk) |
1561 | bank->funcs.idle_disable_level_quirk(bank); | |
68942edb | 1562 | |
a2797bea JH |
1563 | if (bank->loses_context) { |
1564 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1565 | omap_gpio_restore_context(bank); |
1566 | } else { | |
7b1e5dc8 | 1567 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1568 | if (c != bank->context_loss_count) { |
1569 | omap_gpio_restore_context(bank); | |
1570 | } else { | |
b764a586 | 1571 | return; |
a2797bea | 1572 | } |
60a3437d | 1573 | } |
2dc983c5 | 1574 | } |
43ffcd9a | 1575 | |
b764a586 TL |
1576 | if (!bank->workaround_enabled) |
1577 | return; | |
1b128703 | 1578 | |
661553b9 | 1579 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1580 | |
2dc983c5 TKD |
1581 | /* |
1582 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1583 | * state. If so, generate an IRQ by software. This is | |
1584 | * horribly racy, but it's the best we can do to work around | |
1585 | * this silicon bug. | |
1586 | */ | |
1587 | l ^= bank->saved_datain; | |
1588 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1589 | |
2dc983c5 TKD |
1590 | /* |
1591 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1592 | * configured with falling edge only; and vice versa. | |
1593 | */ | |
c6f31c9e | 1594 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1595 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1596 | |
c6f31c9e | 1597 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1598 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1599 | |
2dc983c5 | 1600 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1601 | gen = l & (~(bank->context.fallingdetect) & |
1602 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1603 | /* Consider all GPIO IRQs needed to be updated */ |
1604 | gen |= gen0 | gen1; | |
82dbb9d3 | 1605 | |
2dc983c5 TKD |
1606 | if (gen) { |
1607 | u32 old0, old1; | |
82dbb9d3 | 1608 | |
661553b9 VK |
1609 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1610 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1611 | |
4e962e89 | 1612 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1613 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1614 | bank->regs->leveldetect0); |
661553b9 | 1615 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1616 | bank->regs->leveldetect1); |
2dc983c5 | 1617 | } |
9ea14d8c | 1618 | |
4e962e89 | 1619 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1620 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1621 | bank->regs->leveldetect0); |
661553b9 | 1622 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1623 | bank->regs->leveldetect1); |
3ac4fa99 | 1624 | } |
661553b9 VK |
1625 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1626 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1627 | } |
1628 | ||
1629 | bank->workaround_enabled = false; | |
2dc983c5 | 1630 | } |
2dc983c5 | 1631 | |
352a2d5b JH |
1632 | static void omap_gpio_init_context(struct gpio_bank *p) |
1633 | { | |
1634 | struct omap_gpio_reg_offs *regs = p->regs; | |
1635 | void __iomem *base = p->base; | |
1636 | ||
661553b9 VK |
1637 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1638 | p->context.oe = readl_relaxed(base + regs->direction); | |
1639 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1640 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1641 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1642 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1643 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1644 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1645 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1646 | |
1647 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1648 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1649 | else |
661553b9 | 1650 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1651 | |
1652 | p->context_valid = true; | |
1653 | } | |
1654 | ||
60a3437d | 1655 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1656 | { |
661553b9 | 1657 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1658 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1659 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1660 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1661 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1662 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1663 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1664 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1665 | bank->base + bank->regs->risingdetect); |
661553b9 | 1666 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1667 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1668 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1669 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1670 | bank->base + bank->regs->set_dataout); |
1671 | else | |
661553b9 | 1672 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1673 | bank->base + bank->regs->dataout); |
661553b9 | 1674 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1675 | |
ae547354 | 1676 | if (bank->dbck_enable_mask) { |
661553b9 | 1677 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1678 | bank->regs->debounce); |
661553b9 | 1679 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1680 | bank->base + bank->regs->debounce_en); |
1681 | } | |
ba805be5 | 1682 | |
661553b9 | 1683 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1684 | bank->base + bank->regs->irqenable); |
661553b9 | 1685 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1686 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1687 | } |
40c670f0 | 1688 | |
b764a586 TL |
1689 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) |
1690 | { | |
1691 | struct platform_device *pdev = to_platform_device(dev); | |
1692 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1693 | unsigned long flags; | |
1694 | int error = 0; | |
1695 | ||
1696 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1697 | /* Must be idled only by CPU_CLUSTER_PM_ENTER? */ | |
1698 | if (bank->irq_usage) { | |
1699 | error = -EBUSY; | |
1700 | goto unlock; | |
1701 | } | |
1702 | omap_gpio_idle(bank, true); | |
1703 | bank->is_suspended = true; | |
1704 | unlock: | |
1705 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1706 | ||
1707 | return error; | |
1708 | } | |
1709 | ||
1710 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1711 | { | |
1712 | struct platform_device *pdev = to_platform_device(dev); | |
1713 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1714 | unsigned long flags; | |
1715 | int error = 0; | |
1716 | ||
1717 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1718 | /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */ | |
1719 | if (bank->irq_usage) { | |
1720 | error = -EBUSY; | |
1721 | goto unlock; | |
1722 | } | |
1723 | omap_gpio_unidle(bank); | |
1724 | bank->is_suspended = false; | |
1725 | unlock: | |
1726 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1727 | ||
1728 | return error; | |
1729 | } | |
1730 | ||
1731 | #ifdef CONFIG_ARCH_OMAP2PLUS | |
55b93c32 | 1732 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1733 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1734 | NULL) | |
55b93c32 | 1735 | }; |
b764a586 TL |
1736 | #else |
1737 | static const struct dev_pm_ops gpio_pm_ops; | |
1738 | #endif /* CONFIG_ARCH_OMAP2PLUS */ | |
55b93c32 | 1739 | |
384ebe1c BC |
1740 | #if defined(CONFIG_OF) |
1741 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1742 | .revision = OMAP24XX_GPIO_REVISION, | |
1743 | .direction = OMAP24XX_GPIO_OE, | |
1744 | .datain = OMAP24XX_GPIO_DATAIN, | |
1745 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1746 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1747 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1748 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1749 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1750 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1751 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1752 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1753 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1754 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1755 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1756 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1757 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1758 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1759 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1760 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1761 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1762 | }; | |
1763 | ||
1764 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1765 | .revision = OMAP4_GPIO_REVISION, | |
1766 | .direction = OMAP4_GPIO_OE, | |
1767 | .datain = OMAP4_GPIO_DATAIN, | |
1768 | .dataout = OMAP4_GPIO_DATAOUT, | |
1769 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1770 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1771 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1772 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1773 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1774 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1775 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1776 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1777 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1778 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1779 | .ctrl = OMAP4_GPIO_CTRL, | |
1780 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1781 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1782 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1783 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1784 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1785 | }; | |
1786 | ||
b764a586 TL |
1787 | /* |
1788 | * Note that omap2 does not currently support idle modes with context loss so | |
1789 | * no need to add OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER quirk flag to save | |
1790 | * and restore context. | |
1791 | */ | |
e9a65bb6 | 1792 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1793 | .regs = &omap2_gpio_regs, |
1794 | .bank_width = 32, | |
1795 | .dbck_flag = false, | |
1796 | }; | |
1797 | ||
e9a65bb6 | 1798 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1799 | .regs = &omap2_gpio_regs, |
1800 | .bank_width = 32, | |
1801 | .dbck_flag = true, | |
b764a586 | 1802 | .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER, |
384ebe1c BC |
1803 | }; |
1804 | ||
e9a65bb6 | 1805 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1806 | .regs = &omap4_gpio_regs, |
1807 | .bank_width = 32, | |
1808 | .dbck_flag = true, | |
b764a586 TL |
1809 | .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER | |
1810 | OMAP_GPIO_QUIRK_DEFERRED_WKUP_EN, | |
384ebe1c BC |
1811 | }; |
1812 | ||
1813 | static const struct of_device_id omap_gpio_match[] = { | |
1814 | { | |
1815 | .compatible = "ti,omap4-gpio", | |
1816 | .data = &omap4_pdata, | |
1817 | }, | |
1818 | { | |
1819 | .compatible = "ti,omap3-gpio", | |
1820 | .data = &omap3_pdata, | |
1821 | }, | |
1822 | { | |
1823 | .compatible = "ti,omap2-gpio", | |
1824 | .data = &omap2_pdata, | |
1825 | }, | |
1826 | { }, | |
1827 | }; | |
1828 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1829 | #endif | |
1830 | ||
77640aab VC |
1831 | static struct platform_driver omap_gpio_driver = { |
1832 | .probe = omap_gpio_probe, | |
cac089f9 | 1833 | .remove = omap_gpio_remove, |
77640aab VC |
1834 | .driver = { |
1835 | .name = "omap_gpio", | |
55b93c32 | 1836 | .pm = &gpio_pm_ops, |
384ebe1c | 1837 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1838 | }, |
1839 | }; | |
1840 | ||
5e1c5ff4 | 1841 | /* |
77640aab VC |
1842 | * gpio driver register needs to be done before |
1843 | * machine_init functions access gpio APIs. | |
1844 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1845 | */ |
77640aab | 1846 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1847 | { |
77640aab | 1848 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1849 | } |
77640aab | 1850 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1851 | |
1852 | static void __exit omap_gpio_exit(void) | |
1853 | { | |
1854 | platform_driver_unregister(&omap_gpio_driver); | |
1855 | } | |
1856 | module_exit(omap_gpio_exit); | |
1857 | ||
1858 | MODULE_DESCRIPTION("omap gpio driver"); | |
1859 | MODULE_ALIAS("platform:gpio-omap"); | |
1860 | MODULE_LICENSE("GPL v2"); |