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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[linux-2.6-block.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
140455fa 37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 38 u32 suspend_wakeup;
39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
5e1c5ff4
TL		 57};
58
a8eb7ca0 59#ifdef CONFIG_ARCH_OMAP3
40c670f0 60struct omap3_gpio_regs {
40c670f0
RN		 61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
5492fb1a
SMK		 71};
72
40c670f0 73static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 74#endif
75
77640aab
VC		 76/*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80static struct gpio_bank *gpio_bank;
44169075 81
77640aab 82static int bank_width;
44169075 83
c95d10bc
VC		 84/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count;
5e1c5ff4
TL		 86
87static inline struct gpio_bank *get_gpio_bank(int gpio)
88{
6e60e79a 89 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
5e1c5ff4
TL		 94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
56739a69 99 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
92105bb7
TL		 104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
44169075 106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 107 return &gpio_bank[gpio >> 5];
e031ab23
DB		 108 BUG();
109 return NULL;
5e1c5ff4
TL		 110}
111
112static inline int get_gpio_index(int gpio)
113{
56739a69 114 if (cpu_is_omap7xx())
5e1c5ff4 115 return gpio & 0x1f;
92105bb7
TL		 116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
44169075 118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 119 return gpio & 0x1f;
92105bb7 120 return gpio & 0x0f;
5e1c5ff4
TL		 121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
d11ac979 127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 129 return -1;
130 return 0;
131 }
6e60e79a 132 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 133 return 0;
5e1c5ff4
TL		 134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
56739a69 136 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 137 return 0;
25d6f630
TL		 138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
92105bb7 141 return 0;
44169075 142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 143 return 0;
5e1c5ff4
TL		 144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
d32b20fc 149 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{
92105bb7 159 void __iomem *reg = bank->base;
5e1c5ff4
TL		 160 u32 l;
161
162 switch (bank->method) {
e5c56ed3 163#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 164 case METHOD_MPUIO:
5de62b86 165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
5e1c5ff4 166 break;
e5c56ed3
DB		 167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
e5c56ed3
DB		 172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
e5c56ed3 177#endif
b718aa81 178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 181 break;
182#endif
a8eb7ca0 183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
78a1a6d3
SR		 187#endif
188#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 189 case METHOD_GPIO_44XX:
78a1a6d3
SR		 190 reg += OMAP4_GPIO_OE;
191 break;
e5c56ed3
DB		 192#endif
193 default:
194 WARN_ON(1);
195 return;
5e1c5ff4
TL		 196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203}
204
5e1c5ff4
TL		 205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206{
92105bb7 207 void __iomem *reg = bank->base;
5e1c5ff4
TL		 208 u32 l = 0;
209
210 switch (bank->method) {
e5c56ed3 211#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 212 case METHOD_MPUIO:
5de62b86 213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
5e1c5ff4
TL		 214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
e5c56ed3
DB		 220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
e5c56ed3
DB		 230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
e5c56ed3 239#endif
b718aa81 240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
a8eb7ca0 250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
78a1a6d3
SR		 258#endif
259#ifdef CONFIG_ARCH_OMAP4
3f1686a9 260 case METHOD_GPIO_44XX:
78a1a6d3
SR		 261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
e5c56ed3 267#endif
5e1c5ff4 268 default:
e5c56ed3 269 WARN_ON(1);
5e1c5ff4
TL		 270 return;
271 }
272 __raw_writel(l, reg);
273}
274
b37c45b8 275static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 276{
92105bb7 277 void __iomem *reg;
5e1c5ff4
TL		 278
279 if (check_gpio(gpio) < 0)
e5c56ed3 280 return -EINVAL;
5e1c5ff4
TL		 281 reg = bank->base;
282 switch (bank->method) {
e5c56ed3 283#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 284 case METHOD_MPUIO:
5de62b86 285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
5e1c5ff4 286 break;
e5c56ed3
DB		 287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
e5c56ed3
DB		 292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
e5c56ed3 297#endif
b718aa81 298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 301 break;
302#endif
a8eb7ca0 303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
78a1a6d3
SR		 307#endif
308#ifdef CONFIG_ARCH_OMAP4
3f1686a9 309 case METHOD_GPIO_44XX:
78a1a6d3
SR		 310 reg += OMAP4_GPIO_DATAIN;
311 break;
e5c56ed3 312#endif
5e1c5ff4 313 default:
e5c56ed3 314 return -EINVAL;
5e1c5ff4 315 }
92105bb7
TL		 316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 318}
319
b37c45b8
RQ		 320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321{
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329#ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
5de62b86 331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
b37c45b8
RQ		 332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
b718aa81 344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 347 break;
348#endif
9f096868 349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
9f096868
C		 353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
b37c45b8
RQ		 358#endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364}
365
92105bb7
TL		 366#define MOD_REG_BIT(reg, bit_mask, set) \
367do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372} while(0)
373
168ef3d9
FB		 374/**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385{
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
77640aab
VC		 390 if (!bank->dbck_flag)
391 return;
392
168ef3d9
FB		 393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
77640aab 402 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
77640aab 410 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
77640aab 419 clk_enable(bank->dbck);
168ef3d9
FB		 420 } else {
421 val &= ~l;
77640aab 422 clk_disable(bank->dbck);
168ef3d9 423 }
f7ec0b0b 424 bank->dbck_enable_mask = val;
168ef3d9
FB		 425
426 __raw_writel(val, reg);
427}
428
140455fa 429#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 430static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
5e1c5ff4 432{
3ac4fa99 433 void __iomem *base = bank->base;
92105bb7
TL		 434 u32 gpio_bit = 1 << gpio;
435
78a1a6d3
SR		 436 if (cpu_is_omap44xx()) {
437 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
438 trigger & IRQ_TYPE_LEVEL_LOW);
439 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
440 trigger & IRQ_TYPE_LEVEL_HIGH);
441 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
442 trigger & IRQ_TYPE_EDGE_RISING);
443 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
444 trigger & IRQ_TYPE_EDGE_FALLING);
445 } else {
446 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
447 trigger & IRQ_TYPE_LEVEL_LOW);
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
449 trigger & IRQ_TYPE_LEVEL_HIGH);
450 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
451 trigger & IRQ_TYPE_EDGE_RISING);
452 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
453 trigger & IRQ_TYPE_EDGE_FALLING);
454 }
3ac4fa99 455 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 456 if (cpu_is_omap44xx()) {
0622b25b
CC		 457 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
458 trigger != 0);
78a1a6d3 459 } else {
699117a6
CW		 460 /*
461 * GPIO wakeup request can only be generated on edge
462 * transitions
463 */
464 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 465 __raw_writel(1 << gpio, bank->base
5eb3bb9c 466 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 467 else
468 __raw_writel(1 << gpio, bank->base
5eb3bb9c 469 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 470 }
a118b5f3 471 }
55b220ca
A		 472 /* This part needs to be executed always for OMAP{34xx, 44xx} */
473 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
474 (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 475 /*
476 * Log the edge gpio and manually trigger the IRQ
477 * after resume if the input level changes
478 * to avoid irq lost during PER RET/OFF mode
479 * Applies for omap2 non-wakeup gpio and all omap3 gpios
480 */
481 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 482 bank->enabled_non_wakeup_gpios |= gpio_bit;
483 else
484 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
485 }
5eb3bb9c 486
78a1a6d3
SR		 487 if (cpu_is_omap44xx()) {
488 bank->level_mask =
489 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
490 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
491 } else {
492 bank->level_mask =
493 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
494 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
495 }
92105bb7 496}
3ac4fa99 497#endif
92105bb7 498
9198bcd3 499#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 500/*
501 * This only applies to chips that can't do both rising and falling edge
502 * detection at once. For all other chips, this function is a noop.
503 */
504static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
505{
506 void __iomem *reg = bank->base;
507 u32 l = 0;
508
509 switch (bank->method) {
4318f36b 510 case METHOD_MPUIO:
5de62b86 511 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 512 break;
4318f36b
CM		 513#ifdef CONFIG_ARCH_OMAP15XX
514 case METHOD_GPIO_1510:
515 reg += OMAP1510_GPIO_INT_CONTROL;
516 break;
517#endif
518#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
519 case METHOD_GPIO_7XX:
520 reg += OMAP7XX_GPIO_INT_CONTROL;
521 break;
522#endif
523 default:
524 return;
525 }
526
527 l = __raw_readl(reg);
528 if ((l >> gpio) & 1)
529 l &= ~(1 << gpio);
530 else
531 l |= 1 << gpio;
532
533 __raw_writel(l, reg);
534}
9198bcd3 535#endif
4318f36b 536
92105bb7
TL		 537static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
538{
539 void __iomem *reg = bank->base;
540 u32 l = 0;
5e1c5ff4
TL		 541
542 switch (bank->method) {
e5c56ed3 543#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 544 case METHOD_MPUIO:
5de62b86 545 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 546 l = __raw_readl(reg);
29501577 547 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 548 bank->toggle_mask |= 1 << gpio;
6cab4860 549 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 550 l |= 1 << gpio;
6cab4860 551 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 552 l &= ~(1 << gpio);
92105bb7
TL		 553 else
554 goto bad;
5e1c5ff4 555 break;
e5c56ed3
DB		 556#endif
557#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 558 case METHOD_GPIO_1510:
559 reg += OMAP1510_GPIO_INT_CONTROL;
560 l = __raw_readl(reg);
29501577 561 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 562 bank->toggle_mask |= 1 << gpio;
6cab4860 563 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 564 l |= 1 << gpio;
6cab4860 565 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 566 l &= ~(1 << gpio);
92105bb7
TL		 567 else
568 goto bad;
5e1c5ff4 569 break;
e5c56ed3 570#endif
3ac4fa99 571#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 572 case METHOD_GPIO_1610:
5e1c5ff4
TL		 573 if (gpio & 0x08)
574 reg += OMAP1610_GPIO_EDGE_CTRL2;
575 else
576 reg += OMAP1610_GPIO_EDGE_CTRL1;
577 gpio &= 0x07;
578 l = __raw_readl(reg);
579 l &= ~(3 << (gpio << 1));
6cab4860 580 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 581 l |= 2 << (gpio << 1);
6cab4860 582 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 583 l |= 1 << (gpio << 1);
3ac4fa99
JY		 584 if (trigger)
585 /* Enable wake-up during idle for dynamic tick */
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
587 else
588 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 589 break;
3ac4fa99 590#endif
b718aa81 591#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 592 case METHOD_GPIO_7XX:
593 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 594 l = __raw_readl(reg);
29501577 595 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 596 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 597 if (trigger & IRQ_TYPE_EDGE_RISING)
598 l |= 1 << gpio;
599 else if (trigger & IRQ_TYPE_EDGE_FALLING)
600 l &= ~(1 << gpio);
601 else
602 goto bad;
603 break;
604#endif
140455fa 605#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 606 case METHOD_GPIO_24XX:
3f1686a9 607 case METHOD_GPIO_44XX:
3ac4fa99 608 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 609 return 0;
3ac4fa99 610#endif
5e1c5ff4 611 default:
92105bb7 612 goto bad;
5e1c5ff4 613 }
92105bb7
TL		 614 __raw_writel(l, reg);
615 return 0;
616bad:
617 return -EINVAL;
5e1c5ff4
TL		 618}
619
e9191028 620static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 621{
622 struct gpio_bank *bank;
92105bb7
TL		 623 unsigned gpio;
624 int retval;
a6472533 625 unsigned long flags;
92105bb7 626
e9191028
LB		 627 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
628 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 629 else
e9191028 630 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4
TL		 631
632 if (check_gpio(gpio) < 0)
92105bb7
TL		 633 return -EINVAL;
634
e5c56ed3 635 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 636 return -EINVAL;
e5c56ed3
DB		 637
638 /* OMAP1 allows only only edge triggering */
5492fb1a 639 if (!cpu_class_is_omap2()
e5c56ed3 640 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 641 return -EINVAL;
642
e9191028 643 bank = irq_data_get_irq_chip_data(d);
a6472533 644 spin_lock_irqsave(&bank->lock, flags);
92105bb7 645 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
a6472533 646 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 647
648 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 649 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 650 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 651 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 652
92105bb7 653 return retval;
5e1c5ff4
TL		 654}
655
656static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657{
92105bb7 658 void __iomem *reg = bank->base;
5e1c5ff4
TL		 659
660 switch (bank->method) {
e5c56ed3 661#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 662 case METHOD_MPUIO:
663 /* MPUIO irqstatus is reset by reading the status register,
664 * so do nothing here */
665 return;
e5c56ed3
DB		 666#endif
667#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 668 case METHOD_GPIO_1510:
669 reg += OMAP1510_GPIO_INT_STATUS;
670 break;
e5c56ed3
DB		 671#endif
672#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 673 case METHOD_GPIO_1610:
674 reg += OMAP1610_GPIO_IRQSTATUS1;
675 break;
e5c56ed3 676#endif
b718aa81 677#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 678 case METHOD_GPIO_7XX:
679 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 680 break;
681#endif
a8eb7ca0 682#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 683 case METHOD_GPIO_24XX:
684 reg += OMAP24XX_GPIO_IRQSTATUS1;
685 break;
78a1a6d3
SR		 686#endif
687#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 688 case METHOD_GPIO_44XX:
78a1a6d3
SR		 689 reg += OMAP4_GPIO_IRQSTATUS0;
690 break;
e5c56ed3 691#endif
5e1c5ff4 692 default:
e5c56ed3 693 WARN_ON(1);
5e1c5ff4
TL		 694 return;
695 }
696 __raw_writel(gpio_mask, reg);
bee7930f
HD		 697
698 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 699 if (cpu_is_omap24xx() || cpu_is_omap34xx())
700 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
701 else if (cpu_is_omap44xx())
702 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
703
78a1a6d3 704 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 705 __raw_writel(gpio_mask, reg);
706
707 /* Flush posted write for the irq status to avoid spurious interrupts */
708 __raw_readl(reg);
78a1a6d3 709 }
5e1c5ff4
TL		 710}
711
712static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
713{
714 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
715}
716
ea6dedd7
ID		 717static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
718{
719 void __iomem *reg = bank->base;
99c47707
ID		 720 int inv = 0;
721 u32 l;
722 u32 mask;
ea6dedd7
ID		 723
724 switch (bank->method) {
e5c56ed3 725#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 726 case METHOD_MPUIO:
5de62b86 727 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707
ID		 728 mask = 0xffff;
729 inv = 1;
ea6dedd7 730 break;
e5c56ed3
DB		 731#endif
732#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 733 case METHOD_GPIO_1510:
734 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 735 mask = 0xffff;
736 inv = 1;
ea6dedd7 737 break;
e5c56ed3
DB		 738#endif
739#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 740 case METHOD_GPIO_1610:
741 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 742 mask = 0xffff;
ea6dedd7 743 break;
e5c56ed3 744#endif
b718aa81 745#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 746 case METHOD_GPIO_7XX:
747 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 748 mask = 0xffffffff;
749 inv = 1;
750 break;
751#endif
a8eb7ca0 752#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 753 case METHOD_GPIO_24XX:
754 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 755 mask = 0xffffffff;
ea6dedd7 756 break;
78a1a6d3
SR		 757#endif
758#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 759 case METHOD_GPIO_44XX:
78a1a6d3
SR		 760 reg += OMAP4_GPIO_IRQSTATUSSET0;
761 mask = 0xffffffff;
762 break;
e5c56ed3 763#endif
ea6dedd7 764 default:
e5c56ed3 765 WARN_ON(1);
ea6dedd7
ID		 766 return 0;
767 }
768
99c47707
ID		 769 l = __raw_readl(reg);
770 if (inv)
771 l = ~l;
772 l &= mask;
773 return l;
ea6dedd7
ID		 774}
775
5e1c5ff4
TL		 776static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
777{
92105bb7 778 void __iomem *reg = bank->base;
5e1c5ff4
TL		 779 u32 l;
780
781 switch (bank->method) {
e5c56ed3 782#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 783 case METHOD_MPUIO:
5de62b86 784 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 785 l = __raw_readl(reg);
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
e5c56ed3
DB		 791#endif
792#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_MASK;
795 l = __raw_readl(reg);
796 if (enable)
797 l &= ~(gpio_mask);
798 else
799 l |= gpio_mask;
800 break;
e5c56ed3
DB		 801#endif
802#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 803 case METHOD_GPIO_1610:
804 if (enable)
805 reg += OMAP1610_GPIO_SET_IRQENABLE1;
806 else
807 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
808 l = gpio_mask;
809 break;
e5c56ed3 810#endif
b718aa81 811#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 812 case METHOD_GPIO_7XX:
813 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 814 l = __raw_readl(reg);
815 if (enable)
816 l &= ~(gpio_mask);
817 else
818 l |= gpio_mask;
819 break;
820#endif
a8eb7ca0 821#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 822 case METHOD_GPIO_24XX:
823 if (enable)
824 reg += OMAP24XX_GPIO_SETIRQENABLE1;
825 else
826 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
827 l = gpio_mask;
828 break;
78a1a6d3
SR		 829#endif
830#ifdef CONFIG_ARCH_OMAP4
3f1686a9 831 case METHOD_GPIO_44XX:
78a1a6d3
SR		 832 if (enable)
833 reg += OMAP4_GPIO_IRQSTATUSSET0;
834 else
835 reg += OMAP4_GPIO_IRQSTATUSCLR0;
836 l = gpio_mask;
837 break;
e5c56ed3 838#endif
5e1c5ff4 839 default:
e5c56ed3 840 WARN_ON(1);
5e1c5ff4
TL		 841 return;
842 }
843 __raw_writel(l, reg);
844}
845
846static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
847{
848 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
849}
850
92105bb7
TL		 851/*
852 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
853 * 1510 does not seem to have a wake-up register. If JTAG is connected
854 * to the target, system will wake up always on GPIO events. While
855 * system is running all registered GPIO interrupts need to have wake-up
856 * enabled. When system is suspended, only selected GPIO interrupts need
857 * to have wake-up enabled.
858 */
859static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
860{
4cc6420c 861 unsigned long uninitialized_var(flags);
a6472533 862
92105bb7 863 switch (bank->method) {
3ac4fa99 864#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 865 case METHOD_MPUIO:
92105bb7 866 case METHOD_GPIO_1610:
a6472533 867 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 868 if (enable)
92105bb7 869 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 870 else
92105bb7 871 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 872 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 873 return 0;
3ac4fa99 874#endif
140455fa 875#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 876 case METHOD_GPIO_24XX:
3f1686a9 877 case METHOD_GPIO_44XX:
11a78b79
DB		 878 if (bank->non_wakeup_gpios & (1 << gpio)) {
879 printk(KERN_ERR "Unable to modify wakeup on "
880 "non-wakeup GPIO%d\n",
881 (bank - gpio_bank) * 32 + gpio);
882 return -EINVAL;
883 }
a6472533 884 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 885 if (enable)
3ac4fa99 886 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 887 else
3ac4fa99 888 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 889 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 890 return 0;
891#endif
92105bb7
TL		 892 default:
893 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
894 bank->method);
895 return -EINVAL;
896 }
897}
898
4196dd6b
TL		 899static void _reset_gpio(struct gpio_bank *bank, int gpio)
900{
901 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
902 _set_gpio_irqenable(bank, gpio, 0);
903 _clear_gpio_irqstatus(bank, gpio);
6cab4860 904 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 905}
906
92105bb7 907/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 908static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 909{
e9191028 910 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 911 struct gpio_bank *bank;
912 int retval;
913
914 if (check_gpio(gpio) < 0)
915 return -ENODEV;
e9191028 916 bank = irq_data_get_irq_chip_data(d);
92105bb7 917 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 918
919 return retval;
920}
921
3ff164e1 922static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 923{
3ff164e1 924 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 925 unsigned long flags;
52e31344 926
a6472533 927 spin_lock_irqsave(&bank->lock, flags);
92105bb7 928
4196dd6b
TL		 929 /* Set trigger to none. You need to enable the desired trigger with
930 * request_irq() or set_irq_type().
931 */
3ff164e1 932 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 933
1a8bfa1e 934#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 935 if (bank->method == METHOD_GPIO_1510) {
92105bb7 936 void __iomem *reg;
5e1c5ff4 937
92105bb7 938 /* Claim the pin for MPU */
5e1c5ff4 939 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 940 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 941 }
942#endif
058af1ea
C		 943 if (!cpu_class_is_omap1()) {
944 if (!bank->mod_usage) {
9f096868 945 void __iomem *reg = bank->base;
058af1ea 946 u32 ctrl;
9f096868
C		 947
948 if (cpu_is_omap24xx() || cpu_is_omap34xx())
949 reg += OMAP24XX_GPIO_CTRL;
950 else if (cpu_is_omap44xx())
951 reg += OMAP4_GPIO_CTRL;
952 ctrl = __raw_readl(reg);
058af1ea 953 /* Module is enabled, clocks are not gated */
9f096868
C		 954 ctrl &= 0xFFFFFFFE;
955 __raw_writel(ctrl, reg);
058af1ea
C		 956 }
957 bank->mod_usage |= 1 << offset;
958 }
a6472533 959 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 960
961 return 0;
962}
963
3ff164e1 964static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 965{
3ff164e1 966 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 967 unsigned long flags;
5e1c5ff4 968
a6472533 969 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 970#ifdef CONFIG_ARCH_OMAP16XX
971 if (bank->method == METHOD_GPIO_1610) {
972 /* Disable wake-up during idle for dynamic tick */
973 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 974 __raw_writel(1 << offset, reg);
92105bb7
TL		 975 }
976#endif
9f096868
C		 977#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
978 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 981 __raw_writel(1 << offset, reg);
92105bb7 982 }
9f096868
C		 983#endif
984#ifdef CONFIG_ARCH_OMAP4
985 if (bank->method == METHOD_GPIO_44XX) {
986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
988 __raw_writel(1 << offset, reg);
989 }
92105bb7 990#endif
058af1ea
C		 991 if (!cpu_class_is_omap1()) {
992 bank->mod_usage &= ~(1 << offset);
993 if (!bank->mod_usage) {
9f096868 994 void __iomem *reg = bank->base;
058af1ea 995 u32 ctrl;
9f096868
C		 996
997 if (cpu_is_omap24xx() || cpu_is_omap34xx())
998 reg += OMAP24XX_GPIO_CTRL;
999 else if (cpu_is_omap44xx())
1000 reg += OMAP4_GPIO_CTRL;
1001 ctrl = __raw_readl(reg);
058af1ea
C		 1002 /* Module is disabled, clocks are gated */
1003 ctrl |= 1;
9f096868 1004 __raw_writel(ctrl, reg);
058af1ea
C		 1005 }
1006 }
3ff164e1 1007 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1008 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1009}
1010
1011/*
1012 * We need to unmask the GPIO bank interrupt as soon as possible to
1013 * avoid missing GPIO interrupts for other lines in the bank.
1014 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1015 * in the bank to avoid missing nested interrupts for a GPIO line.
1016 * If we wait to unmask individual GPIO lines in the bank after the
1017 * line's interrupt handler has been run, we may miss some nested
1018 * interrupts.
1019 */
10dd5ce2 1020static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1021{
92105bb7 1022 void __iomem *isr_reg = NULL;
5e1c5ff4 1023 u32 isr;
4318f36b 1024 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1025 struct gpio_bank *bank;
ea6dedd7
ID		 1026 u32 retrigger = 0;
1027 int unmasked = 0;
ee144182 1028 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 1029
ee144182 1030 chained_irq_enter(chip, desc);
5e1c5ff4 1031
6845664a 1032 bank = irq_get_handler_data(irq);
e5c56ed3 1033#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 1034 if (bank->method == METHOD_MPUIO)
5de62b86
TL		 1035 isr_reg = bank->base +
1036 OMAP_MPUIO_GPIO_INT / bank->stride;
e5c56ed3 1037#endif
1a8bfa1e 1038#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1039 if (bank->method == METHOD_GPIO_1510)
1040 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1041#endif
1042#if defined(CONFIG_ARCH_OMAP16XX)
1043 if (bank->method == METHOD_GPIO_1610)
1044 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1045#endif
b718aa81 1046#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1047 if (bank->method == METHOD_GPIO_7XX)
1048 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1049#endif
a8eb7ca0 1050#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1051 if (bank->method == METHOD_GPIO_24XX)
1052 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1053#endif
1054#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1055 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1056 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1057#endif
b1cc4c55
EK		 1058
1059 if (WARN_ON(!isr_reg))
1060 goto exit;
1061
92105bb7 1062 while(1) {
6e60e79a 1063 u32 isr_saved, level_mask = 0;
ea6dedd7 1064 u32 enabled;
6e60e79a 1065
ea6dedd7
ID		 1066 enabled = _get_gpio_irqbank_mask(bank);
1067 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1068
1069 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1070 isr &= 0x0000ffff;
1071
5492fb1a 1072 if (cpu_class_is_omap2()) {
b144ff6f 1073 level_mask = bank->level_mask & enabled;
ea6dedd7 1074 }
6e60e79a
TL		 1075
1076 /* clear edge sensitive interrupts before handler(s) are
1077 called so that we don't miss any interrupt occurred while
1078 executing them */
1079 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1080 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1081 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1082
1083 /* if there is only edge sensitive GPIO pin interrupts
1084 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1085 if (!level_mask && !unmasked) {
1086 unmasked = 1;
ee144182 1087 chained_irq_exit(chip, desc);
ea6dedd7 1088 }
92105bb7 1089
ea6dedd7
ID		 1090 isr |= retrigger;
1091 retrigger = 0;
92105bb7
TL		 1092 if (!isr)
1093 break;
1094
1095 gpio_irq = bank->virtual_irq_start;
1096 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1097 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1098
92105bb7
TL		 1099 if (!(isr & 1))
1100 continue;
29454dde 1101
4318f36b
CM		 1102#ifdef CONFIG_ARCH_OMAP1
1103 /*
1104 * Some chips can't respond to both rising and falling
1105 * at the same time. If this irq was requested with
1106 * both flags, we need to flip the ICR data for the IRQ
1107 * to respond to the IRQ for the opposite direction.
1108 * This will be indicated in the bank toggle_mask.
1109 */
1110 if (bank->toggle_mask & (1 << gpio_index))
1111 _toggle_gpio_edge_triggering(bank, gpio_index);
1112#endif
1113
d8aa0251 1114 generic_handle_irq(gpio_irq);
92105bb7 1115 }
1a8bfa1e 1116 }
ea6dedd7
ID		 1117 /* if bank has any level sensitive GPIO pin interrupt
1118 configured, we must unmask the bank interrupt only after
1119 handler(s) are executed in order to avoid spurious bank
1120 interrupt */
b1cc4c55 1121exit:
ea6dedd7 1122 if (!unmasked)
ee144182 1123 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 1124}
1125
e9191028 1126static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 1127{
e9191028
LB		 1128 unsigned int gpio = d->irq - IH_GPIO_BASE;
1129 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 1130 unsigned long flags;
4196dd6b 1131
85ec7b97 1132 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 1133 _reset_gpio(bank, gpio);
85ec7b97 1134 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 1135}
1136
e9191028 1137static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 1138{
e9191028
LB		 1139 unsigned int gpio = d->irq - IH_GPIO_BASE;
1140 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1141
1142 _clear_gpio_irqstatus(bank, gpio);
1143}
1144
e9191028 1145static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 1146{
e9191028
LB		 1147 unsigned int gpio = d->irq - IH_GPIO_BASE;
1148 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 1149 unsigned long flags;
5e1c5ff4 1150
85ec7b97 1151 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 1152 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1153 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
85ec7b97 1154 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1155}
1156
e9191028 1157static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 1158{
e9191028
LB		 1159 unsigned int gpio = d->irq - IH_GPIO_BASE;
1160 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
b144ff6f 1161 unsigned int irq_mask = 1 << get_gpio_index(gpio);
8c04a176 1162 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 1163 unsigned long flags;
55b6019a 1164
85ec7b97 1165 spin_lock_irqsave(&bank->lock, flags);
55b6019a
KH		 1166 if (trigger)
1167 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1168
1169 /* For level-triggered GPIOs, the clearing must be done after
1170 * the HW source is cleared, thus after the handler has run */
1171 if (bank->level_mask & irq_mask) {
1172 _set_gpio_irqenable(bank, gpio, 0);
1173 _clear_gpio_irqstatus(bank, gpio);
1174 }
5e1c5ff4 1175
4de8c75b 1176 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 1177 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1178}
1179
e5c56ed3
DB		 1180static struct irq_chip gpio_irq_chip = {
1181 .name = "GPIO",
e9191028
LB		 1182 .irq_shutdown = gpio_irq_shutdown,
1183 .irq_ack = gpio_ack_irq,
1184 .irq_mask = gpio_mask_irq,
1185 .irq_unmask = gpio_unmask_irq,
1186 .irq_set_type = gpio_irq_type,
1187 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 1188};
1189
1190/*---------------------------------------------------------------------*/
1191
1192#ifdef CONFIG_ARCH_OMAP1
1193
1194/* MPUIO uses the always-on 32k clock */
1195
e9191028 1196static void mpuio_ack_irq(struct irq_data *d)
5e1c5ff4
TL		 1197{
1198 /* The ISR is reset automatically, so do nothing here. */
1199}
1200
e9191028 1201static void mpuio_mask_irq(struct irq_data *d)
5e1c5ff4 1202{
e9191028
LB		 1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1205
1206 _set_gpio_irqenable(bank, gpio, 0);
1207}
1208
e9191028 1209static void mpuio_unmask_irq(struct irq_data *d)
5e1c5ff4 1210{
e9191028
LB		 1211 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1212 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1213
1214 _set_gpio_irqenable(bank, gpio, 1);
1215}
1216
e5c56ed3
DB		 1217static struct irq_chip mpuio_irq_chip = {
1218 .name = "MPUIO",
e9191028
LB		 1219 .irq_ack = mpuio_ack_irq,
1220 .irq_mask = mpuio_mask_irq,
1221 .irq_unmask = mpuio_unmask_irq,
1222 .irq_set_type = gpio_irq_type,
11a78b79
DB		 1223#ifdef CONFIG_ARCH_OMAP16XX
1224 /* REVISIT: assuming only 16xx supports MPUIO wake events */
e9191028 1225 .irq_set_wake = gpio_wake_enable,
11a78b79 1226#endif
5e1c5ff4
TL		 1227};
1228
e5c56ed3
DB		 1229
1230#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231
11a78b79
DB		 1232
1233#ifdef CONFIG_ARCH_OMAP16XX
1234
1235#include <linux/platform_device.h>
1236
79ee031f 1237static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1238{
79ee031f 1239 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1240 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1241 void __iomem *mask_reg = bank->base +
1242 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1243 unsigned long flags;
11a78b79 1244
a6472533 1245 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1246 bank->saved_wakeup = __raw_readl(mask_reg);
1247 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1248 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1249
1250 return 0;
1251}
1252
79ee031f 1253static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1254{
79ee031f 1255 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1256 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1257 void __iomem *mask_reg = bank->base +
1258 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1259 unsigned long flags;
11a78b79 1260
a6472533 1261 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1262 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1263 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1264
1265 return 0;
1266}
1267
47145210 1268static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1269 .suspend_noirq = omap_mpuio_suspend_noirq,
1270 .resume_noirq = omap_mpuio_resume_noirq,
1271};
1272
3c437ffd 1273/* use platform_driver for this. */
11a78b79 1274static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1275 .driver = {
1276 .name = "mpuio",
79ee031f 1277 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1278 },
1279};
1280
1281static struct platform_device omap_mpuio_device = {
1282 .name = "mpuio",
1283 .id = -1,
1284 .dev = {
1285 .driver = &omap_mpuio_driver.driver,
1286 }
1287 /* could list the /proc/iomem resources */
1288};
1289
1290static inline void mpuio_init(void)
1291{
77640aab
VC		 1292 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1293 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1294
11a78b79
DB		 1295 if (platform_driver_register(&omap_mpuio_driver) == 0)
1296 (void) platform_device_register(&omap_mpuio_device);
1297}
1298
1299#else
1300static inline void mpuio_init(void) {}
1301#endif /* 16xx */
1302
e5c56ed3
DB		 1303#else
1304
1305extern struct irq_chip mpuio_irq_chip;
1306
1307#define bank_is_mpuio(bank) 0
11a78b79 1308static inline void mpuio_init(void) {}
e5c56ed3
DB		 1309
1310#endif
1311
1312/*---------------------------------------------------------------------*/
5e1c5ff4 1313
52e31344
DB		 1314/* REVISIT these are stupid implementations! replace by ones that
1315 * don't switch on METHOD_* and which mostly avoid spinlocks
1316 */
1317
1318static int gpio_input(struct gpio_chip *chip, unsigned offset)
1319{
1320 struct gpio_bank *bank;
1321 unsigned long flags;
1322
1323 bank = container_of(chip, struct gpio_bank, chip);
1324 spin_lock_irqsave(&bank->lock, flags);
1325 _set_gpio_direction(bank, offset, 1);
1326 spin_unlock_irqrestore(&bank->lock, flags);
1327 return 0;
1328}
1329
b37c45b8
RQ		 1330static int gpio_is_input(struct gpio_bank *bank, int mask)
1331{
1332 void __iomem *reg = bank->base;
1333
1334 switch (bank->method) {
1335 case METHOD_MPUIO:
5de62b86 1336 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
b37c45b8
RQ		 1337 break;
1338 case METHOD_GPIO_1510:
1339 reg += OMAP1510_GPIO_DIR_CONTROL;
1340 break;
1341 case METHOD_GPIO_1610:
1342 reg += OMAP1610_GPIO_DIRECTION;
1343 break;
7c006926
AB		 1344 case METHOD_GPIO_7XX:
1345 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1346 break;
1347 case METHOD_GPIO_24XX:
1348 reg += OMAP24XX_GPIO_OE;
1349 break;
9f096868
C		 1350 case METHOD_GPIO_44XX:
1351 reg += OMAP4_GPIO_OE;
1352 break;
1353 default:
1354 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return -EINVAL;
b37c45b8
RQ		 1356 }
1357 return __raw_readl(reg) & mask;
1358}
1359
52e31344
DB		 1360static int gpio_get(struct gpio_chip *chip, unsigned offset)
1361{
b37c45b8
RQ		 1362 struct gpio_bank *bank;
1363 void __iomem *reg;
1364 int gpio;
1365 u32 mask;
1366
1367 gpio = chip->base + offset;
1368 bank = get_gpio_bank(gpio);
1369 reg = bank->base;
1370 mask = 1 << get_gpio_index(gpio);
1371
1372 if (gpio_is_input(bank, mask))
1373 return _get_gpio_datain(bank, gpio);
1374 else
1375 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1376}
1377
1378static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1379{
1380 struct gpio_bank *bank;
1381 unsigned long flags;
1382
1383 bank = container_of(chip, struct gpio_bank, chip);
1384 spin_lock_irqsave(&bank->lock, flags);
1385 _set_gpio_dataout(bank, offset, value);
1386 _set_gpio_direction(bank, offset, 0);
1387 spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0;
1389}
1390
168ef3d9
FB		 1391static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1392 unsigned debounce)
1393{
1394 struct gpio_bank *bank;
1395 unsigned long flags;
1396
1397 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1398
1399 if (!bank->dbck) {
1400 bank->dbck = clk_get(bank->dev, "dbclk");
1401 if (IS_ERR(bank->dbck))
1402 dev_err(bank->dev, "Could not get gpio dbck\n");
1403 }
1404
168ef3d9
FB		 1405 spin_lock_irqsave(&bank->lock, flags);
1406 _set_gpio_debounce(bank, offset, debounce);
1407 spin_unlock_irqrestore(&bank->lock, flags);
1408
1409 return 0;
1410}
1411
52e31344
DB		 1412static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1413{
1414 struct gpio_bank *bank;
1415 unsigned long flags;
1416
1417 bank = container_of(chip, struct gpio_bank, chip);
1418 spin_lock_irqsave(&bank->lock, flags);
1419 _set_gpio_dataout(bank, offset, value);
1420 spin_unlock_irqrestore(&bank->lock, flags);
1421}
1422
a007b709
DB		 1423static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1424{
1425 struct gpio_bank *bank;
1426
1427 bank = container_of(chip, struct gpio_bank, chip);
1428 return bank->virtual_irq_start + offset;
1429}
1430
52e31344
DB		 1431/*---------------------------------------------------------------------*/
1432
9a748053 1433static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1434{
1435 u32 rev;
1436
9a748053
TL		 1437 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1438 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1439 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1440 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1441 else if (cpu_is_omap44xx())
9a748053 1442 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1443 else
1444 return;
1445
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f);
1448}
1449
8ba55c5c
DB		 1450/* This lock class tells lockdep that GPIO irqs are in a different
1451 * category than their parents, so it won't report false recursion.
1452 */
1453static struct lock_class_key gpio_lock_class;
1454
77640aab
VC		 1455static inline int init_gpio_info(struct platform_device *pdev)
1456{
1457 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1458 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1459 GFP_KERNEL);
1460 if (!gpio_bank) {
1461 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1462 return -ENOMEM;
1463 }
1464 return 0;
1465}
1466
1467/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1468static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1469{
1470 if (cpu_class_is_omap2()) {
1471 if (cpu_is_omap44xx()) {
1472 __raw_writel(0xffffffff, bank->base +
1473 OMAP4_GPIO_IRQSTATUSCLR0);
1474 __raw_writel(0x00000000, bank->base +
1475 OMAP4_GPIO_DEBOUNCENABLE);
1476 /* Initialize interface clk ungated, module enabled */
1477 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1478 } else if (cpu_is_omap34xx()) {
1479 __raw_writel(0x00000000, bank->base +
1480 OMAP24XX_GPIO_IRQENABLE1);
1481 __raw_writel(0xffffffff, bank->base +
1482 OMAP24XX_GPIO_IRQSTATUS1);
1483 __raw_writel(0x00000000, bank->base +
1484 OMAP24XX_GPIO_DEBOUNCE_EN);
1485
1486 /* Initialize interface clk ungated, module enabled */
1487 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1488 } else if (cpu_is_omap24xx()) {
1489 static const u32 non_wakeup_gpios[] = {
1490 0xe203ffc0, 0x08700040
1491 };
1492 if (id < ARRAY_SIZE(non_wakeup_gpios))
1493 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1494 }
1495 } else if (cpu_class_is_omap1()) {
1496 if (bank_is_mpuio(bank))
5de62b86
TL		 1497 __raw_writew(0xffff, bank->base +
1498 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1499 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1500 __raw_writew(0xffff, bank->base
1501 + OMAP1510_GPIO_INT_MASK);
1502 __raw_writew(0x0000, bank->base
1503 + OMAP1510_GPIO_INT_STATUS);
1504 }
1505 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1506 __raw_writew(0x0000, bank->base
1507 + OMAP1610_GPIO_IRQENABLE1);
1508 __raw_writew(0xffff, bank->base
1509 + OMAP1610_GPIO_IRQSTATUS1);
1510 __raw_writew(0x0014, bank->base
1511 + OMAP1610_GPIO_SYSCONFIG);
1512
1513 /*
1514 * Enable system clock for GPIO module.
1515 * The CAM_CLK_CTRL *is* really the right place.
1516 */
1517 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1518 ULPD_CAM_CLK_CTRL);
1519 }
1520 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1521 __raw_writel(0xffffffff, bank->base
1522 + OMAP7XX_GPIO_INT_MASK);
1523 __raw_writel(0x00000000, bank->base
1524 + OMAP7XX_GPIO_INT_STATUS);
1525 }
1526 }
1527}
1528
d52b31de 1529static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1530{
77640aab 1531 int j;
2fae7fbe
VC		 1532 static int gpio;
1533
2fae7fbe
VC		 1534 bank->mod_usage = 0;
1535 /*
1536 * REVISIT eventually switch from OMAP-specific gpio structs
1537 * over to the generic ones
1538 */
1539 bank->chip.request = omap_gpio_request;
1540 bank->chip.free = omap_gpio_free;
1541 bank->chip.direction_input = gpio_input;
1542 bank->chip.get = gpio_get;
1543 bank->chip.direction_output = gpio_output;
1544 bank->chip.set_debounce = gpio_debounce;
1545 bank->chip.set = gpio_set;
1546 bank->chip.to_irq = gpio_2irq;
1547 if (bank_is_mpuio(bank)) {
1548 bank->chip.label = "mpuio";
1549#ifdef CONFIG_ARCH_OMAP16XX
1550 bank->chip.dev = &omap_mpuio_device.dev;
1551#endif
1552 bank->chip.base = OMAP_MPUIO(0);
1553 } else {
1554 bank->chip.label = "gpio";
1555 bank->chip.base = gpio;
1556 gpio += bank_width;
1557 }
1558 bank->chip.ngpio = bank_width;
1559
1560 gpiochip_add(&bank->chip);
1561
1562 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + bank_width; j++) {
1475b85d 1564 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1565 irq_set_chip_data(j, bank);
2fae7fbe 1566 if (bank_is_mpuio(bank))
6845664a 1567 irq_set_chip(j, &mpuio_irq_chip);
2fae7fbe 1568 else
6845664a
TG		 1569 irq_set_chip(j, &gpio_irq_chip);
1570 irq_set_handler(j, handle_simple_irq);
2fae7fbe
VC		 1571 set_irq_flags(j, IRQF_VALID);
1572 }
6845664a
TG		 1573 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1574 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1575}
1576
77640aab 1577static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1578{
77640aab
VC		 1579 static int gpio_init_done;
1580 struct omap_gpio_platform_data *pdata;
1581 struct resource *res;
1582 int id;
5e1c5ff4
TL		 1583 struct gpio_bank *bank;
1584
77640aab
VC		 1585 if (!pdev->dev.platform_data)
1586 return -EINVAL;
5e1c5ff4 1587
77640aab 1588 pdata = pdev->dev.platform_data;
56a25641 1589
77640aab
VC		 1590 if (!gpio_init_done) {
1591 int ret;
5492fb1a 1592
77640aab
VC		 1593 ret = init_gpio_info(pdev);
1594 if (ret)
1595 return ret;
5492fb1a 1596 }
5492fb1a 1597
77640aab
VC		 1598 id = pdev->id;
1599 bank = &gpio_bank[id];
92105bb7 1600
77640aab
VC		 1601 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1602 if (unlikely(!res)) {
1603 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1604 return -ENODEV;
44169075 1605 }
5e1c5ff4 1606
77640aab
VC		 1607 bank->irq = res->start;
1608 bank->virtual_irq_start = pdata->virtual_irq_start;
1609 bank->method = pdata->bank_type;
1610 bank->dev = &pdev->dev;
1611 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1612 bank->stride = pdata->bank_stride;
77640aab 1613 bank_width = pdata->bank_width;
9f7065da 1614
77640aab 1615 spin_lock_init(&bank->lock);
9f7065da 1616
77640aab
VC		 1617 /* Static mapping, never released */
1618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1619 if (unlikely(!res)) {
1620 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1621 return -ENODEV;
1622 }
89db9482 1623
77640aab
VC		 1624 bank->base = ioremap(res->start, resource_size(res));
1625 if (!bank->base) {
1626 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1627 return -ENOMEM;
5e1c5ff4
TL		 1628 }
1629
77640aab
VC		 1630 pm_runtime_enable(bank->dev);
1631 pm_runtime_get_sync(bank->dev);
1632
1633 omap_gpio_mod_init(bank, id);
1634 omap_gpio_chip_init(bank);
9a748053 1635 omap_gpio_show_rev(bank);
9f7065da 1636
77640aab
VC		 1637 if (!gpio_init_done)
1638 gpio_init_done = 1;
1639
5e1c5ff4
TL		 1640 return 0;
1641}
1642
140455fa 1643#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1644static int omap_gpio_suspend(void)
92105bb7
TL		 1645{
1646 int i;
1647
5492fb1a 1648 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1649 return 0;
1650
1651 for (i = 0; i < gpio_bank_count; i++) {
1652 struct gpio_bank *bank = &gpio_bank[i];
1653 void __iomem *wake_status;
1654 void __iomem *wake_clear;
1655 void __iomem *wake_set;
a6472533 1656 unsigned long flags;
92105bb7
TL		 1657
1658 switch (bank->method) {
e5c56ed3 1659#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1660 case METHOD_GPIO_1610:
1661 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1662 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1663 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1664 break;
e5c56ed3 1665#endif
a8eb7ca0 1666#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1667 case METHOD_GPIO_24XX:
723fdb78 1668 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1669 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1670 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1671 break;
78a1a6d3
SR		 1672#endif
1673#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1674 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1675 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1677 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1678 break;
e5c56ed3 1679#endif
92105bb7
TL		 1680 default:
1681 continue;
1682 }
1683
a6472533 1684 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1685 bank->saved_wakeup = __raw_readl(wake_status);
1686 __raw_writel(0xffffffff, wake_clear);
1687 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1688 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1689 }
1690
1691 return 0;
1692}
1693
3c437ffd 1694static void omap_gpio_resume(void)
92105bb7
TL		 1695{
1696 int i;
1697
723fdb78 1698 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1699 return;
92105bb7
TL		 1700
1701 for (i = 0; i < gpio_bank_count; i++) {
1702 struct gpio_bank *bank = &gpio_bank[i];
1703 void __iomem *wake_clear;
1704 void __iomem *wake_set;
a6472533 1705 unsigned long flags;
92105bb7
TL		 1706
1707 switch (bank->method) {
e5c56ed3 1708#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1709 case METHOD_GPIO_1610:
1710 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1711 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1712 break;
e5c56ed3 1713#endif
a8eb7ca0 1714#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1715 case METHOD_GPIO_24XX:
0d9356cb
TL		 1716 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1717 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1718 break;
78a1a6d3
SR		 1719#endif
1720#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1721 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1722 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1723 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1724 break;
e5c56ed3 1725#endif
92105bb7
TL		 1726 default:
1727 continue;
1728 }
1729
a6472533 1730 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1731 __raw_writel(0xffffffff, wake_clear);
1732 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1733 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1734 }
92105bb7
TL		 1735}
1736
3c437ffd 1737static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1738 .suspend = omap_gpio_suspend,
1739 .resume = omap_gpio_resume,
1740};
1741
3ac4fa99
JY		 1742#endif
1743
140455fa 1744#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1745
1746static int workaround_enabled;
1747
72e06d08 1748void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1749{
1750 int i, c = 0;
a118b5f3 1751 int min = 0;
3ac4fa99 1752
a118b5f3
TK		 1753 if (cpu_is_omap34xx())
1754 min = 1;
43ffcd9a 1755
a118b5f3 1756 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1757 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1758 u32 l1 = 0, l2 = 0;
0aed0435 1759 int j;
3ac4fa99 1760
0aed0435 1761 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1762 clk_disable(bank->dbck);
1763
72e06d08 1764 if (!off_mode)
43ffcd9a
KH		 1765 continue;
1766
1767 /* If going to OFF, remove triggering for all
1768 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1769 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1770 if (!(bank->enabled_non_wakeup_gpios))
1771 continue;
3f1686a9
TL		 1772
1773 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1774 bank->saved_datain = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_DATAIN);
1776 l1 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_FALLINGDETECT);
1778 l2 = __raw_readl(bank->base +
1779 OMAP24XX_GPIO_RISINGDETECT);
1780 }
1781
1782 if (cpu_is_omap44xx()) {
1783 bank->saved_datain = __raw_readl(bank->base +
1784 OMAP4_GPIO_DATAIN);
1785 l1 = __raw_readl(bank->base +
1786 OMAP4_GPIO_FALLINGDETECT);
1787 l2 = __raw_readl(bank->base +
1788 OMAP4_GPIO_RISINGDETECT);
1789 }
1790
3ac4fa99
JY		 1791 bank->saved_fallingdetect = l1;
1792 bank->saved_risingdetect = l2;
1793 l1 &= ~bank->enabled_non_wakeup_gpios;
1794 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1795
1796 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1797 __raw_writel(l1, bank->base +
1798 OMAP24XX_GPIO_FALLINGDETECT);
1799 __raw_writel(l2, bank->base +
1800 OMAP24XX_GPIO_RISINGDETECT);
1801 }
1802
1803 if (cpu_is_omap44xx()) {
1804 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1805 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1806 }
1807
3ac4fa99
JY		 1808 c++;
1809 }
1810 if (!c) {
1811 workaround_enabled = 0;
1812 return;
1813 }
1814 workaround_enabled = 1;
1815}
1816
43ffcd9a 1817void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1818{
1819 int i;
a118b5f3 1820 int min = 0;
3ac4fa99 1821
a118b5f3
TK		 1822 if (cpu_is_omap34xx())
1823 min = 1;
1824 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1825 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1826 u32 l = 0, gen, gen0, gen1;
0aed0435 1827 int j;
3ac4fa99 1828
0aed0435 1829 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1830 clk_enable(bank->dbck);
1831
43ffcd9a
KH		 1832 if (!workaround_enabled)
1833 continue;
1834
3ac4fa99
JY		 1835 if (!(bank->enabled_non_wakeup_gpios))
1836 continue;
3f1686a9
TL		 1837
1838 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1839 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1840 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1841 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1842 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1843 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1844 }
1845
1846 if (cpu_is_omap44xx()) {
1847 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1848 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1849 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1850 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1851 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1852 }
1853
3ac4fa99
JY		 1854 /* Check if any of the non-wakeup interrupt GPIOs have changed
1855 * state. If so, generate an IRQ by software. This is
1856 * horribly racy, but it's the best we can do to work around
1857 * this silicon bug. */
3ac4fa99 1858 l ^= bank->saved_datain;
a118b5f3 1859 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1860
1861 /*
1862 * No need to generate IRQs for the rising edge for gpio IRQs
1863 * configured with falling edge only; and vice versa.
1864 */
1865 gen0 = l & bank->saved_fallingdetect;
1866 gen0 &= bank->saved_datain;
1867
1868 gen1 = l & bank->saved_risingdetect;
1869 gen1 &= ~(bank->saved_datain);
1870
1871 /* FIXME: Consider GPIO IRQs with level detections properly! */
1872 gen = l & (~(bank->saved_fallingdetect) &
1873 ~(bank->saved_risingdetect));
1874 /* Consider all GPIO IRQs needed to be updated */
1875 gen |= gen0 | gen1;
1876
1877 if (gen) {
3ac4fa99 1878 u32 old0, old1;
3f1686a9 1879
f00d6497 1880 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1881 old0 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT0);
1883 old1 = __raw_readl(bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1885 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1886 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1887 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1888 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1889 __raw_writel(old0, bank->base +
3f1686a9 1890 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1891 __raw_writel(old1, bank->base +
3f1686a9
TL		 1892 OMAP24XX_GPIO_LEVELDETECT1);
1893 }
1894
1895 if (cpu_is_omap44xx()) {
1896 old0 = __raw_readl(bank->base +
78a1a6d3 1897 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1898 old1 = __raw_readl(bank->base +
78a1a6d3 1899 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1900 __raw_writel(old0 | l, bank->base +
78a1a6d3 1901 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1902 __raw_writel(old1 | l, bank->base +
78a1a6d3 1903 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1904 __raw_writel(old0, bank->base +
78a1a6d3 1905 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1906 __raw_writel(old1, bank->base +
78a1a6d3 1907 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1908 }
3ac4fa99
JY		 1909 }
1910 }
1911
1912}
1913
92105bb7
TL		 1914#endif
1915
a8eb7ca0 1916#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1917/* save the registers of bank 2-6 */
1918void omap_gpio_save_context(void)
1919{
1920 int i;
1921
1922 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1923 for (i = 1; i < gpio_bank_count; i++) {
1924 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1925 gpio_context[i].irqenable1 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1927 gpio_context[i].irqenable2 =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1929 gpio_context[i].wake_en =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1931 gpio_context[i].ctrl =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1933 gpio_context[i].oe =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1935 gpio_context[i].leveldetect0 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1937 gpio_context[i].leveldetect1 =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1939 gpio_context[i].risingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1941 gpio_context[i].fallingdetect =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1943 gpio_context[i].dataout =
1944 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1945 }
1946}
1947
1948/* restore the required registers of bank 2-6 */
1949void omap_gpio_restore_context(void)
1950{
1951 int i;
1952
1953 for (i = 1; i < gpio_bank_count; i++) {
1954 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1955 __raw_writel(gpio_context[i].irqenable1,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1957 __raw_writel(gpio_context[i].irqenable2,
1958 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1959 __raw_writel(gpio_context[i].wake_en,
1960 bank->base + OMAP24XX_GPIO_WAKE_EN);
1961 __raw_writel(gpio_context[i].ctrl,
1962 bank->base + OMAP24XX_GPIO_CTRL);
1963 __raw_writel(gpio_context[i].oe,
1964 bank->base + OMAP24XX_GPIO_OE);
1965 __raw_writel(gpio_context[i].leveldetect0,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1967 __raw_writel(gpio_context[i].leveldetect1,
1968 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1969 __raw_writel(gpio_context[i].risingdetect,
1970 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1971 __raw_writel(gpio_context[i].fallingdetect,
1972 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1973 __raw_writel(gpio_context[i].dataout,
1974 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1975 }
1976}
1977#endif
1978
77640aab
VC		 1979static struct platform_driver omap_gpio_driver = {
1980 .probe = omap_gpio_probe,
1981 .driver = {
1982 .name = "omap_gpio",
1983 },
1984};
1985
5e1c5ff4 1986/*
77640aab
VC		 1987 * gpio driver register needs to be done before
1988 * machine_init functions access gpio APIs.
1989 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1990 */
77640aab 1991static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1992{
77640aab 1993 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1994}
77640aab 1995postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1996
92105bb7
TL		 1997static int __init omap_gpio_sysinit(void)
1998{
11a78b79
DB		 1999 mpuio_init();
2000
140455fa 2001#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 2002 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2003 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 2004#endif
2005
3c437ffd 2006 return 0;
92105bb7
TL		 2007}
2008
92105bb7 2009arch_initcall(omap_gpio_sysinit);
Linux 6.x block layer and io_uring tree(s)