Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 | 31 | #define OFF_MODE 1 |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
30cefeac | 54 | int irq; |
3ac4fa99 JY |
55 | u32 non_wakeup_gpios; |
56 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 57 | struct gpio_regs context; |
3ac4fa99 | 58 | u32 saved_datain; |
b144ff6f | 59 | u32 level_mask; |
4318f36b | 60 | u32 toggle_mask; |
4dbada2b | 61 | raw_spinlock_t lock; |
450fa54c | 62 | raw_spinlock_t wa_lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
fa365e4d | 66 | u32 irq_usage; |
8865b9b6 | 67 | u32 dbck_enable_mask; |
72f83af9 | 68 | bool dbck_enabled; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
352a2d5b | 72 | bool context_valid; |
5de62b86 | 73 | int stride; |
d5f46247 | 74 | u32 width; |
60a3437d | 75 | int context_loss_count; |
2dc983c5 TKD |
76 | int power_mode; |
77 | bool workaround_enabled; | |
fa87931a | 78 | |
04ebcbd8 | 79 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 80 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
81 | |
82 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
83 | }; |
84 | ||
c8eef65a | 85 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 86 | |
fa365e4d | 87 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 88 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 89 | |
3d009c8c TL |
90 | static void omap_gpio_unmask_irq(struct irq_data *d); |
91 | ||
a0e827c6 | 92 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 93 | { |
fb655f57 | 94 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 95 | return gpiochip_get_data(chip); |
25db711d BC |
96 | } |
97 | ||
a0e827c6 JMC |
98 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
99 | int is_input) | |
5e1c5ff4 | 100 | { |
92105bb7 | 101 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
102 | u32 l; |
103 | ||
fa87931a | 104 | reg += bank->regs->direction; |
661553b9 | 105 | l = readl_relaxed(reg); |
5e1c5ff4 | 106 | if (is_input) |
b1e9fec2 | 107 | l |= BIT(gpio); |
5e1c5ff4 | 108 | else |
b1e9fec2 | 109 | l &= ~(BIT(gpio)); |
661553b9 | 110 | writel_relaxed(l, reg); |
41d87cbd | 111 | bank->context.oe = l; |
5e1c5ff4 TL |
112 | } |
113 | ||
fa87931a KH |
114 | |
115 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 116 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 117 | int enable) |
5e1c5ff4 | 118 | { |
92105bb7 | 119 | void __iomem *reg = bank->base; |
04ebcbd8 | 120 | u32 l = BIT(offset); |
5e1c5ff4 | 121 | |
2c836f7e | 122 | if (enable) { |
fa87931a | 123 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
124 | bank->context.dataout |= l; |
125 | } else { | |
fa87931a | 126 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
127 | bank->context.dataout &= ~l; |
128 | } | |
5e1c5ff4 | 129 | |
661553b9 | 130 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
131 | } |
132 | ||
fa87931a | 133 | /* set data out value using mask register */ |
04ebcbd8 | 134 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 135 | int enable) |
5e1c5ff4 | 136 | { |
fa87931a | 137 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 138 | u32 gpio_bit = BIT(offset); |
fa87931a | 139 | u32 l; |
5e1c5ff4 | 140 | |
661553b9 | 141 | l = readl_relaxed(reg); |
fa87931a KH |
142 | if (enable) |
143 | l |= gpio_bit; | |
144 | else | |
145 | l &= ~gpio_bit; | |
661553b9 | 146 | writel_relaxed(l, reg); |
41d87cbd | 147 | bank->context.dataout = l; |
5e1c5ff4 TL |
148 | } |
149 | ||
a0e827c6 | 150 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 151 | { |
fa87931a | 152 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 153 | |
b1e9fec2 | 154 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 155 | } |
b37c45b8 | 156 | |
a0e827c6 | 157 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 158 | { |
fa87931a | 159 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 160 | |
b1e9fec2 | 161 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
162 | } |
163 | ||
a0e827c6 | 164 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 165 | { |
661553b9 | 166 | int l = readl_relaxed(base + reg); |
ece9528e | 167 | |
862ff640 | 168 | if (set) |
ece9528e KH |
169 | l |= mask; |
170 | else | |
171 | l &= ~mask; | |
172 | ||
661553b9 | 173 | writel_relaxed(l, base + reg); |
ece9528e | 174 | } |
92105bb7 | 175 | |
a0e827c6 | 176 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
177 | { |
178 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 179 | clk_enable(bank->dbck); |
72f83af9 | 180 | bank->dbck_enabled = true; |
9e303f22 | 181 | |
661553b9 | 182 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 183 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
184 | } |
185 | } | |
186 | ||
a0e827c6 | 187 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
188 | { |
189 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
190 | /* |
191 | * Disable debounce before cutting it's clock. If debounce is | |
192 | * enabled but the clock is not, GPIO module seems to be unable | |
193 | * to detect events and generate interrupts at least on OMAP3. | |
194 | */ | |
661553b9 | 195 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 196 | |
5d9452e7 | 197 | clk_disable(bank->dbck); |
72f83af9 TKD |
198 | bank->dbck_enabled = false; |
199 | } | |
200 | } | |
201 | ||
168ef3d9 | 202 | /** |
a0e827c6 | 203 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 204 | * @bank: the gpio bank we're acting upon |
4a58d229 | 205 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
206 | * @debounce: debounce time to use |
207 | * | |
e85ec6c3 GS |
208 | * OMAP's debounce time is in 31us steps |
209 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
210 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
211 | * |
212 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 213 | */ |
83977443 DR |
214 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
215 | unsigned debounce) | |
168ef3d9 | 216 | { |
9942da0e | 217 | void __iomem *reg; |
168ef3d9 FB |
218 | u32 val; |
219 | u32 l; | |
e85ec6c3 | 220 | bool enable = !!debounce; |
168ef3d9 | 221 | |
77640aab | 222 | if (!bank->dbck_flag) |
83977443 | 223 | return -ENOTSUPP; |
77640aab | 224 | |
e85ec6c3 GS |
225 | if (enable) { |
226 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
227 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
228 | return -EINVAL; | |
e85ec6c3 | 229 | } |
168ef3d9 | 230 | |
4a58d229 | 231 | l = BIT(offset); |
168ef3d9 | 232 | |
5d9452e7 | 233 | clk_enable(bank->dbck); |
9942da0e | 234 | reg = bank->base + bank->regs->debounce; |
661553b9 | 235 | writel_relaxed(debounce, reg); |
168ef3d9 | 236 | |
9942da0e | 237 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 238 | val = readl_relaxed(reg); |
168ef3d9 | 239 | |
e85ec6c3 | 240 | if (enable) |
168ef3d9 | 241 | val |= l; |
6fd9c421 | 242 | else |
168ef3d9 | 243 | val &= ~l; |
f7ec0b0b | 244 | bank->dbck_enable_mask = val; |
168ef3d9 | 245 | |
661553b9 | 246 | writel_relaxed(val, reg); |
5d9452e7 | 247 | clk_disable(bank->dbck); |
6fd9c421 TKD |
248 | /* |
249 | * Enable debounce clock per module. | |
250 | * This call is mandatory because in omap_gpio_request() when | |
251 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
252 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
253 | * used within _gpio_dbck_enable() is still not initialized at | |
254 | * that point. Therefore we have to enable dbck here. | |
255 | */ | |
a0e827c6 | 256 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
257 | if (bank->dbck_enable_mask) { |
258 | bank->context.debounce = debounce; | |
259 | bank->context.debounce_en = val; | |
260 | } | |
83977443 DR |
261 | |
262 | return 0; | |
168ef3d9 FB |
263 | } |
264 | ||
c9c55d92 | 265 | /** |
a0e827c6 | 266 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 267 | * @bank: the gpio bank we're acting upon |
4a58d229 | 268 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
269 | * |
270 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
271 | * this is the only gpio in this bank using debounce, then clear the debounce | |
272 | * time too. The debounce clock will also be disabled when calling this function | |
273 | * if this is the only gpio in the bank using debounce. | |
274 | */ | |
4a58d229 | 275 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 276 | { |
4a58d229 | 277 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
278 | |
279 | if (!bank->dbck_flag) | |
280 | return; | |
281 | ||
282 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
283 | return; | |
284 | ||
285 | bank->dbck_enable_mask &= ~gpio_bit; | |
286 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 287 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
288 | bank->base + bank->regs->debounce_en); |
289 | ||
290 | if (!bank->dbck_enable_mask) { | |
291 | bank->context.debounce = 0; | |
661553b9 | 292 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 293 | bank->regs->debounce); |
5d9452e7 | 294 | clk_disable(bank->dbck); |
c9c55d92 JH |
295 | bank->dbck_enabled = false; |
296 | } | |
297 | } | |
298 | ||
a0e827c6 | 299 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 300 | unsigned trigger) |
5e1c5ff4 | 301 | { |
3ac4fa99 | 302 | void __iomem *base = bank->base; |
b1e9fec2 | 303 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 304 | |
a0e827c6 JMC |
305 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
306 | trigger & IRQ_TYPE_LEVEL_LOW); | |
307 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
308 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
309 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
310 | trigger & IRQ_TYPE_EDGE_RISING); | |
311 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
312 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 313 | |
41d87cbd | 314 | bank->context.leveldetect0 = |
661553b9 | 315 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 316 | bank->context.leveldetect1 = |
661553b9 | 317 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 318 | bank->context.risingdetect = |
661553b9 | 319 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 320 | bank->context.fallingdetect = |
661553b9 | 321 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
322 | |
323 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 324 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 325 | bank->context.wake_en = |
661553b9 | 326 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 327 | } |
5e571f38 | 328 | |
55b220ca | 329 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
330 | if (!bank->regs->irqctrl) { |
331 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
332 | if (bank->non_wakeup_gpios) { | |
333 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
334 | goto exit; | |
335 | } | |
336 | ||
699117a6 CW |
337 | /* |
338 | * Log the edge gpio and manually trigger the IRQ | |
339 | * after resume if the input level changes | |
340 | * to avoid irq lost during PER RET/OFF mode | |
341 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
342 | */ | |
343 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
344 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
345 | else | |
346 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
347 | } | |
5eb3bb9c | 348 | |
5e571f38 | 349 | exit: |
9ea14d8c | 350 | bank->level_mask = |
661553b9 VK |
351 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
352 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
353 | } |
354 | ||
9198bcd3 | 355 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
356 | /* |
357 | * This only applies to chips that can't do both rising and falling edge | |
358 | * detection at once. For all other chips, this function is a noop. | |
359 | */ | |
a0e827c6 | 360 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
361 | { |
362 | void __iomem *reg = bank->base; | |
363 | u32 l = 0; | |
364 | ||
5e571f38 | 365 | if (!bank->regs->irqctrl) |
4318f36b | 366 | return; |
5e571f38 TKD |
367 | |
368 | reg += bank->regs->irqctrl; | |
4318f36b | 369 | |
661553b9 | 370 | l = readl_relaxed(reg); |
4318f36b | 371 | if ((l >> gpio) & 1) |
b1e9fec2 | 372 | l &= ~(BIT(gpio)); |
4318f36b | 373 | else |
b1e9fec2 | 374 | l |= BIT(gpio); |
4318f36b | 375 | |
661553b9 | 376 | writel_relaxed(l, reg); |
4318f36b | 377 | } |
5e571f38 | 378 | #else |
a0e827c6 | 379 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 380 | #endif |
4318f36b | 381 | |
a0e827c6 JMC |
382 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
383 | unsigned trigger) | |
92105bb7 TL |
384 | { |
385 | void __iomem *reg = bank->base; | |
5e571f38 | 386 | void __iomem *base = bank->base; |
92105bb7 | 387 | u32 l = 0; |
5e1c5ff4 | 388 | |
5e571f38 | 389 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 390 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
391 | } else if (bank->regs->irqctrl) { |
392 | reg += bank->regs->irqctrl; | |
393 | ||
661553b9 | 394 | l = readl_relaxed(reg); |
29501577 | 395 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 396 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 397 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 398 | l |= BIT(gpio); |
6cab4860 | 399 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 400 | l &= ~(BIT(gpio)); |
92105bb7 | 401 | else |
5e571f38 TKD |
402 | return -EINVAL; |
403 | ||
661553b9 | 404 | writel_relaxed(l, reg); |
5e571f38 | 405 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 406 | if (gpio & 0x08) |
5e571f38 | 407 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 408 | else |
5e571f38 TKD |
409 | reg += bank->regs->edgectrl1; |
410 | ||
5e1c5ff4 | 411 | gpio &= 0x07; |
661553b9 | 412 | l = readl_relaxed(reg); |
5e1c5ff4 | 413 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 414 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 415 | l |= 2 << (gpio << 1); |
6cab4860 | 416 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 417 | l |= BIT(gpio << 1); |
5e571f38 TKD |
418 | |
419 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 420 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 421 | bank->context.wake_en = |
661553b9 VK |
422 | readl_relaxed(bank->base + bank->regs->wkup_en); |
423 | writel_relaxed(l, reg); | |
5e1c5ff4 | 424 | } |
92105bb7 | 425 | return 0; |
5e1c5ff4 TL |
426 | } |
427 | ||
a0e827c6 | 428 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
429 | { |
430 | if (bank->regs->pinctrl) { | |
431 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
432 | ||
433 | /* Claim the pin for MPU */ | |
b1e9fec2 | 434 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
435 | } |
436 | ||
437 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
438 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
439 | u32 ctrl; | |
440 | ||
661553b9 | 441 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
442 | /* Module is enabled, clocks are not gated */ |
443 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 444 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
445 | bank->context.ctrl = ctrl; |
446 | } | |
447 | } | |
448 | ||
a0e827c6 | 449 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
450 | { |
451 | void __iomem *base = bank->base; | |
452 | ||
453 | if (bank->regs->wkup_en && | |
454 | !LINE_USED(bank->mod_usage, offset) && | |
455 | !LINE_USED(bank->irq_usage, offset)) { | |
456 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 457 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 458 | bank->context.wake_en = |
661553b9 | 459 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
460 | } |
461 | ||
462 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
463 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
464 | u32 ctrl; | |
465 | ||
661553b9 | 466 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
467 | /* Module is disabled, clocks are gated */ |
468 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 469 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
470 | bank->context.ctrl = ctrl; |
471 | } | |
472 | } | |
473 | ||
b2b20045 | 474 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
475 | { |
476 | void __iomem *reg = bank->base + bank->regs->direction; | |
477 | ||
b2b20045 | 478 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
479 | } |
480 | ||
37e14ecf | 481 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
482 | { |
483 | if (!LINE_USED(bank->mod_usage, offset)) { | |
484 | omap_enable_gpio_module(bank, offset); | |
485 | omap_set_gpio_direction(bank, offset, 1); | |
486 | } | |
37e14ecf | 487 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
488 | } |
489 | ||
a0e827c6 | 490 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 491 | { |
a0e827c6 | 492 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 493 | int retval; |
a6472533 | 494 | unsigned long flags; |
ea5fbe8d | 495 | unsigned offset = d->hwirq; |
92105bb7 | 496 | |
e5c56ed3 | 497 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 498 | return -EINVAL; |
e5c56ed3 | 499 | |
9ea14d8c TKD |
500 | if (!bank->regs->leveldetect0 && |
501 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
502 | return -EINVAL; |
503 | ||
4dbada2b | 504 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 505 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 506 | if (retval) { |
627c89b4 | 507 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 508 | goto error; |
977bd8a9 | 509 | } |
37e14ecf | 510 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 511 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 512 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
513 | retval = -EINVAL; |
514 | goto error; | |
fac7fa16 | 515 | } |
4dbada2b | 516 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
517 | |
518 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 519 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 520 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
521 | /* |
522 | * Edge IRQs are already cleared/acked in irq_handler and | |
523 | * not need to be masked, as result handle_edge_irq() | |
524 | * logic is excessed here and may cause lose of interrupts. | |
525 | * So just use handle_simple_irq. | |
526 | */ | |
527 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 528 | |
1562e461 GS |
529 | return 0; |
530 | ||
531 | error: | |
92105bb7 | 532 | return retval; |
5e1c5ff4 TL |
533 | } |
534 | ||
a0e827c6 | 535 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 536 | { |
92105bb7 | 537 | void __iomem *reg = bank->base; |
5e1c5ff4 | 538 | |
eef4bec7 | 539 | reg += bank->regs->irqstatus; |
661553b9 | 540 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
541 | |
542 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
543 | if (bank->regs->irqstatus2) { |
544 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 545 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 546 | } |
bedfd154 RQ |
547 | |
548 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 549 | readl_relaxed(reg); |
5e1c5ff4 TL |
550 | } |
551 | ||
9943f261 GS |
552 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
553 | unsigned offset) | |
5e1c5ff4 | 554 | { |
9943f261 | 555 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
556 | } |
557 | ||
a0e827c6 | 558 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
559 | { |
560 | void __iomem *reg = bank->base; | |
99c47707 | 561 | u32 l; |
b1e9fec2 | 562 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 563 | |
28f3b5a0 | 564 | reg += bank->regs->irqenable; |
661553b9 | 565 | l = readl_relaxed(reg); |
28f3b5a0 | 566 | if (bank->regs->irqenable_inv) |
99c47707 ID |
567 | l = ~l; |
568 | l &= mask; | |
569 | return l; | |
ea6dedd7 ID |
570 | } |
571 | ||
a0e827c6 | 572 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 573 | { |
92105bb7 | 574 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
575 | u32 l; |
576 | ||
28f3b5a0 KH |
577 | if (bank->regs->set_irqenable) { |
578 | reg += bank->regs->set_irqenable; | |
579 | l = gpio_mask; | |
2a900eb7 | 580 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
581 | } else { |
582 | reg += bank->regs->irqenable; | |
661553b9 | 583 | l = readl_relaxed(reg); |
28f3b5a0 KH |
584 | if (bank->regs->irqenable_inv) |
585 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
586 | else |
587 | l |= gpio_mask; | |
2a900eb7 | 588 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
589 | } |
590 | ||
661553b9 | 591 | writel_relaxed(l, reg); |
28f3b5a0 KH |
592 | } |
593 | ||
a0e827c6 | 594 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
595 | { |
596 | void __iomem *reg = bank->base; | |
597 | u32 l; | |
598 | ||
599 | if (bank->regs->clr_irqenable) { | |
600 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 601 | l = gpio_mask; |
2a900eb7 | 602 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
603 | } else { |
604 | reg += bank->regs->irqenable; | |
661553b9 | 605 | l = readl_relaxed(reg); |
28f3b5a0 | 606 | if (bank->regs->irqenable_inv) |
56739a69 | 607 | l |= gpio_mask; |
92105bb7 | 608 | else |
28f3b5a0 | 609 | l &= ~gpio_mask; |
2a900eb7 | 610 | bank->context.irqenable1 = l; |
5e1c5ff4 | 611 | } |
28f3b5a0 | 612 | |
661553b9 | 613 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
614 | } |
615 | ||
9943f261 GS |
616 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
617 | unsigned offset, int enable) | |
5e1c5ff4 | 618 | { |
8276536c | 619 | if (enable) |
9943f261 | 620 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 621 | else |
9943f261 | 622 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
623 | } |
624 | ||
92105bb7 | 625 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 626 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 627 | { |
a0e827c6 | 628 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 629 | |
0c0451e7 | 630 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
631 | } |
632 | ||
3ff164e1 | 633 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 634 | { |
d99f7aec | 635 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 636 | unsigned long flags; |
52e31344 | 637 | |
55b93c32 TKD |
638 | /* |
639 | * If this is the first gpio_request for the bank, | |
640 | * enable the bank module. | |
641 | */ | |
fa365e4d | 642 | if (!BANK_USED(bank)) |
7b1e5dc8 | 643 | pm_runtime_get_sync(chip->parent); |
92105bb7 | 644 | |
4dbada2b | 645 | raw_spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 646 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 647 | bank->mod_usage |= BIT(offset); |
4dbada2b | 648 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
649 | |
650 | return 0; | |
651 | } | |
652 | ||
3ff164e1 | 653 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 654 | { |
d99f7aec | 655 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 656 | unsigned long flags; |
5e1c5ff4 | 657 | |
4dbada2b | 658 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 659 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
660 | if (!LINE_USED(bank->irq_usage, offset)) { |
661 | omap_set_gpio_direction(bank, offset, 1); | |
662 | omap_clear_gpio_debounce(bank, offset); | |
663 | } | |
a0e827c6 | 664 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 665 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
666 | |
667 | /* | |
668 | * If this is the last gpio to be freed in the bank, | |
669 | * disable the bank module. | |
670 | */ | |
fa365e4d | 671 | if (!BANK_USED(bank)) |
7b1e5dc8 | 672 | pm_runtime_put(chip->parent); |
5e1c5ff4 TL |
673 | } |
674 | ||
675 | /* | |
676 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
677 | * avoid missing GPIO interrupts for other lines in the bank. | |
678 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
679 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
680 | * If we wait to unmask individual GPIO lines in the bank after the | |
681 | * line's interrupt handler has been run, we may miss some nested | |
682 | * interrupts. | |
683 | */ | |
450fa54c | 684 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 685 | { |
92105bb7 | 686 | void __iomem *isr_reg = NULL; |
80ac93c2 | 687 | u32 enabled, isr, level_mask; |
3513cdec | 688 | unsigned int bit; |
450fa54c GS |
689 | struct gpio_bank *bank = gpiobank; |
690 | unsigned long wa_lock_flags; | |
235f1eb1 | 691 | unsigned long lock_flags; |
5e1c5ff4 | 692 | |
eef4bec7 | 693 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
694 | if (WARN_ON(!isr_reg)) |
695 | goto exit; | |
696 | ||
7b1e5dc8 | 697 | pm_runtime_get_sync(bank->chip.parent); |
450fa54c | 698 | |
e83507b7 | 699 | while (1) { |
235f1eb1 GS |
700 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
701 | ||
a0e827c6 | 702 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 703 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 704 | |
9ea14d8c | 705 | if (bank->level_mask) |
b144ff6f | 706 | level_mask = bank->level_mask & enabled; |
80ac93c2 GS |
707 | else |
708 | level_mask = 0; | |
6e60e79a TL |
709 | |
710 | /* clear edge sensitive interrupts before handler(s) are | |
711 | called so that we don't miss any interrupt occurred while | |
712 | executing them */ | |
80ac93c2 GS |
713 | if (isr & ~level_mask) |
714 | omap_clear_gpio_irqbank(bank, isr & ~level_mask); | |
6e60e79a | 715 | |
235f1eb1 GS |
716 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
717 | ||
92105bb7 TL |
718 | if (!isr) |
719 | break; | |
720 | ||
3513cdec JH |
721 | while (isr) { |
722 | bit = __ffs(isr); | |
b1e9fec2 | 723 | isr &= ~(BIT(bit)); |
25db711d | 724 | |
235f1eb1 | 725 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
726 | /* |
727 | * Some chips can't respond to both rising and falling | |
728 | * at the same time. If this irq was requested with | |
729 | * both flags, we need to flip the ICR data for the IRQ | |
730 | * to respond to the IRQ for the opposite direction. | |
731 | * This will be indicated in the bank toggle_mask. | |
732 | */ | |
b1e9fec2 | 733 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 734 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 735 | |
235f1eb1 GS |
736 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
737 | ||
450fa54c GS |
738 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
739 | ||
f0fbe7bc | 740 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 741 | bit)); |
450fa54c GS |
742 | |
743 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
744 | wa_lock_flags); | |
92105bb7 | 745 | } |
1a8bfa1e | 746 | } |
b1cc4c55 | 747 | exit: |
7b1e5dc8 | 748 | pm_runtime_put(bank->chip.parent); |
450fa54c | 749 | return IRQ_HANDLED; |
5e1c5ff4 TL |
750 | } |
751 | ||
3d009c8c TL |
752 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
753 | { | |
754 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 755 | unsigned long flags; |
37e14ecf | 756 | unsigned offset = d->hwirq; |
3d009c8c | 757 | |
4dbada2b | 758 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
759 | |
760 | if (!LINE_USED(bank->mod_usage, offset)) | |
761 | omap_set_gpio_direction(bank, offset, 1); | |
762 | else if (!omap_gpio_is_input(bank, offset)) | |
763 | goto err; | |
764 | omap_enable_gpio_module(bank, offset); | |
765 | bank->irq_usage |= BIT(offset); | |
766 | ||
4dbada2b | 767 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
768 | omap_gpio_unmask_irq(d); |
769 | ||
770 | return 0; | |
121dcb76 | 771 | err: |
4dbada2b | 772 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 773 | return -EINVAL; |
3d009c8c TL |
774 | } |
775 | ||
a0e827c6 | 776 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 777 | { |
a0e827c6 | 778 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 779 | unsigned long flags; |
9943f261 | 780 | unsigned offset = d->hwirq; |
4196dd6b | 781 | |
4dbada2b | 782 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 783 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
784 | omap_set_gpio_irqenable(bank, offset, 0); |
785 | omap_clear_gpio_irqstatus(bank, offset); | |
786 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
787 | if (!LINE_USED(bank->mod_usage, offset)) | |
788 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 789 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 790 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
791 | } |
792 | ||
793 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
794 | { | |
795 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
796 | ||
797 | if (!BANK_USED(bank)) | |
7b1e5dc8 | 798 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
799 | } |
800 | ||
801 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
802 | { | |
803 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 JMC |
804 | |
805 | /* | |
806 | * If this is the last IRQ to be freed in the bank, | |
807 | * disable the bank module. | |
808 | */ | |
809 | if (!BANK_USED(bank)) | |
7b1e5dc8 | 810 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
811 | } |
812 | ||
a0e827c6 | 813 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 814 | { |
a0e827c6 | 815 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 816 | unsigned offset = d->hwirq; |
5e1c5ff4 | 817 | |
9943f261 | 818 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
819 | } |
820 | ||
a0e827c6 | 821 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 822 | { |
a0e827c6 | 823 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 824 | unsigned offset = d->hwirq; |
85ec7b97 | 825 | unsigned long flags; |
5e1c5ff4 | 826 | |
4dbada2b | 827 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
828 | omap_set_gpio_irqenable(bank, offset, 0); |
829 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
4dbada2b | 830 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
831 | } |
832 | ||
a0e827c6 | 833 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 834 | { |
a0e827c6 | 835 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 836 | unsigned offset = d->hwirq; |
8c04a176 | 837 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 838 | unsigned long flags; |
55b6019a | 839 | |
4dbada2b | 840 | raw_spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 841 | if (trigger) |
9943f261 | 842 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f KH |
843 | |
844 | /* For level-triggered GPIOs, the clearing must be done after | |
845 | * the HW source is cleared, thus after the handler has run */ | |
9943f261 GS |
846 | if (bank->level_mask & BIT(offset)) { |
847 | omap_set_gpio_irqenable(bank, offset, 0); | |
848 | omap_clear_gpio_irqstatus(bank, offset); | |
b144ff6f | 849 | } |
5e1c5ff4 | 850 | |
9943f261 | 851 | omap_set_gpio_irqenable(bank, offset, 1); |
4dbada2b | 852 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
853 | } |
854 | ||
e5c56ed3 DB |
855 | /*---------------------------------------------------------------------*/ |
856 | ||
79ee031f | 857 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 858 | { |
79ee031f | 859 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 860 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
861 | void __iomem *mask_reg = bank->base + |
862 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 863 | unsigned long flags; |
11a78b79 | 864 | |
4dbada2b | 865 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 866 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 867 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
79ee031f | 872 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 873 | { |
79ee031f | 874 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 875 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
876 | void __iomem *mask_reg = bank->base + |
877 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 878 | unsigned long flags; |
11a78b79 | 879 | |
4dbada2b | 880 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 881 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 882 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
883 | |
884 | return 0; | |
885 | } | |
886 | ||
47145210 | 887 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
888 | .suspend_noirq = omap_mpuio_suspend_noirq, |
889 | .resume_noirq = omap_mpuio_resume_noirq, | |
890 | }; | |
891 | ||
3c437ffd | 892 | /* use platform_driver for this. */ |
11a78b79 | 893 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
894 | .driver = { |
895 | .name = "mpuio", | |
79ee031f | 896 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
897 | }, |
898 | }; | |
899 | ||
900 | static struct platform_device omap_mpuio_device = { | |
901 | .name = "mpuio", | |
902 | .id = -1, | |
903 | .dev = { | |
904 | .driver = &omap_mpuio_driver.driver, | |
905 | } | |
906 | /* could list the /proc/iomem resources */ | |
907 | }; | |
908 | ||
a0e827c6 | 909 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 910 | { |
77640aab | 911 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 912 | |
11a78b79 DB |
913 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
914 | (void) platform_device_register(&omap_mpuio_device); | |
915 | } | |
916 | ||
e5c56ed3 | 917 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 918 | |
a0e827c6 | 919 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
920 | { |
921 | struct gpio_bank *bank; | |
922 | unsigned long flags; | |
923 | void __iomem *reg; | |
924 | int dir; | |
925 | ||
d99f7aec | 926 | bank = gpiochip_get_data(chip); |
9370084e | 927 | reg = bank->base + bank->regs->direction; |
4dbada2b | 928 | raw_spin_lock_irqsave(&bank->lock, flags); |
9370084e | 929 | dir = !!(readl_relaxed(reg) & BIT(offset)); |
4dbada2b | 930 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
9370084e YY |
931 | return dir; |
932 | } | |
933 | ||
a0e827c6 | 934 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
935 | { |
936 | struct gpio_bank *bank; | |
937 | unsigned long flags; | |
938 | ||
d99f7aec | 939 | bank = gpiochip_get_data(chip); |
4dbada2b | 940 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 941 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 942 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
943 | return 0; |
944 | } | |
945 | ||
a0e827c6 | 946 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 947 | { |
b37c45b8 | 948 | struct gpio_bank *bank; |
b37c45b8 | 949 | |
d99f7aec | 950 | bank = gpiochip_get_data(chip); |
b37c45b8 | 951 | |
b2b20045 | 952 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 953 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 954 | else |
a0e827c6 | 955 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
956 | } |
957 | ||
a0e827c6 | 958 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
959 | { |
960 | struct gpio_bank *bank; | |
961 | unsigned long flags; | |
962 | ||
d99f7aec | 963 | bank = gpiochip_get_data(chip); |
4dbada2b | 964 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 965 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 966 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 967 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 968 | return 0; |
52e31344 DB |
969 | } |
970 | ||
a0e827c6 JMC |
971 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
972 | unsigned debounce) | |
168ef3d9 FB |
973 | { |
974 | struct gpio_bank *bank; | |
975 | unsigned long flags; | |
83977443 | 976 | int ret; |
168ef3d9 | 977 | |
d99f7aec | 978 | bank = gpiochip_get_data(chip); |
77640aab | 979 | |
4dbada2b | 980 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 981 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 982 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 983 | |
83977443 DR |
984 | if (ret) |
985 | dev_info(chip->parent, | |
986 | "Could not set line %u debounce to %u microseconds (%d)", | |
987 | offset, debounce, ret); | |
988 | ||
989 | return ret; | |
168ef3d9 FB |
990 | } |
991 | ||
2956b5d9 MW |
992 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
993 | unsigned long config) | |
994 | { | |
995 | u32 debounce; | |
996 | ||
997 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
998 | return -ENOTSUPP; | |
999 | ||
1000 | debounce = pinconf_to_config_argument(config); | |
1001 | return omap_gpio_debounce(chip, offset, debounce); | |
1002 | } | |
1003 | ||
a0e827c6 | 1004 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1005 | { |
1006 | struct gpio_bank *bank; | |
1007 | unsigned long flags; | |
1008 | ||
d99f7aec | 1009 | bank = gpiochip_get_data(chip); |
4dbada2b | 1010 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1011 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1012 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1013 | } |
1014 | ||
1015 | /*---------------------------------------------------------------------*/ | |
1016 | ||
e4b2ae7a | 1017 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1018 | { |
e5ff4440 | 1019 | static bool called; |
9f7065da TL |
1020 | u32 rev; |
1021 | ||
e5ff4440 | 1022 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1023 | return; |
1024 | ||
661553b9 | 1025 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1026 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1027 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1028 | |
1029 | called = true; | |
9f7065da TL |
1030 | } |
1031 | ||
03e128ca | 1032 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1033 | { |
ab985f0f TKD |
1034 | void __iomem *base = bank->base; |
1035 | u32 l = 0xffffffff; | |
2fae7fbe | 1036 | |
ab985f0f TKD |
1037 | if (bank->width == 16) |
1038 | l = 0xffff; | |
1039 | ||
d0d665a8 | 1040 | if (bank->is_mpuio) { |
661553b9 | 1041 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1042 | return; |
2fae7fbe | 1043 | } |
ab985f0f | 1044 | |
a0e827c6 JMC |
1045 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1046 | bank->regs->irqenable_inv); | |
1047 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1048 | !bank->regs->irqenable_inv); | |
ab985f0f | 1049 | if (bank->regs->debounce_en) |
661553b9 | 1050 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1051 | |
2dc983c5 | 1052 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1053 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1054 | /* Initialize interface clk ungated, module enabled */ |
1055 | if (bank->regs->ctrl) | |
661553b9 | 1056 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1057 | } |
1058 | ||
46824e22 | 1059 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1060 | { |
81930328 | 1061 | struct gpio_irq_chip *irq; |
2fae7fbe | 1062 | static int gpio; |
088413bc | 1063 | const char *label; |
fb655f57 | 1064 | int irq_base = 0; |
6ef7f385 | 1065 | int ret; |
2fae7fbe | 1066 | |
2fae7fbe VC |
1067 | /* |
1068 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1069 | * over to the generic ones | |
1070 | */ | |
1071 | bank->chip.request = omap_gpio_request; | |
1072 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1073 | bank->chip.get_direction = omap_gpio_get_direction; |
1074 | bank->chip.direction_input = omap_gpio_input; | |
1075 | bank->chip.get = omap_gpio_get; | |
1076 | bank->chip.direction_output = omap_gpio_output; | |
2956b5d9 | 1077 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1078 | bank->chip.set = omap_gpio_set; |
d0d665a8 | 1079 | if (bank->is_mpuio) { |
2fae7fbe | 1080 | bank->chip.label = "mpuio"; |
6ed87c5b | 1081 | if (bank->regs->wkup_en) |
58383c78 | 1082 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1083 | bank->chip.base = OMAP_MPUIO(0); |
1084 | } else { | |
088413bc LW |
1085 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1086 | gpio, gpio + bank->width - 1); | |
1087 | if (!label) | |
1088 | return -ENOMEM; | |
1089 | bank->chip.label = label; | |
2fae7fbe | 1090 | bank->chip.base = gpio; |
2fae7fbe | 1091 | } |
d5f46247 | 1092 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1093 | |
fb655f57 JMC |
1094 | #ifdef CONFIG_ARCH_OMAP1 |
1095 | /* | |
1096 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1097 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1098 | */ | |
2ed36f30 BG |
1099 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1100 | -1, 0, bank->width, 0); | |
fb655f57 | 1101 | if (irq_base < 0) { |
7b1e5dc8 | 1102 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1103 | return -ENODEV; |
1104 | } | |
1105 | #endif | |
1106 | ||
d2d05c65 TL |
1107 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1108 | if (bank->is_mpuio) { | |
1109 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
d2d05c65 TL |
1110 | if (!bank->regs->wkup_en) |
1111 | irqc->irq_set_wake = NULL; | |
1112 | } | |
1113 | ||
81930328 GS |
1114 | irq = &bank->chip.irq; |
1115 | irq->chip = irqc; | |
1116 | irq->handler = handle_bad_irq; | |
1117 | irq->default_type = IRQ_TYPE_NONE; | |
1118 | irq->num_parents = 1; | |
1119 | irq->parents = &bank->irq; | |
1120 | irq->first = irq_base; | |
fb655f57 | 1121 | |
81930328 | 1122 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1123 | if (ret) { |
7b1e5dc8 | 1124 | dev_err(bank->chip.parent, |
81930328 GS |
1125 | "Could not register gpio chip %d\n", ret); |
1126 | return ret; | |
fb655f57 JMC |
1127 | } |
1128 | ||
7b1e5dc8 GS |
1129 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1130 | omap_gpio_irq_handler, | |
1131 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1132 | if (ret) |
1133 | gpiochip_remove(&bank->chip); | |
1134 | ||
81930328 GS |
1135 | if (!bank->is_mpuio) |
1136 | gpio += bank->width; | |
1137 | ||
450fa54c | 1138 | return ret; |
2fae7fbe VC |
1139 | } |
1140 | ||
384ebe1c BC |
1141 | static const struct of_device_id omap_gpio_match[]; |
1142 | ||
3836309d | 1143 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1144 | { |
862ff640 | 1145 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1146 | struct device_node *node = dev->of_node; |
1147 | const struct of_device_id *match; | |
f6817a2c | 1148 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1149 | struct resource *res; |
5e1c5ff4 | 1150 | struct gpio_bank *bank; |
46824e22 | 1151 | struct irq_chip *irqc; |
6ef7f385 | 1152 | int ret; |
5e1c5ff4 | 1153 | |
384ebe1c BC |
1154 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1155 | ||
e56aee18 | 1156 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1157 | if (!pdata) |
96751fcb | 1158 | return -EINVAL; |
5492fb1a | 1159 | |
f97364c9 | 1160 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); |
9117d40b | 1161 | if (!bank) |
96751fcb | 1162 | return -ENOMEM; |
92105bb7 | 1163 | |
46824e22 NM |
1164 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1165 | if (!irqc) | |
1166 | return -ENOMEM; | |
1167 | ||
3d009c8c | 1168 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1169 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1170 | irqc->irq_ack = omap_gpio_ack_irq, | |
1171 | irqc->irq_mask = omap_gpio_mask_irq, | |
1172 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1173 | irqc->irq_set_type = omap_gpio_irq_type, | |
1174 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
aca82d1c GS |
1175 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, |
1176 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
46824e22 | 1177 | irqc->name = dev_name(&pdev->dev); |
0c0451e7 | 1178 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; |
46824e22 | 1179 | |
89d18e3a GS |
1180 | bank->irq = platform_get_irq(pdev, 0); |
1181 | if (bank->irq <= 0) { | |
1182 | if (!bank->irq) | |
1183 | bank->irq = -ENXIO; | |
1184 | if (bank->irq != -EPROBE_DEFER) | |
1185 | dev_err(dev, | |
1186 | "can't get irq resource ret=%d\n", bank->irq); | |
1187 | return bank->irq; | |
44169075 | 1188 | } |
5e1c5ff4 | 1189 | |
58383c78 | 1190 | bank->chip.parent = dev; |
c23837ce | 1191 | bank->chip.owner = THIS_MODULE; |
77640aab | 1192 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1193 | bank->stride = pdata->bank_stride; |
d5f46247 | 1194 | bank->width = pdata->bank_width; |
d0d665a8 | 1195 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1196 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1197 | bank->regs = pdata->regs; |
384ebe1c BC |
1198 | #ifdef CONFIG_OF_GPIO |
1199 | bank->chip.of_node = of_node_get(node); | |
1200 | #endif | |
a2797bea JH |
1201 | if (node) { |
1202 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1203 | bank->loses_context = true; | |
1204 | } else { | |
1205 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1206 | |
1207 | if (bank->loses_context) | |
1208 | bank->get_context_loss_count = | |
1209 | pdata->get_context_loss_count; | |
384ebe1c BC |
1210 | } |
1211 | ||
fa87931a | 1212 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1213 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1214 | else |
a0e827c6 | 1215 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1216 | |
4dbada2b | 1217 | raw_spin_lock_init(&bank->lock); |
450fa54c | 1218 | raw_spin_lock_init(&bank->wa_lock); |
9f7065da | 1219 | |
77640aab VC |
1220 | /* Static mapping, never released */ |
1221 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1222 | bank->base = devm_ioremap_resource(dev, res); |
1223 | if (IS_ERR(bank->base)) { | |
717f70e3 | 1224 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1225 | } |
1226 | ||
5d9452e7 | 1227 | if (bank->dbck_flag) { |
7b1e5dc8 | 1228 | bank->dbck = devm_clk_get(dev, "dbclk"); |
5d9452e7 | 1229 | if (IS_ERR(bank->dbck)) { |
7b1e5dc8 | 1230 | dev_err(dev, |
5d9452e7 GS |
1231 | "Could not get gpio dbck. Disable debounce\n"); |
1232 | bank->dbck_flag = false; | |
1233 | } else { | |
1234 | clk_prepare(bank->dbck); | |
1235 | } | |
1236 | } | |
1237 | ||
065cd795 TKD |
1238 | platform_set_drvdata(pdev, bank); |
1239 | ||
7b1e5dc8 GS |
1240 | pm_runtime_enable(dev); |
1241 | pm_runtime_irq_safe(dev); | |
1242 | pm_runtime_get_sync(dev); | |
77640aab | 1243 | |
d0d665a8 | 1244 | if (bank->is_mpuio) |
a0e827c6 | 1245 | omap_mpuio_init(bank); |
ab985f0f | 1246 | |
03e128ca | 1247 | omap_gpio_mod_init(bank); |
6ef7f385 | 1248 | |
46824e22 | 1249 | ret = omap_gpio_chip_init(bank, irqc); |
5e606abe | 1250 | if (ret) { |
7b1e5dc8 GS |
1251 | pm_runtime_put_sync(dev); |
1252 | pm_runtime_disable(dev); | |
e2c3c196 AY |
1253 | if (bank->dbck_flag) |
1254 | clk_unprepare(bank->dbck); | |
6ef7f385 | 1255 | return ret; |
5e606abe | 1256 | } |
6ef7f385 | 1257 | |
9a748053 | 1258 | omap_gpio_show_rev(bank); |
9f7065da | 1259 | |
7b1e5dc8 | 1260 | pm_runtime_put(dev); |
55b93c32 | 1261 | |
03e128ca | 1262 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1263 | |
879fe324 | 1264 | return 0; |
5e1c5ff4 TL |
1265 | } |
1266 | ||
cac089f9 TL |
1267 | static int omap_gpio_remove(struct platform_device *pdev) |
1268 | { | |
1269 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1270 | ||
1271 | list_del(&bank->node); | |
1272 | gpiochip_remove(&bank->chip); | |
7b1e5dc8 | 1273 | pm_runtime_disable(&pdev->dev); |
5d9452e7 GS |
1274 | if (bank->dbck_flag) |
1275 | clk_unprepare(bank->dbck); | |
cac089f9 TL |
1276 | |
1277 | return 0; | |
1278 | } | |
1279 | ||
55b93c32 TKD |
1280 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1281 | ||
ecb2312f | 1282 | #if defined(CONFIG_PM) |
60a3437d | 1283 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1284 | |
2dc983c5 | 1285 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1286 | { |
2dc983c5 TKD |
1287 | struct platform_device *pdev = to_platform_device(dev); |
1288 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1289 | u32 l1 = 0, l2 = 0; | |
1290 | unsigned long flags; | |
68942edb | 1291 | u32 wake_low, wake_hi; |
8865b9b6 | 1292 | |
4dbada2b | 1293 | raw_spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1294 | |
1295 | /* | |
1296 | * Only edges can generate a wakeup event to the PRCM. | |
1297 | * | |
1298 | * Therefore, ensure any wake-up capable GPIOs have | |
1299 | * edge-detection enabled before going idle to ensure a wakeup | |
1300 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1301 | * NDA TRM 25.5.3.1) | |
1302 | * | |
1303 | * The normal values will be restored upon ->runtime_resume() | |
1304 | * by writing back the values saved in bank->context. | |
1305 | */ | |
1306 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1307 | if (wake_low) | |
661553b9 | 1308 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1309 | bank->base + bank->regs->fallingdetect); |
1310 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1311 | if (wake_hi) | |
661553b9 | 1312 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1313 | bank->base + bank->regs->risingdetect); |
1314 | ||
b3c64bc3 KH |
1315 | if (!bank->enabled_non_wakeup_gpios) |
1316 | goto update_gpio_context_count; | |
1317 | ||
2dc983c5 TKD |
1318 | if (bank->power_mode != OFF_MODE) { |
1319 | bank->power_mode = 0; | |
41d87cbd | 1320 | goto update_gpio_context_count; |
2dc983c5 TKD |
1321 | } |
1322 | /* | |
1323 | * If going to OFF, remove triggering for all | |
1324 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1325 | * generated. See OMAP2420 Errata item 1.101. | |
1326 | */ | |
661553b9 | 1327 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1328 | bank->regs->datain); |
c6f31c9e TKD |
1329 | l1 = bank->context.fallingdetect; |
1330 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1331 | |
2dc983c5 TKD |
1332 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1333 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1334 | |
661553b9 VK |
1335 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1336 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1337 | |
2dc983c5 | 1338 | bank->workaround_enabled = true; |
3f1686a9 | 1339 | |
41d87cbd | 1340 | update_gpio_context_count: |
2dc983c5 TKD |
1341 | if (bank->get_context_loss_count) |
1342 | bank->context_loss_count = | |
7b1e5dc8 | 1343 | bank->get_context_loss_count(dev); |
60a3437d | 1344 | |
a0e827c6 | 1345 | omap_gpio_dbck_disable(bank); |
4dbada2b | 1346 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1347 | |
2dc983c5 | 1348 | return 0; |
3ac4fa99 JY |
1349 | } |
1350 | ||
352a2d5b JH |
1351 | static void omap_gpio_init_context(struct gpio_bank *p); |
1352 | ||
2dc983c5 | 1353 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1354 | { |
2dc983c5 TKD |
1355 | struct platform_device *pdev = to_platform_device(dev); |
1356 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1357 | u32 l = 0, gen, gen0, gen1; |
1358 | unsigned long flags; | |
a2797bea | 1359 | int c; |
8865b9b6 | 1360 | |
4dbada2b | 1361 | raw_spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1362 | |
1363 | /* | |
1364 | * On the first resume during the probe, the context has not | |
1365 | * been initialised and so initialise it now. Also initialise | |
1366 | * the context loss count. | |
1367 | */ | |
1368 | if (bank->loses_context && !bank->context_valid) { | |
1369 | omap_gpio_init_context(bank); | |
1370 | ||
1371 | if (bank->get_context_loss_count) | |
1372 | bank->context_loss_count = | |
7b1e5dc8 | 1373 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1374 | } |
1375 | ||
a0e827c6 | 1376 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1377 | |
1378 | /* | |
1379 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1380 | * GPIOs were set to edge trigger also in order to be able to | |
1381 | * generate a PRCM wakeup. Here we restore the | |
1382 | * pre-runtime_suspend() values for edge triggering. | |
1383 | */ | |
661553b9 | 1384 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1385 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1386 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1387 | bank->base + bank->regs->risingdetect); |
1388 | ||
a2797bea JH |
1389 | if (bank->loses_context) { |
1390 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1391 | omap_gpio_restore_context(bank); |
1392 | } else { | |
7b1e5dc8 | 1393 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1394 | if (c != bank->context_loss_count) { |
1395 | omap_gpio_restore_context(bank); | |
1396 | } else { | |
4dbada2b | 1397 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
a2797bea JH |
1398 | return 0; |
1399 | } | |
60a3437d | 1400 | } |
2dc983c5 | 1401 | } |
43ffcd9a | 1402 | |
1b128703 | 1403 | if (!bank->workaround_enabled) { |
4dbada2b | 1404 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1b128703 TKD |
1405 | return 0; |
1406 | } | |
1407 | ||
661553b9 | 1408 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1409 | |
2dc983c5 TKD |
1410 | /* |
1411 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1412 | * state. If so, generate an IRQ by software. This is | |
1413 | * horribly racy, but it's the best we can do to work around | |
1414 | * this silicon bug. | |
1415 | */ | |
1416 | l ^= bank->saved_datain; | |
1417 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1418 | |
2dc983c5 TKD |
1419 | /* |
1420 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1421 | * configured with falling edge only; and vice versa. | |
1422 | */ | |
c6f31c9e | 1423 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1424 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1425 | |
c6f31c9e | 1426 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1427 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1428 | |
2dc983c5 | 1429 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1430 | gen = l & (~(bank->context.fallingdetect) & |
1431 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1432 | /* Consider all GPIO IRQs needed to be updated */ |
1433 | gen |= gen0 | gen1; | |
82dbb9d3 | 1434 | |
2dc983c5 TKD |
1435 | if (gen) { |
1436 | u32 old0, old1; | |
82dbb9d3 | 1437 | |
661553b9 VK |
1438 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1439 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1440 | |
4e962e89 | 1441 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1442 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1443 | bank->regs->leveldetect0); |
661553b9 | 1444 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1445 | bank->regs->leveldetect1); |
2dc983c5 | 1446 | } |
9ea14d8c | 1447 | |
4e962e89 | 1448 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1449 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1450 | bank->regs->leveldetect0); |
661553b9 | 1451 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1452 | bank->regs->leveldetect1); |
3ac4fa99 | 1453 | } |
661553b9 VK |
1454 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1455 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1456 | } |
1457 | ||
1458 | bank->workaround_enabled = false; | |
4dbada2b | 1459 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2dc983c5 TKD |
1460 | |
1461 | return 0; | |
1462 | } | |
ecb2312f | 1463 | #endif /* CONFIG_PM */ |
2dc983c5 | 1464 | |
cac089f9 | 1465 | #if IS_BUILTIN(CONFIG_GPIO_OMAP) |
2dc983c5 TKD |
1466 | void omap2_gpio_prepare_for_idle(int pwr_mode) |
1467 | { | |
1468 | struct gpio_bank *bank; | |
1469 | ||
1470 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1471 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1472 | continue; |
1473 | ||
1474 | bank->power_mode = pwr_mode; | |
1475 | ||
7b1e5dc8 | 1476 | pm_runtime_put_sync_suspend(bank->chip.parent); |
2dc983c5 TKD |
1477 | } |
1478 | } | |
1479 | ||
1480 | void omap2_gpio_resume_after_idle(void) | |
1481 | { | |
1482 | struct gpio_bank *bank; | |
1483 | ||
1484 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1485 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1486 | continue; |
1487 | ||
7b1e5dc8 | 1488 | pm_runtime_get_sync(bank->chip.parent); |
3ac4fa99 | 1489 | } |
3ac4fa99 | 1490 | } |
cac089f9 | 1491 | #endif |
3ac4fa99 | 1492 | |
ecb2312f | 1493 | #if defined(CONFIG_PM) |
352a2d5b JH |
1494 | static void omap_gpio_init_context(struct gpio_bank *p) |
1495 | { | |
1496 | struct omap_gpio_reg_offs *regs = p->regs; | |
1497 | void __iomem *base = p->base; | |
1498 | ||
661553b9 VK |
1499 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1500 | p->context.oe = readl_relaxed(base + regs->direction); | |
1501 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1502 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1503 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1504 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1505 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1506 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1507 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1508 | |
1509 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1510 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1511 | else |
661553b9 | 1512 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1513 | |
1514 | p->context_valid = true; | |
1515 | } | |
1516 | ||
60a3437d | 1517 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1518 | { |
661553b9 | 1519 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1520 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1521 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1522 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1523 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1524 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1525 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1526 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1527 | bank->base + bank->regs->risingdetect); |
661553b9 | 1528 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1529 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1530 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1531 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1532 | bank->base + bank->regs->set_dataout); |
1533 | else | |
661553b9 | 1534 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1535 | bank->base + bank->regs->dataout); |
661553b9 | 1536 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1537 | |
ae547354 | 1538 | if (bank->dbck_enable_mask) { |
661553b9 | 1539 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1540 | bank->regs->debounce); |
661553b9 | 1541 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1542 | bank->base + bank->regs->debounce_en); |
1543 | } | |
ba805be5 | 1544 | |
661553b9 | 1545 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1546 | bank->base + bank->regs->irqenable); |
661553b9 | 1547 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1548 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1549 | } |
ecb2312f | 1550 | #endif /* CONFIG_PM */ |
55b93c32 | 1551 | #else |
2dc983c5 TKD |
1552 | #define omap_gpio_runtime_suspend NULL |
1553 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1554 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1555 | #endif |
1556 | ||
55b93c32 | 1557 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1558 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1559 | NULL) | |
55b93c32 TKD |
1560 | }; |
1561 | ||
384ebe1c BC |
1562 | #if defined(CONFIG_OF) |
1563 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1564 | .revision = OMAP24XX_GPIO_REVISION, | |
1565 | .direction = OMAP24XX_GPIO_OE, | |
1566 | .datain = OMAP24XX_GPIO_DATAIN, | |
1567 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1568 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1569 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1570 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1571 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1572 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1573 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1574 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1575 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1576 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1577 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1578 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1579 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1580 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1581 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1582 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1583 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1584 | }; | |
1585 | ||
1586 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1587 | .revision = OMAP4_GPIO_REVISION, | |
1588 | .direction = OMAP4_GPIO_OE, | |
1589 | .datain = OMAP4_GPIO_DATAIN, | |
1590 | .dataout = OMAP4_GPIO_DATAOUT, | |
1591 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1592 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1593 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1594 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1595 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1596 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1597 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1598 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1599 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1600 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1601 | .ctrl = OMAP4_GPIO_CTRL, | |
1602 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1603 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1604 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1605 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1606 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1607 | }; | |
1608 | ||
e9a65bb6 | 1609 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1610 | .regs = &omap2_gpio_regs, |
1611 | .bank_width = 32, | |
1612 | .dbck_flag = false, | |
1613 | }; | |
1614 | ||
e9a65bb6 | 1615 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1616 | .regs = &omap2_gpio_regs, |
1617 | .bank_width = 32, | |
1618 | .dbck_flag = true, | |
1619 | }; | |
1620 | ||
e9a65bb6 | 1621 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1622 | .regs = &omap4_gpio_regs, |
1623 | .bank_width = 32, | |
1624 | .dbck_flag = true, | |
1625 | }; | |
1626 | ||
1627 | static const struct of_device_id omap_gpio_match[] = { | |
1628 | { | |
1629 | .compatible = "ti,omap4-gpio", | |
1630 | .data = &omap4_pdata, | |
1631 | }, | |
1632 | { | |
1633 | .compatible = "ti,omap3-gpio", | |
1634 | .data = &omap3_pdata, | |
1635 | }, | |
1636 | { | |
1637 | .compatible = "ti,omap2-gpio", | |
1638 | .data = &omap2_pdata, | |
1639 | }, | |
1640 | { }, | |
1641 | }; | |
1642 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1643 | #endif | |
1644 | ||
77640aab VC |
1645 | static struct platform_driver omap_gpio_driver = { |
1646 | .probe = omap_gpio_probe, | |
cac089f9 | 1647 | .remove = omap_gpio_remove, |
77640aab VC |
1648 | .driver = { |
1649 | .name = "omap_gpio", | |
55b93c32 | 1650 | .pm = &gpio_pm_ops, |
384ebe1c | 1651 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1652 | }, |
1653 | }; | |
1654 | ||
5e1c5ff4 | 1655 | /* |
77640aab VC |
1656 | * gpio driver register needs to be done before |
1657 | * machine_init functions access gpio APIs. | |
1658 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1659 | */ |
77640aab | 1660 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1661 | { |
77640aab | 1662 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1663 | } |
77640aab | 1664 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1665 | |
1666 | static void __exit omap_gpio_exit(void) | |
1667 | { | |
1668 | platform_driver_unregister(&omap_gpio_driver); | |
1669 | } | |
1670 | module_exit(omap_gpio_exit); | |
1671 | ||
1672 | MODULE_DESCRIPTION("omap gpio driver"); | |
1673 | MODULE_ALIAS("platform:gpio-omap"); | |
1674 | MODULE_LICENSE("GPL v2"); |