Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
b764a586 | 22 | #include <linux/cpu_pm.h> |
96751fcb | 23 | #include <linux/device.h> |
77640aab | 24 | #include <linux/pm_runtime.h> |
55b93c32 | 25 | #include <linux/pm.h> |
384ebe1c BC |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
b7351b07 | 28 | #include <linux/gpio/driver.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
6d62e216 C |
34 | struct gpio_regs { |
35 | u32 irqenable1; | |
36 | u32 irqenable2; | |
37 | u32 wake_en; | |
38 | u32 ctrl; | |
39 | u32 oe; | |
40 | u32 leveldetect0; | |
41 | u32 leveldetect1; | |
42 | u32 risingdetect; | |
43 | u32 fallingdetect; | |
44 | u32 dataout; | |
ae547354 NM |
45 | u32 debounce; |
46 | u32 debounce_en; | |
6d62e216 C |
47 | }; |
48 | ||
5e1c5ff4 | 49 | struct gpio_bank { |
03e128ca | 50 | struct list_head node; |
92105bb7 | 51 | void __iomem *base; |
30cefeac | 52 | int irq; |
3ac4fa99 JY |
53 | u32 non_wakeup_gpios; |
54 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 55 | struct gpio_regs context; |
3ac4fa99 | 56 | u32 saved_datain; |
b144ff6f | 57 | u32 level_mask; |
4318f36b | 58 | u32 toggle_mask; |
4dbada2b | 59 | raw_spinlock_t lock; |
450fa54c | 60 | raw_spinlock_t wa_lock; |
52e31344 | 61 | struct gpio_chip chip; |
89db9482 | 62 | struct clk *dbck; |
b764a586 TL |
63 | struct notifier_block nb; |
64 | unsigned int is_suspended:1; | |
058af1ea | 65 | u32 mod_usage; |
fa365e4d | 66 | u32 irq_usage; |
8865b9b6 | 67 | u32 dbck_enable_mask; |
72f83af9 | 68 | bool dbck_enabled; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
352a2d5b | 72 | bool context_valid; |
5de62b86 | 73 | int stride; |
d5f46247 | 74 | u32 width; |
60a3437d | 75 | int context_loss_count; |
fa87931a | 76 | |
04ebcbd8 | 77 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
442af140 JK |
78 | void (*set_dataout_multiple)(struct gpio_bank *bank, |
79 | unsigned long *mask, unsigned long *bits); | |
60a3437d | 80 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
81 | |
82 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
83 | }; |
84 | ||
c8eef65a | 85 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 86 | |
fa365e4d | 87 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 88 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 89 | |
3d009c8c TL |
90 | static void omap_gpio_unmask_irq(struct irq_data *d); |
91 | ||
a0e827c6 | 92 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 93 | { |
fb655f57 | 94 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 95 | return gpiochip_get_data(chip); |
25db711d BC |
96 | } |
97 | ||
a0e827c6 JMC |
98 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
99 | int is_input) | |
5e1c5ff4 | 100 | { |
92105bb7 | 101 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
102 | u32 l; |
103 | ||
fa87931a | 104 | reg += bank->regs->direction; |
661553b9 | 105 | l = readl_relaxed(reg); |
5e1c5ff4 | 106 | if (is_input) |
b1e9fec2 | 107 | l |= BIT(gpio); |
5e1c5ff4 | 108 | else |
b1e9fec2 | 109 | l &= ~(BIT(gpio)); |
661553b9 | 110 | writel_relaxed(l, reg); |
41d87cbd | 111 | bank->context.oe = l; |
5e1c5ff4 TL |
112 | } |
113 | ||
fa87931a KH |
114 | |
115 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 116 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 117 | int enable) |
5e1c5ff4 | 118 | { |
92105bb7 | 119 | void __iomem *reg = bank->base; |
04ebcbd8 | 120 | u32 l = BIT(offset); |
5e1c5ff4 | 121 | |
2c836f7e | 122 | if (enable) { |
fa87931a | 123 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
124 | bank->context.dataout |= l; |
125 | } else { | |
fa87931a | 126 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
127 | bank->context.dataout &= ~l; |
128 | } | |
5e1c5ff4 | 129 | |
661553b9 | 130 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
131 | } |
132 | ||
fa87931a | 133 | /* set data out value using mask register */ |
04ebcbd8 | 134 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 135 | int enable) |
5e1c5ff4 | 136 | { |
fa87931a | 137 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 138 | u32 gpio_bit = BIT(offset); |
fa87931a | 139 | u32 l; |
5e1c5ff4 | 140 | |
661553b9 | 141 | l = readl_relaxed(reg); |
fa87931a KH |
142 | if (enable) |
143 | l |= gpio_bit; | |
144 | else | |
145 | l &= ~gpio_bit; | |
661553b9 | 146 | writel_relaxed(l, reg); |
41d87cbd | 147 | bank->context.dataout = l; |
5e1c5ff4 TL |
148 | } |
149 | ||
a0e827c6 | 150 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 151 | { |
fa87931a | 152 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 153 | |
b1e9fec2 | 154 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 155 | } |
b37c45b8 | 156 | |
a0e827c6 | 157 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 158 | { |
fa87931a | 159 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 160 | |
b1e9fec2 | 161 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
162 | } |
163 | ||
442af140 JK |
164 | /* set multiple data out values using dedicate set/clear register */ |
165 | static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, | |
166 | unsigned long *mask, | |
167 | unsigned long *bits) | |
168 | { | |
169 | void __iomem *reg = bank->base; | |
170 | u32 l; | |
171 | ||
172 | l = *bits & *mask; | |
173 | writel_relaxed(l, reg + bank->regs->set_dataout); | |
174 | bank->context.dataout |= l; | |
175 | ||
176 | l = ~*bits & *mask; | |
177 | writel_relaxed(l, reg + bank->regs->clr_dataout); | |
178 | bank->context.dataout &= ~l; | |
179 | } | |
180 | ||
181 | /* set multiple data out values using mask register */ | |
182 | static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, | |
183 | unsigned long *mask, | |
184 | unsigned long *bits) | |
185 | { | |
186 | void __iomem *reg = bank->base + bank->regs->dataout; | |
187 | u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); | |
188 | ||
189 | writel_relaxed(l, reg); | |
190 | bank->context.dataout = l; | |
191 | } | |
192 | ||
193 | static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank, | |
194 | unsigned long *mask) | |
195 | { | |
196 | void __iomem *reg = bank->base + bank->regs->datain; | |
197 | ||
198 | return readl_relaxed(reg) & *mask; | |
199 | } | |
200 | ||
201 | static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank, | |
202 | unsigned long *mask) | |
203 | { | |
204 | void __iomem *reg = bank->base + bank->regs->dataout; | |
205 | ||
206 | return readl_relaxed(reg) & *mask; | |
207 | } | |
208 | ||
a0e827c6 | 209 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 210 | { |
661553b9 | 211 | int l = readl_relaxed(base + reg); |
ece9528e | 212 | |
862ff640 | 213 | if (set) |
ece9528e KH |
214 | l |= mask; |
215 | else | |
216 | l &= ~mask; | |
217 | ||
661553b9 | 218 | writel_relaxed(l, base + reg); |
ece9528e | 219 | } |
92105bb7 | 220 | |
a0e827c6 | 221 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
222 | { |
223 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 224 | clk_enable(bank->dbck); |
72f83af9 | 225 | bank->dbck_enabled = true; |
9e303f22 | 226 | |
661553b9 | 227 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 228 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
229 | } |
230 | } | |
231 | ||
a0e827c6 | 232 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
233 | { |
234 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
235 | /* |
236 | * Disable debounce before cutting it's clock. If debounce is | |
237 | * enabled but the clock is not, GPIO module seems to be unable | |
238 | * to detect events and generate interrupts at least on OMAP3. | |
239 | */ | |
661553b9 | 240 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 241 | |
5d9452e7 | 242 | clk_disable(bank->dbck); |
72f83af9 TKD |
243 | bank->dbck_enabled = false; |
244 | } | |
245 | } | |
246 | ||
168ef3d9 | 247 | /** |
a0e827c6 | 248 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 249 | * @bank: the gpio bank we're acting upon |
4a58d229 | 250 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
251 | * @debounce: debounce time to use |
252 | * | |
e85ec6c3 GS |
253 | * OMAP's debounce time is in 31us steps |
254 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
255 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
256 | * |
257 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 258 | */ |
83977443 DR |
259 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
260 | unsigned debounce) | |
168ef3d9 | 261 | { |
9942da0e | 262 | void __iomem *reg; |
168ef3d9 FB |
263 | u32 val; |
264 | u32 l; | |
e85ec6c3 | 265 | bool enable = !!debounce; |
168ef3d9 | 266 | |
77640aab | 267 | if (!bank->dbck_flag) |
83977443 | 268 | return -ENOTSUPP; |
77640aab | 269 | |
e85ec6c3 GS |
270 | if (enable) { |
271 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
272 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
273 | return -EINVAL; | |
e85ec6c3 | 274 | } |
168ef3d9 | 275 | |
4a58d229 | 276 | l = BIT(offset); |
168ef3d9 | 277 | |
5d9452e7 | 278 | clk_enable(bank->dbck); |
9942da0e | 279 | reg = bank->base + bank->regs->debounce; |
661553b9 | 280 | writel_relaxed(debounce, reg); |
168ef3d9 | 281 | |
9942da0e | 282 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 283 | val = readl_relaxed(reg); |
168ef3d9 | 284 | |
e85ec6c3 | 285 | if (enable) |
168ef3d9 | 286 | val |= l; |
6fd9c421 | 287 | else |
168ef3d9 | 288 | val &= ~l; |
f7ec0b0b | 289 | bank->dbck_enable_mask = val; |
168ef3d9 | 290 | |
661553b9 | 291 | writel_relaxed(val, reg); |
5d9452e7 | 292 | clk_disable(bank->dbck); |
6fd9c421 TKD |
293 | /* |
294 | * Enable debounce clock per module. | |
295 | * This call is mandatory because in omap_gpio_request() when | |
296 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
297 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
298 | * used within _gpio_dbck_enable() is still not initialized at | |
299 | * that point. Therefore we have to enable dbck here. | |
300 | */ | |
a0e827c6 | 301 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
302 | if (bank->dbck_enable_mask) { |
303 | bank->context.debounce = debounce; | |
304 | bank->context.debounce_en = val; | |
305 | } | |
83977443 DR |
306 | |
307 | return 0; | |
168ef3d9 FB |
308 | } |
309 | ||
c9c55d92 | 310 | /** |
a0e827c6 | 311 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 312 | * @bank: the gpio bank we're acting upon |
4a58d229 | 313 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
314 | * |
315 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
316 | * this is the only gpio in this bank using debounce, then clear the debounce | |
317 | * time too. The debounce clock will also be disabled when calling this function | |
318 | * if this is the only gpio in the bank using debounce. | |
319 | */ | |
4a58d229 | 320 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 321 | { |
4a58d229 | 322 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
323 | |
324 | if (!bank->dbck_flag) | |
325 | return; | |
326 | ||
327 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
328 | return; | |
329 | ||
330 | bank->dbck_enable_mask &= ~gpio_bit; | |
331 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 332 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
333 | bank->base + bank->regs->debounce_en); |
334 | ||
335 | if (!bank->dbck_enable_mask) { | |
336 | bank->context.debounce = 0; | |
661553b9 | 337 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 338 | bank->regs->debounce); |
5d9452e7 | 339 | clk_disable(bank->dbck); |
c9c55d92 JH |
340 | bank->dbck_enabled = false; |
341 | } | |
342 | } | |
343 | ||
da38ef3e TL |
344 | /* |
345 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
346 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
347 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
348 | * are capable waking up the system from off mode. | |
349 | */ | |
350 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
351 | { | |
352 | u32 no_wake = bank->non_wakeup_gpios; | |
353 | ||
354 | if (no_wake) | |
355 | return !!(~no_wake & gpio_mask); | |
356 | ||
357 | return false; | |
358 | } | |
359 | ||
a0e827c6 | 360 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 361 | unsigned trigger) |
5e1c5ff4 | 362 | { |
3ac4fa99 | 363 | void __iomem *base = bank->base; |
b1e9fec2 | 364 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 365 | |
a0e827c6 JMC |
366 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
367 | trigger & IRQ_TYPE_LEVEL_LOW); | |
368 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
369 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
e6818d29 RK |
370 | |
371 | /* | |
372 | * We need the edge detection enabled for to allow the GPIO block | |
373 | * to be woken from idle state. Set the appropriate edge detection | |
374 | * in addition to the level detection. | |
375 | */ | |
a0e827c6 | 376 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, |
e6818d29 | 377 | trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); |
a0e827c6 | 378 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, |
e6818d29 | 379 | trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); |
5e571f38 | 380 | |
41d87cbd | 381 | bank->context.leveldetect0 = |
661553b9 | 382 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 383 | bank->context.leveldetect1 = |
661553b9 | 384 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 385 | bank->context.risingdetect = |
661553b9 | 386 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 387 | bank->context.fallingdetect = |
661553b9 | 388 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
389 | |
390 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
00ded24c TL |
391 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
392 | bank->context.wake_en = | |
393 | readl_relaxed(bank->base + bank->regs->wkup_en); | |
41d87cbd | 394 | } |
5e571f38 | 395 | |
55b220ca | 396 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 397 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
398 | /* |
399 | * Log the edge gpio and manually trigger the IRQ | |
400 | * after resume if the input level changes | |
401 | * to avoid irq lost during PER RET/OFF mode | |
402 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
403 | */ | |
404 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
405 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
406 | else | |
407 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
408 | } | |
5eb3bb9c | 409 | |
9ea14d8c | 410 | bank->level_mask = |
661553b9 VK |
411 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
412 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
413 | } |
414 | ||
9198bcd3 | 415 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
416 | /* |
417 | * This only applies to chips that can't do both rising and falling edge | |
418 | * detection at once. For all other chips, this function is a noop. | |
419 | */ | |
a0e827c6 | 420 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
421 | { |
422 | void __iomem *reg = bank->base; | |
423 | u32 l = 0; | |
424 | ||
5e571f38 | 425 | if (!bank->regs->irqctrl) |
4318f36b | 426 | return; |
5e571f38 TKD |
427 | |
428 | reg += bank->regs->irqctrl; | |
4318f36b | 429 | |
661553b9 | 430 | l = readl_relaxed(reg); |
4318f36b | 431 | if ((l >> gpio) & 1) |
b1e9fec2 | 432 | l &= ~(BIT(gpio)); |
4318f36b | 433 | else |
b1e9fec2 | 434 | l |= BIT(gpio); |
4318f36b | 435 | |
661553b9 | 436 | writel_relaxed(l, reg); |
4318f36b | 437 | } |
5e571f38 | 438 | #else |
a0e827c6 | 439 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 440 | #endif |
4318f36b | 441 | |
a0e827c6 JMC |
442 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
443 | unsigned trigger) | |
92105bb7 TL |
444 | { |
445 | void __iomem *reg = bank->base; | |
5e571f38 | 446 | void __iomem *base = bank->base; |
92105bb7 | 447 | u32 l = 0; |
5e1c5ff4 | 448 | |
5e571f38 | 449 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 450 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
451 | } else if (bank->regs->irqctrl) { |
452 | reg += bank->regs->irqctrl; | |
453 | ||
661553b9 | 454 | l = readl_relaxed(reg); |
29501577 | 455 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 456 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 457 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 458 | l |= BIT(gpio); |
6cab4860 | 459 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 460 | l &= ~(BIT(gpio)); |
92105bb7 | 461 | else |
5e571f38 TKD |
462 | return -EINVAL; |
463 | ||
661553b9 | 464 | writel_relaxed(l, reg); |
5e571f38 | 465 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 466 | if (gpio & 0x08) |
5e571f38 | 467 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 468 | else |
5e571f38 TKD |
469 | reg += bank->regs->edgectrl1; |
470 | ||
5e1c5ff4 | 471 | gpio &= 0x07; |
661553b9 | 472 | l = readl_relaxed(reg); |
5e1c5ff4 | 473 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 474 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 475 | l |= 2 << (gpio << 1); |
6cab4860 | 476 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 477 | l |= BIT(gpio << 1); |
5e571f38 TKD |
478 | |
479 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 480 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 481 | bank->context.wake_en = |
661553b9 VK |
482 | readl_relaxed(bank->base + bank->regs->wkup_en); |
483 | writel_relaxed(l, reg); | |
5e1c5ff4 | 484 | } |
92105bb7 | 485 | return 0; |
5e1c5ff4 TL |
486 | } |
487 | ||
a0e827c6 | 488 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
489 | { |
490 | if (bank->regs->pinctrl) { | |
491 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
492 | ||
493 | /* Claim the pin for MPU */ | |
b1e9fec2 | 494 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
495 | } |
496 | ||
497 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
498 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
499 | u32 ctrl; | |
500 | ||
661553b9 | 501 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
502 | /* Module is enabled, clocks are not gated */ |
503 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 504 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
505 | bank->context.ctrl = ctrl; |
506 | } | |
507 | } | |
508 | ||
a0e827c6 | 509 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
510 | { |
511 | void __iomem *base = bank->base; | |
512 | ||
513 | if (bank->regs->wkup_en && | |
514 | !LINE_USED(bank->mod_usage, offset) && | |
515 | !LINE_USED(bank->irq_usage, offset)) { | |
516 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 517 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 518 | bank->context.wake_en = |
661553b9 | 519 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
520 | } |
521 | ||
522 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
523 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
524 | u32 ctrl; | |
525 | ||
661553b9 | 526 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
527 | /* Module is disabled, clocks are gated */ |
528 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 529 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
530 | bank->context.ctrl = ctrl; |
531 | } | |
532 | } | |
533 | ||
b2b20045 | 534 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
535 | { |
536 | void __iomem *reg = bank->base + bank->regs->direction; | |
537 | ||
b2b20045 | 538 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
539 | } |
540 | ||
37e14ecf | 541 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
542 | { |
543 | if (!LINE_USED(bank->mod_usage, offset)) { | |
544 | omap_enable_gpio_module(bank, offset); | |
545 | omap_set_gpio_direction(bank, offset, 1); | |
546 | } | |
37e14ecf | 547 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
548 | } |
549 | ||
a0e827c6 | 550 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 551 | { |
a0e827c6 | 552 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 553 | int retval; |
a6472533 | 554 | unsigned long flags; |
ea5fbe8d | 555 | unsigned offset = d->hwirq; |
92105bb7 | 556 | |
e5c56ed3 | 557 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 558 | return -EINVAL; |
e5c56ed3 | 559 | |
9ea14d8c TKD |
560 | if (!bank->regs->leveldetect0 && |
561 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
562 | return -EINVAL; |
563 | ||
4dbada2b | 564 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 565 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 566 | if (retval) { |
627c89b4 | 567 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 568 | goto error; |
977bd8a9 | 569 | } |
37e14ecf | 570 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 571 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 572 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
573 | retval = -EINVAL; |
574 | goto error; | |
fac7fa16 | 575 | } |
4dbada2b | 576 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
577 | |
578 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 579 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 580 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
581 | /* |
582 | * Edge IRQs are already cleared/acked in irq_handler and | |
583 | * not need to be masked, as result handle_edge_irq() | |
584 | * logic is excessed here and may cause lose of interrupts. | |
585 | * So just use handle_simple_irq. | |
586 | */ | |
587 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 588 | |
1562e461 GS |
589 | return 0; |
590 | ||
591 | error: | |
92105bb7 | 592 | return retval; |
5e1c5ff4 TL |
593 | } |
594 | ||
a0e827c6 | 595 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 596 | { |
92105bb7 | 597 | void __iomem *reg = bank->base; |
5e1c5ff4 | 598 | |
eef4bec7 | 599 | reg += bank->regs->irqstatus; |
661553b9 | 600 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
601 | |
602 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
603 | if (bank->regs->irqstatus2) { |
604 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 605 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 606 | } |
bedfd154 RQ |
607 | |
608 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 609 | readl_relaxed(reg); |
5e1c5ff4 TL |
610 | } |
611 | ||
9943f261 GS |
612 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
613 | unsigned offset) | |
5e1c5ff4 | 614 | { |
9943f261 | 615 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
616 | } |
617 | ||
a0e827c6 | 618 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
619 | { |
620 | void __iomem *reg = bank->base; | |
99c47707 | 621 | u32 l; |
b1e9fec2 | 622 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 623 | |
28f3b5a0 | 624 | reg += bank->regs->irqenable; |
661553b9 | 625 | l = readl_relaxed(reg); |
28f3b5a0 | 626 | if (bank->regs->irqenable_inv) |
99c47707 ID |
627 | l = ~l; |
628 | l &= mask; | |
629 | return l; | |
ea6dedd7 ID |
630 | } |
631 | ||
a0e827c6 | 632 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 633 | { |
92105bb7 | 634 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
635 | u32 l; |
636 | ||
28f3b5a0 KH |
637 | if (bank->regs->set_irqenable) { |
638 | reg += bank->regs->set_irqenable; | |
639 | l = gpio_mask; | |
2a900eb7 | 640 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
641 | } else { |
642 | reg += bank->regs->irqenable; | |
661553b9 | 643 | l = readl_relaxed(reg); |
28f3b5a0 KH |
644 | if (bank->regs->irqenable_inv) |
645 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
646 | else |
647 | l |= gpio_mask; | |
2a900eb7 | 648 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
649 | } |
650 | ||
661553b9 | 651 | writel_relaxed(l, reg); |
28f3b5a0 KH |
652 | } |
653 | ||
a0e827c6 | 654 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
655 | { |
656 | void __iomem *reg = bank->base; | |
657 | u32 l; | |
658 | ||
659 | if (bank->regs->clr_irqenable) { | |
660 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 661 | l = gpio_mask; |
2a900eb7 | 662 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
663 | } else { |
664 | reg += bank->regs->irqenable; | |
661553b9 | 665 | l = readl_relaxed(reg); |
28f3b5a0 | 666 | if (bank->regs->irqenable_inv) |
56739a69 | 667 | l |= gpio_mask; |
92105bb7 | 668 | else |
28f3b5a0 | 669 | l &= ~gpio_mask; |
2a900eb7 | 670 | bank->context.irqenable1 = l; |
5e1c5ff4 | 671 | } |
28f3b5a0 | 672 | |
661553b9 | 673 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
674 | } |
675 | ||
9943f261 GS |
676 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
677 | unsigned offset, int enable) | |
5e1c5ff4 | 678 | { |
8276536c | 679 | if (enable) |
9943f261 | 680 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 681 | else |
9943f261 | 682 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
683 | } |
684 | ||
92105bb7 | 685 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 686 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 687 | { |
a0e827c6 | 688 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 689 | |
0c0451e7 | 690 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
691 | } |
692 | ||
3ff164e1 | 693 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 694 | { |
d99f7aec | 695 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 696 | unsigned long flags; |
52e31344 | 697 | |
46748073 | 698 | pm_runtime_get_sync(chip->parent); |
92105bb7 | 699 | |
4dbada2b | 700 | raw_spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 701 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 702 | bank->mod_usage |= BIT(offset); |
4dbada2b | 703 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
704 | |
705 | return 0; | |
706 | } | |
707 | ||
3ff164e1 | 708 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 709 | { |
d99f7aec | 710 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 711 | unsigned long flags; |
5e1c5ff4 | 712 | |
4dbada2b | 713 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 714 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
715 | if (!LINE_USED(bank->irq_usage, offset)) { |
716 | omap_set_gpio_direction(bank, offset, 1); | |
717 | omap_clear_gpio_debounce(bank, offset); | |
718 | } | |
a0e827c6 | 719 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 720 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 721 | |
46748073 | 722 | pm_runtime_put(chip->parent); |
5e1c5ff4 TL |
723 | } |
724 | ||
725 | /* | |
726 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
727 | * avoid missing GPIO interrupts for other lines in the bank. | |
728 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
729 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
730 | * If we wait to unmask individual GPIO lines in the bank after the | |
731 | * line's interrupt handler has been run, we may miss some nested | |
732 | * interrupts. | |
733 | */ | |
450fa54c | 734 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 735 | { |
92105bb7 | 736 | void __iomem *isr_reg = NULL; |
80ac93c2 | 737 | u32 enabled, isr, level_mask; |
3513cdec | 738 | unsigned int bit; |
450fa54c GS |
739 | struct gpio_bank *bank = gpiobank; |
740 | unsigned long wa_lock_flags; | |
235f1eb1 | 741 | unsigned long lock_flags; |
5e1c5ff4 | 742 | |
eef4bec7 | 743 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
744 | if (WARN_ON(!isr_reg)) |
745 | goto exit; | |
746 | ||
5284521a TL |
747 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
748 | "gpio irq%i while runtime suspended?\n", irq)) | |
749 | return IRQ_NONE; | |
450fa54c | 750 | |
e83507b7 | 751 | while (1) { |
235f1eb1 GS |
752 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
753 | ||
a0e827c6 | 754 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 755 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 756 | |
9ea14d8c | 757 | if (bank->level_mask) |
b144ff6f | 758 | level_mask = bank->level_mask & enabled; |
80ac93c2 GS |
759 | else |
760 | level_mask = 0; | |
6e60e79a TL |
761 | |
762 | /* clear edge sensitive interrupts before handler(s) are | |
763 | called so that we don't miss any interrupt occurred while | |
764 | executing them */ | |
80ac93c2 GS |
765 | if (isr & ~level_mask) |
766 | omap_clear_gpio_irqbank(bank, isr & ~level_mask); | |
6e60e79a | 767 | |
235f1eb1 GS |
768 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
769 | ||
92105bb7 TL |
770 | if (!isr) |
771 | break; | |
772 | ||
3513cdec JH |
773 | while (isr) { |
774 | bit = __ffs(isr); | |
b1e9fec2 | 775 | isr &= ~(BIT(bit)); |
25db711d | 776 | |
235f1eb1 | 777 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
778 | /* |
779 | * Some chips can't respond to both rising and falling | |
780 | * at the same time. If this irq was requested with | |
781 | * both flags, we need to flip the ICR data for the IRQ | |
782 | * to respond to the IRQ for the opposite direction. | |
783 | * This will be indicated in the bank toggle_mask. | |
784 | */ | |
b1e9fec2 | 785 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 786 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 787 | |
235f1eb1 GS |
788 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
789 | ||
450fa54c GS |
790 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
791 | ||
f0fbe7bc | 792 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 793 | bit)); |
450fa54c GS |
794 | |
795 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
796 | wa_lock_flags); | |
92105bb7 | 797 | } |
1a8bfa1e | 798 | } |
b1cc4c55 | 799 | exit: |
450fa54c | 800 | return IRQ_HANDLED; |
5e1c5ff4 TL |
801 | } |
802 | ||
3d009c8c TL |
803 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
804 | { | |
805 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 806 | unsigned long flags; |
37e14ecf | 807 | unsigned offset = d->hwirq; |
3d009c8c | 808 | |
4dbada2b | 809 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
810 | |
811 | if (!LINE_USED(bank->mod_usage, offset)) | |
812 | omap_set_gpio_direction(bank, offset, 1); | |
813 | else if (!omap_gpio_is_input(bank, offset)) | |
814 | goto err; | |
815 | omap_enable_gpio_module(bank, offset); | |
816 | bank->irq_usage |= BIT(offset); | |
817 | ||
4dbada2b | 818 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
819 | omap_gpio_unmask_irq(d); |
820 | ||
821 | return 0; | |
121dcb76 | 822 | err: |
4dbada2b | 823 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 824 | return -EINVAL; |
3d009c8c TL |
825 | } |
826 | ||
a0e827c6 | 827 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 828 | { |
a0e827c6 | 829 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 830 | unsigned long flags; |
9943f261 | 831 | unsigned offset = d->hwirq; |
4196dd6b | 832 | |
4dbada2b | 833 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 834 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
835 | omap_set_gpio_irqenable(bank, offset, 0); |
836 | omap_clear_gpio_irqstatus(bank, offset); | |
837 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
838 | if (!LINE_USED(bank->mod_usage, offset)) | |
839 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 840 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 841 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
842 | } |
843 | ||
844 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
845 | { | |
846 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
847 | ||
46748073 | 848 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
849 | } |
850 | ||
851 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
852 | { | |
853 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 854 | |
46748073 | 855 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
856 | } |
857 | ||
a0e827c6 | 858 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 859 | { |
a0e827c6 | 860 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 861 | unsigned offset = d->hwirq; |
5e1c5ff4 | 862 | |
9943f261 | 863 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
864 | } |
865 | ||
a0e827c6 | 866 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 867 | { |
a0e827c6 | 868 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 869 | unsigned offset = d->hwirq; |
85ec7b97 | 870 | unsigned long flags; |
5e1c5ff4 | 871 | |
4dbada2b | 872 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
873 | omap_set_gpio_irqenable(bank, offset, 0); |
874 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
4dbada2b | 875 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
876 | } |
877 | ||
a0e827c6 | 878 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 879 | { |
a0e827c6 | 880 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 881 | unsigned offset = d->hwirq; |
8c04a176 | 882 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 883 | unsigned long flags; |
55b6019a | 884 | |
4dbada2b | 885 | raw_spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 886 | if (trigger) |
9943f261 | 887 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f | 888 | |
d01849f7 RK |
889 | omap_set_gpio_irqenable(bank, offset, 1); |
890 | ||
891 | /* | |
892 | * For level-triggered GPIOs, clearing must be done after the source | |
893 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
894 | * after enabing the interrupt to clear the wakeup status. | |
895 | */ | |
896 | if (bank->level_mask & BIT(offset)) | |
9943f261 | 897 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 898 | |
4dbada2b | 899 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
900 | } |
901 | ||
e5c56ed3 DB |
902 | /*---------------------------------------------------------------------*/ |
903 | ||
79ee031f | 904 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 905 | { |
a3f4f728 | 906 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
907 | void __iomem *mask_reg = bank->base + |
908 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 909 | unsigned long flags; |
11a78b79 | 910 | |
4dbada2b | 911 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 912 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 913 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
914 | |
915 | return 0; | |
916 | } | |
917 | ||
79ee031f | 918 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 919 | { |
a3f4f728 | 920 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
921 | void __iomem *mask_reg = bank->base + |
922 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 923 | unsigned long flags; |
11a78b79 | 924 | |
4dbada2b | 925 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 926 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 927 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
928 | |
929 | return 0; | |
930 | } | |
931 | ||
47145210 | 932 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
933 | .suspend_noirq = omap_mpuio_suspend_noirq, |
934 | .resume_noirq = omap_mpuio_resume_noirq, | |
935 | }; | |
936 | ||
3c437ffd | 937 | /* use platform_driver for this. */ |
11a78b79 | 938 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
939 | .driver = { |
940 | .name = "mpuio", | |
79ee031f | 941 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
942 | }, |
943 | }; | |
944 | ||
945 | static struct platform_device omap_mpuio_device = { | |
946 | .name = "mpuio", | |
947 | .id = -1, | |
948 | .dev = { | |
949 | .driver = &omap_mpuio_driver.driver, | |
950 | } | |
951 | /* could list the /proc/iomem resources */ | |
952 | }; | |
953 | ||
a0e827c6 | 954 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 955 | { |
77640aab | 956 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 957 | |
11a78b79 DB |
958 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
959 | (void) platform_device_register(&omap_mpuio_device); | |
960 | } | |
961 | ||
e5c56ed3 | 962 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 963 | |
a0e827c6 | 964 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
965 | { |
966 | struct gpio_bank *bank; | |
967 | unsigned long flags; | |
968 | void __iomem *reg; | |
969 | int dir; | |
970 | ||
d99f7aec | 971 | bank = gpiochip_get_data(chip); |
9370084e | 972 | reg = bank->base + bank->regs->direction; |
4dbada2b | 973 | raw_spin_lock_irqsave(&bank->lock, flags); |
9370084e | 974 | dir = !!(readl_relaxed(reg) & BIT(offset)); |
4dbada2b | 975 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
9370084e YY |
976 | return dir; |
977 | } | |
978 | ||
a0e827c6 | 979 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
980 | { |
981 | struct gpio_bank *bank; | |
982 | unsigned long flags; | |
983 | ||
d99f7aec | 984 | bank = gpiochip_get_data(chip); |
4dbada2b | 985 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 986 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 987 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
988 | return 0; |
989 | } | |
990 | ||
a0e827c6 | 991 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 992 | { |
b37c45b8 | 993 | struct gpio_bank *bank; |
b37c45b8 | 994 | |
d99f7aec | 995 | bank = gpiochip_get_data(chip); |
b37c45b8 | 996 | |
b2b20045 | 997 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 998 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 999 | else |
a0e827c6 | 1000 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
1001 | } |
1002 | ||
a0e827c6 | 1003 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1004 | { |
1005 | struct gpio_bank *bank; | |
1006 | unsigned long flags; | |
1007 | ||
d99f7aec | 1008 | bank = gpiochip_get_data(chip); |
4dbada2b | 1009 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1010 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 1011 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 1012 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 1013 | return 0; |
52e31344 DB |
1014 | } |
1015 | ||
442af140 JK |
1016 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
1017 | unsigned long *bits) | |
1018 | { | |
1019 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1020 | void __iomem *reg = bank->base + bank->regs->direction; | |
1021 | unsigned long in = readl_relaxed(reg), l; | |
1022 | ||
1023 | *bits = 0; | |
1024 | ||
1025 | l = in & *mask; | |
1026 | if (l) | |
1027 | *bits |= omap_get_gpio_datain_multiple(bank, &l); | |
1028 | ||
1029 | l = ~in & *mask; | |
1030 | if (l) | |
1031 | *bits |= omap_get_gpio_dataout_multiple(bank, &l); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
a0e827c6 JMC |
1036 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1037 | unsigned debounce) | |
168ef3d9 FB |
1038 | { |
1039 | struct gpio_bank *bank; | |
1040 | unsigned long flags; | |
83977443 | 1041 | int ret; |
168ef3d9 | 1042 | |
d99f7aec | 1043 | bank = gpiochip_get_data(chip); |
77640aab | 1044 | |
4dbada2b | 1045 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 1046 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 1047 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 1048 | |
83977443 DR |
1049 | if (ret) |
1050 | dev_info(chip->parent, | |
1051 | "Could not set line %u debounce to %u microseconds (%d)", | |
1052 | offset, debounce, ret); | |
1053 | ||
1054 | return ret; | |
168ef3d9 FB |
1055 | } |
1056 | ||
2956b5d9 MW |
1057 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
1058 | unsigned long config) | |
1059 | { | |
1060 | u32 debounce; | |
1061 | ||
1062 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
1063 | return -ENOTSUPP; | |
1064 | ||
1065 | debounce = pinconf_to_config_argument(config); | |
1066 | return omap_gpio_debounce(chip, offset, debounce); | |
1067 | } | |
1068 | ||
a0e827c6 | 1069 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1070 | { |
1071 | struct gpio_bank *bank; | |
1072 | unsigned long flags; | |
1073 | ||
d99f7aec | 1074 | bank = gpiochip_get_data(chip); |
4dbada2b | 1075 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1076 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1077 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1078 | } |
1079 | ||
442af140 JK |
1080 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
1081 | unsigned long *bits) | |
1082 | { | |
1083 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1084 | unsigned long flags; | |
1085 | ||
1086 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1087 | bank->set_dataout_multiple(bank, mask, bits); | |
1088 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1089 | } | |
1090 | ||
52e31344 DB |
1091 | /*---------------------------------------------------------------------*/ |
1092 | ||
e4b2ae7a | 1093 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1094 | { |
e5ff4440 | 1095 | static bool called; |
9f7065da TL |
1096 | u32 rev; |
1097 | ||
e5ff4440 | 1098 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1099 | return; |
1100 | ||
661553b9 | 1101 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1102 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1103 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1104 | |
1105 | called = true; | |
9f7065da TL |
1106 | } |
1107 | ||
03e128ca | 1108 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1109 | { |
ab985f0f TKD |
1110 | void __iomem *base = bank->base; |
1111 | u32 l = 0xffffffff; | |
2fae7fbe | 1112 | |
ab985f0f TKD |
1113 | if (bank->width == 16) |
1114 | l = 0xffff; | |
1115 | ||
d0d665a8 | 1116 | if (bank->is_mpuio) { |
661553b9 | 1117 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1118 | return; |
2fae7fbe | 1119 | } |
ab985f0f | 1120 | |
a0e827c6 JMC |
1121 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1122 | bank->regs->irqenable_inv); | |
1123 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1124 | !bank->regs->irqenable_inv); | |
ab985f0f | 1125 | if (bank->regs->debounce_en) |
661553b9 | 1126 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1127 | |
2dc983c5 | 1128 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1129 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1130 | /* Initialize interface clk ungated, module enabled */ |
1131 | if (bank->regs->ctrl) | |
661553b9 | 1132 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1133 | } |
1134 | ||
46824e22 | 1135 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1136 | { |
81930328 | 1137 | struct gpio_irq_chip *irq; |
2fae7fbe | 1138 | static int gpio; |
088413bc | 1139 | const char *label; |
fb655f57 | 1140 | int irq_base = 0; |
6ef7f385 | 1141 | int ret; |
2fae7fbe | 1142 | |
2fae7fbe VC |
1143 | /* |
1144 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1145 | * over to the generic ones | |
1146 | */ | |
1147 | bank->chip.request = omap_gpio_request; | |
1148 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1149 | bank->chip.get_direction = omap_gpio_get_direction; |
1150 | bank->chip.direction_input = omap_gpio_input; | |
1151 | bank->chip.get = omap_gpio_get; | |
442af140 | 1152 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1153 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1154 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1155 | bank->chip.set = omap_gpio_set; |
442af140 | 1156 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1157 | if (bank->is_mpuio) { |
2fae7fbe | 1158 | bank->chip.label = "mpuio"; |
6ed87c5b | 1159 | if (bank->regs->wkup_en) |
58383c78 | 1160 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1161 | bank->chip.base = OMAP_MPUIO(0); |
1162 | } else { | |
088413bc LW |
1163 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1164 | gpio, gpio + bank->width - 1); | |
1165 | if (!label) | |
1166 | return -ENOMEM; | |
1167 | bank->chip.label = label; | |
2fae7fbe | 1168 | bank->chip.base = gpio; |
2fae7fbe | 1169 | } |
d5f46247 | 1170 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1171 | |
fb655f57 JMC |
1172 | #ifdef CONFIG_ARCH_OMAP1 |
1173 | /* | |
1174 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1175 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1176 | */ | |
2ed36f30 BG |
1177 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1178 | -1, 0, bank->width, 0); | |
fb655f57 | 1179 | if (irq_base < 0) { |
7b1e5dc8 | 1180 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1181 | return -ENODEV; |
1182 | } | |
1183 | #endif | |
1184 | ||
d2d05c65 TL |
1185 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1186 | if (bank->is_mpuio) { | |
1187 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
d2d05c65 TL |
1188 | if (!bank->regs->wkup_en) |
1189 | irqc->irq_set_wake = NULL; | |
1190 | } | |
1191 | ||
81930328 GS |
1192 | irq = &bank->chip.irq; |
1193 | irq->chip = irqc; | |
1194 | irq->handler = handle_bad_irq; | |
1195 | irq->default_type = IRQ_TYPE_NONE; | |
1196 | irq->num_parents = 1; | |
1197 | irq->parents = &bank->irq; | |
1198 | irq->first = irq_base; | |
fb655f57 | 1199 | |
81930328 | 1200 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1201 | if (ret) { |
7b1e5dc8 | 1202 | dev_err(bank->chip.parent, |
81930328 GS |
1203 | "Could not register gpio chip %d\n", ret); |
1204 | return ret; | |
fb655f57 JMC |
1205 | } |
1206 | ||
7b1e5dc8 GS |
1207 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1208 | omap_gpio_irq_handler, | |
1209 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1210 | if (ret) |
1211 | gpiochip_remove(&bank->chip); | |
1212 | ||
81930328 GS |
1213 | if (!bank->is_mpuio) |
1214 | gpio += bank->width; | |
1215 | ||
450fa54c | 1216 | return ret; |
2fae7fbe VC |
1217 | } |
1218 | ||
7c68571f | 1219 | static void omap_gpio_init_context(struct gpio_bank *p) |
b764a586 | 1220 | { |
7c68571f AB |
1221 | struct omap_gpio_reg_offs *regs = p->regs; |
1222 | void __iomem *base = p->base; | |
b764a586 | 1223 | |
7c68571f AB |
1224 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1225 | p->context.oe = readl_relaxed(base + regs->direction); | |
1226 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1227 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1228 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1229 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1230 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1231 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1232 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
b764a586 | 1233 | |
7c68571f AB |
1234 | if (regs->set_dataout && p->regs->clr_dataout) |
1235 | p->context.dataout = readl_relaxed(base + regs->set_dataout); | |
1236 | else | |
1237 | p->context.dataout = readl_relaxed(base + regs->dataout); | |
b764a586 | 1238 | |
7c68571f | 1239 | p->context_valid = true; |
b764a586 TL |
1240 | } |
1241 | ||
7c68571f | 1242 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
5e1c5ff4 | 1243 | { |
7c68571f AB |
1244 | writel_relaxed(bank->context.wake_en, |
1245 | bank->base + bank->regs->wkup_en); | |
1246 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1247 | writel_relaxed(bank->context.leveldetect0, | |
1248 | bank->base + bank->regs->leveldetect0); | |
1249 | writel_relaxed(bank->context.leveldetect1, | |
1250 | bank->base + bank->regs->leveldetect1); | |
1251 | writel_relaxed(bank->context.risingdetect, | |
1252 | bank->base + bank->regs->risingdetect); | |
1253 | writel_relaxed(bank->context.fallingdetect, | |
1254 | bank->base + bank->regs->fallingdetect); | |
1255 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1256 | writel_relaxed(bank->context.dataout, | |
1257 | bank->base + bank->regs->set_dataout); | |
1258 | else | |
1259 | writel_relaxed(bank->context.dataout, | |
1260 | bank->base + bank->regs->dataout); | |
1261 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); | |
9f7065da | 1262 | |
7c68571f AB |
1263 | if (bank->dbck_enable_mask) { |
1264 | writel_relaxed(bank->context.debounce, bank->base + | |
1265 | bank->regs->debounce); | |
1266 | writel_relaxed(bank->context.debounce_en, | |
1267 | bank->base + bank->regs->debounce_en); | |
b764a586 TL |
1268 | } |
1269 | ||
7c68571f AB |
1270 | writel_relaxed(bank->context.irqenable1, |
1271 | bank->base + bank->regs->irqenable); | |
1272 | writel_relaxed(bank->context.irqenable2, | |
1273 | bank->base + bank->regs->irqenable2); | |
cac089f9 TL |
1274 | } |
1275 | ||
b764a586 | 1276 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1277 | { |
b764a586 | 1278 | struct device *dev = bank->chip.parent; |
21e2118f TL |
1279 | void __iomem *base = bank->base; |
1280 | u32 nowake; | |
1281 | ||
1282 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1283 | |
b3c64bc3 KH |
1284 | if (!bank->enabled_non_wakeup_gpios) |
1285 | goto update_gpio_context_count; | |
1286 | ||
b764a586 | 1287 | if (!may_lose_context) |
41d87cbd | 1288 | goto update_gpio_context_count; |
b764a586 | 1289 | |
2dc983c5 | 1290 | /* |
21e2118f | 1291 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1292 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1293 | * generated. See OMAP2420 Errata item 1.101. | |
1294 | */ | |
21e2118f TL |
1295 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1296 | nowake = bank->enabled_non_wakeup_gpios; | |
1297 | omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake); | |
1298 | omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake); | |
1299 | } | |
3f1686a9 | 1300 | |
41d87cbd | 1301 | update_gpio_context_count: |
2dc983c5 TKD |
1302 | if (bank->get_context_loss_count) |
1303 | bank->context_loss_count = | |
7b1e5dc8 | 1304 | bank->get_context_loss_count(dev); |
60a3437d | 1305 | |
a0e827c6 | 1306 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1307 | } |
1308 | ||
b764a586 | 1309 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1310 | { |
b764a586 | 1311 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1312 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1313 | int c; |
8865b9b6 | 1314 | |
352a2d5b JH |
1315 | /* |
1316 | * On the first resume during the probe, the context has not | |
1317 | * been initialised and so initialise it now. Also initialise | |
1318 | * the context loss count. | |
1319 | */ | |
1320 | if (bank->loses_context && !bank->context_valid) { | |
1321 | omap_gpio_init_context(bank); | |
1322 | ||
1323 | if (bank->get_context_loss_count) | |
1324 | bank->context_loss_count = | |
7b1e5dc8 | 1325 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1326 | } |
1327 | ||
a0e827c6 | 1328 | omap_gpio_dbck_enable(bank); |
68942edb | 1329 | |
a2797bea JH |
1330 | if (bank->loses_context) { |
1331 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1332 | omap_gpio_restore_context(bank); |
1333 | } else { | |
7b1e5dc8 | 1334 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1335 | if (c != bank->context_loss_count) { |
1336 | omap_gpio_restore_context(bank); | |
1337 | } else { | |
b764a586 | 1338 | return; |
a2797bea | 1339 | } |
60a3437d | 1340 | } |
21e2118f TL |
1341 | } else { |
1342 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1343 | writel_relaxed(bank->context.fallingdetect, | |
1344 | bank->base + bank->regs->fallingdetect); | |
1345 | writel_relaxed(bank->context.risingdetect, | |
1346 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1347 | } |
43ffcd9a | 1348 | |
661553b9 | 1349 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1350 | |
2dc983c5 TKD |
1351 | /* |
1352 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1353 | * state. If so, generate an IRQ by software. This is | |
1354 | * horribly racy, but it's the best we can do to work around | |
1355 | * this silicon bug. | |
1356 | */ | |
1357 | l ^= bank->saved_datain; | |
1358 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1359 | |
2dc983c5 TKD |
1360 | /* |
1361 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1362 | * configured with falling edge only; and vice versa. | |
1363 | */ | |
c6f31c9e | 1364 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1365 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1366 | |
c6f31c9e | 1367 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1368 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1369 | |
2dc983c5 | 1370 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1371 | gen = l & (~(bank->context.fallingdetect) & |
1372 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1373 | /* Consider all GPIO IRQs needed to be updated */ |
1374 | gen |= gen0 | gen1; | |
82dbb9d3 | 1375 | |
2dc983c5 TKD |
1376 | if (gen) { |
1377 | u32 old0, old1; | |
82dbb9d3 | 1378 | |
661553b9 VK |
1379 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1380 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1381 | |
4e962e89 | 1382 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1383 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1384 | bank->regs->leveldetect0); |
661553b9 | 1385 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1386 | bank->regs->leveldetect1); |
2dc983c5 | 1387 | } |
9ea14d8c | 1388 | |
4e962e89 | 1389 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1390 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1391 | bank->regs->leveldetect0); |
661553b9 | 1392 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1393 | bank->regs->leveldetect1); |
3ac4fa99 | 1394 | } |
661553b9 VK |
1395 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1396 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1397 | } |
2dc983c5 | 1398 | } |
2dc983c5 | 1399 | |
7c68571f AB |
1400 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, |
1401 | unsigned long cmd, void *v) | |
352a2d5b | 1402 | { |
7c68571f AB |
1403 | struct gpio_bank *bank; |
1404 | unsigned long flags; | |
352a2d5b | 1405 | |
7c68571f | 1406 | bank = container_of(nb, struct gpio_bank, nb); |
352a2d5b | 1407 | |
7c68571f AB |
1408 | raw_spin_lock_irqsave(&bank->lock, flags); |
1409 | switch (cmd) { | |
1410 | case CPU_CLUSTER_PM_ENTER: | |
1411 | if (bank->is_suspended) | |
1412 | break; | |
1413 | omap_gpio_idle(bank, true); | |
1414 | break; | |
1415 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1416 | case CPU_CLUSTER_PM_EXIT: | |
1417 | if (bank->is_suspended) | |
1418 | break; | |
1419 | omap_gpio_unidle(bank); | |
1420 | break; | |
1421 | } | |
1422 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
352a2d5b | 1423 | |
7c68571f | 1424 | return NOTIFY_OK; |
b764a586 TL |
1425 | } |
1426 | ||
384ebe1c BC |
1427 | static struct omap_gpio_reg_offs omap2_gpio_regs = { |
1428 | .revision = OMAP24XX_GPIO_REVISION, | |
1429 | .direction = OMAP24XX_GPIO_OE, | |
1430 | .datain = OMAP24XX_GPIO_DATAIN, | |
1431 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1432 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1433 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1434 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1435 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1436 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1437 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1438 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1439 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1440 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1441 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1442 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1443 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1444 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1445 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1446 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1447 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1448 | }; | |
1449 | ||
1450 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1451 | .revision = OMAP4_GPIO_REVISION, | |
1452 | .direction = OMAP4_GPIO_OE, | |
1453 | .datain = OMAP4_GPIO_DATAIN, | |
1454 | .dataout = OMAP4_GPIO_DATAOUT, | |
1455 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1456 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1457 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1458 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1459 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1460 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1461 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1462 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1463 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1464 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1465 | .ctrl = OMAP4_GPIO_CTRL, | |
1466 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1467 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1468 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1469 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1470 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1471 | }; | |
1472 | ||
e9a65bb6 | 1473 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1474 | .regs = &omap2_gpio_regs, |
1475 | .bank_width = 32, | |
1476 | .dbck_flag = false, | |
1477 | }; | |
1478 | ||
e9a65bb6 | 1479 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1480 | .regs = &omap2_gpio_regs, |
1481 | .bank_width = 32, | |
1482 | .dbck_flag = true, | |
1483 | }; | |
1484 | ||
e9a65bb6 | 1485 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1486 | .regs = &omap4_gpio_regs, |
1487 | .bank_width = 32, | |
1488 | .dbck_flag = true, | |
1489 | }; | |
1490 | ||
1491 | static const struct of_device_id omap_gpio_match[] = { | |
1492 | { | |
1493 | .compatible = "ti,omap4-gpio", | |
1494 | .data = &omap4_pdata, | |
1495 | }, | |
1496 | { | |
1497 | .compatible = "ti,omap3-gpio", | |
1498 | .data = &omap3_pdata, | |
1499 | }, | |
1500 | { | |
1501 | .compatible = "ti,omap2-gpio", | |
1502 | .data = &omap2_pdata, | |
1503 | }, | |
1504 | { }, | |
1505 | }; | |
1506 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
7c68571f AB |
1507 | |
1508 | static int omap_gpio_probe(struct platform_device *pdev) | |
1509 | { | |
1510 | struct device *dev = &pdev->dev; | |
1511 | struct device_node *node = dev->of_node; | |
1512 | const struct of_device_id *match; | |
1513 | const struct omap_gpio_platform_data *pdata; | |
7c68571f AB |
1514 | struct gpio_bank *bank; |
1515 | struct irq_chip *irqc; | |
1516 | int ret; | |
1517 | ||
1518 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); | |
1519 | ||
1520 | pdata = match ? match->data : dev_get_platdata(dev); | |
1521 | if (!pdata) | |
1522 | return -EINVAL; | |
1523 | ||
1524 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
1525 | if (!bank) | |
1526 | return -ENOMEM; | |
1527 | ||
1528 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); | |
1529 | if (!irqc) | |
1530 | return -ENOMEM; | |
1531 | ||
1532 | irqc->irq_startup = omap_gpio_irq_startup, | |
1533 | irqc->irq_shutdown = omap_gpio_irq_shutdown, | |
1534 | irqc->irq_ack = omap_gpio_ack_irq, | |
1535 | irqc->irq_mask = omap_gpio_mask_irq, | |
1536 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1537 | irqc->irq_set_type = omap_gpio_irq_type, | |
1538 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1539 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, | |
1540 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
1541 | irqc->name = dev_name(&pdev->dev); | |
1542 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1543 | irqc->parent_device = dev; | |
1544 | ||
1545 | bank->irq = platform_get_irq(pdev, 0); | |
1546 | if (bank->irq <= 0) { | |
1547 | if (!bank->irq) | |
1548 | bank->irq = -ENXIO; | |
1549 | if (bank->irq != -EPROBE_DEFER) | |
1550 | dev_err(dev, | |
1551 | "can't get irq resource ret=%d\n", bank->irq); | |
1552 | return bank->irq; | |
1553 | } | |
1554 | ||
1555 | bank->chip.parent = dev; | |
1556 | bank->chip.owner = THIS_MODULE; | |
1557 | bank->dbck_flag = pdata->dbck_flag; | |
7c68571f AB |
1558 | bank->stride = pdata->bank_stride; |
1559 | bank->width = pdata->bank_width; | |
1560 | bank->is_mpuio = pdata->is_mpuio; | |
1561 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; | |
1562 | bank->regs = pdata->regs; | |
1563 | #ifdef CONFIG_OF_GPIO | |
1564 | bank->chip.of_node = of_node_get(node); | |
384ebe1c BC |
1565 | #endif |
1566 | ||
7c68571f AB |
1567 | if (node) { |
1568 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1569 | bank->loses_context = true; | |
1570 | } else { | |
1571 | bank->loses_context = pdata->loses_context; | |
1572 | ||
1573 | if (bank->loses_context) | |
1574 | bank->get_context_loss_count = | |
1575 | pdata->get_context_loss_count; | |
1576 | } | |
1577 | ||
1578 | if (bank->regs->set_dataout && bank->regs->clr_dataout) { | |
1579 | bank->set_dataout = omap_set_gpio_dataout_reg; | |
1580 | bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; | |
1581 | } else { | |
1582 | bank->set_dataout = omap_set_gpio_dataout_mask; | |
1583 | bank->set_dataout_multiple = | |
1584 | omap_set_gpio_dataout_mask_multiple; | |
1585 | } | |
1586 | ||
7c68571f AB |
1587 | raw_spin_lock_init(&bank->lock); |
1588 | raw_spin_lock_init(&bank->wa_lock); | |
1589 | ||
1590 | /* Static mapping, never released */ | |
58f57f86 | 1591 | bank->base = devm_platform_ioremap_resource(pdev, 0); |
7c68571f AB |
1592 | if (IS_ERR(bank->base)) { |
1593 | return PTR_ERR(bank->base); | |
1594 | } | |
1595 | ||
1596 | if (bank->dbck_flag) { | |
1597 | bank->dbck = devm_clk_get(dev, "dbclk"); | |
1598 | if (IS_ERR(bank->dbck)) { | |
1599 | dev_err(dev, | |
1600 | "Could not get gpio dbck. Disable debounce\n"); | |
1601 | bank->dbck_flag = false; | |
1602 | } else { | |
1603 | clk_prepare(bank->dbck); | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | platform_set_drvdata(pdev, bank); | |
1608 | ||
1609 | pm_runtime_enable(dev); | |
1610 | pm_runtime_get_sync(dev); | |
1611 | ||
1612 | if (bank->is_mpuio) | |
1613 | omap_mpuio_init(bank); | |
1614 | ||
1615 | omap_gpio_mod_init(bank); | |
1616 | ||
1617 | ret = omap_gpio_chip_init(bank, irqc); | |
1618 | if (ret) { | |
1619 | pm_runtime_put_sync(dev); | |
1620 | pm_runtime_disable(dev); | |
1621 | if (bank->dbck_flag) | |
1622 | clk_unprepare(bank->dbck); | |
1623 | return ret; | |
1624 | } | |
1625 | ||
1626 | omap_gpio_show_rev(bank); | |
1627 | ||
e6818d29 RK |
1628 | bank->nb.notifier_call = gpio_omap_cpu_notifier; |
1629 | cpu_pm_register_notifier(&bank->nb); | |
7c68571f AB |
1630 | |
1631 | pm_runtime_put(dev); | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static int omap_gpio_remove(struct platform_device *pdev) | |
1637 | { | |
1638 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1639 | ||
e6818d29 | 1640 | cpu_pm_unregister_notifier(&bank->nb); |
7c68571f AB |
1641 | list_del(&bank->node); |
1642 | gpiochip_remove(&bank->chip); | |
1643 | pm_runtime_disable(&pdev->dev); | |
1644 | if (bank->dbck_flag) | |
1645 | clk_unprepare(bank->dbck); | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
1650 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) | |
1651 | { | |
1652 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1653 | unsigned long flags; | |
7c68571f AB |
1654 | |
1655 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1656 | omap_gpio_idle(bank, true); |
1657 | bank->is_suspended = true; | |
7c68571f AB |
1658 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1659 | ||
044e499a | 1660 | return 0; |
7c68571f AB |
1661 | } |
1662 | ||
1663 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1664 | { | |
1665 | struct gpio_bank *bank = dev_get_drvdata(dev); | |
1666 | unsigned long flags; | |
7c68571f AB |
1667 | |
1668 | raw_spin_lock_irqsave(&bank->lock, flags); | |
7c68571f AB |
1669 | omap_gpio_unidle(bank); |
1670 | bank->is_suspended = false; | |
7c68571f AB |
1671 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1672 | ||
044e499a | 1673 | return 0; |
7c68571f AB |
1674 | } |
1675 | ||
1676 | static const struct dev_pm_ops gpio_pm_ops = { | |
1677 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, | |
1678 | NULL) | |
1679 | }; | |
1680 | ||
77640aab VC |
1681 | static struct platform_driver omap_gpio_driver = { |
1682 | .probe = omap_gpio_probe, | |
cac089f9 | 1683 | .remove = omap_gpio_remove, |
77640aab VC |
1684 | .driver = { |
1685 | .name = "omap_gpio", | |
55b93c32 | 1686 | .pm = &gpio_pm_ops, |
7c68571f | 1687 | .of_match_table = omap_gpio_match, |
77640aab VC |
1688 | }, |
1689 | }; | |
1690 | ||
5e1c5ff4 | 1691 | /* |
77640aab VC |
1692 | * gpio driver register needs to be done before |
1693 | * machine_init functions access gpio APIs. | |
1694 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1695 | */ |
77640aab | 1696 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1697 | { |
77640aab | 1698 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1699 | } |
77640aab | 1700 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1701 | |
1702 | static void __exit omap_gpio_exit(void) | |
1703 | { | |
1704 | platform_driver_unregister(&omap_gpio_driver); | |
1705 | } | |
1706 | module_exit(omap_gpio_exit); | |
1707 | ||
1708 | MODULE_DESCRIPTION("omap gpio driver"); | |
1709 | MODULE_ALIAS("platform:gpio-omap"); | |
1710 | MODULE_LICENSE("GPL v2"); |