[linux-2.6-block.git] / drivers / gpio / gpio-mxs.c

// SPDX-License-Identifier: GPL-2.0+
//
// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
//
// Based on code from Freescale,
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
#define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
#define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
#define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
#define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
#define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
#define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
#define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

enum mxs_gpio_id {
	IMX23_GPIO,
	IMX28_GPIO,
};

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	struct irq_domain *domain;
	struct gpio_chip gc;
	struct device *dev;
	enum mxs_gpio_id devid;
	u32 both_edges;
};

static inline int is_imx23_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX23_GPIO;
}

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 val;
	u32 pin_mask = 1 << d->hwirq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct mxs_gpio_port *port = gc->private;
	void __iomem *pin_addr;
	int edge;

	if (!(ct->type & type))
		if (irq_setup_alt_chip(d, type))
			return -EINVAL;

	port->both_edges &= ~pin_mask;
	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
		if (val)
			edge = GPIO_INT_FALL_EDGE;
		else
			edge = GPIO_INT_RISE_EDGE;
		port->both_edges |= pin_mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port);
	if (edge & GPIO_INT_LEV_MASK) {
		writel(pin_mask, pin_addr + MXS_SET);
		writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
	} else {
		writel(pin_mask, pin_addr + MXS_CLR);
		writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
	}

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	return 0;
}

static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
{
	u32 bit, val, edge;
	void __iomem *pin_addr;

	bit = 1 << gpio;

	pin_addr = port->base + PINCTRL_IRQPOL(port);
	val = readl(pin_addr);
	edge = val & bit;

	if (edge)
		writel(bit, pin_addr + MXS_CLR);
	else
		writel(bit, pin_addr + MXS_SET);
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
			readl(port->base + PINCTRL_IRQEN(port));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		if (port->both_edges & (1 << irqoffset))
			mxs_flip_edge(port, irqoffset);

		generic_handle_domain_irq(port->domain, irqoffset);
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
					 port->base, handle_level_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = port;

	ct = &gc->chip_types[0];
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;

	ct = &gc->chip_types[1];
	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
	ct->handler = handle_level_irq;

	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
					 IRQ_GC_INIT_NESTED_LOCK,
					 IRQ_NOREQUEST, 0);

	return rv;
}

static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
{
	struct mxs_gpio_port *port = gpiochip_get_data(gc);

	return irq_find_mapping(port->domain, offset);
}

static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
	struct mxs_gpio_port *port = gpiochip_get_data(gc);
	u32 mask = 1 << offset;
	u32 dir;

	dir = readl(port->base + PINCTRL_DOE(port));
	if (dir & mask)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static const struct of_device_id mxs_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);

static int mxs_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *parent;
	static void __iomem *base;
	struct mxs_gpio_port *port;
	int irq_base;
	int err;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->id = of_alias_get_id(np, "gpio");
	if (port->id < 0)
		return port->id;
	port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
	port->dev = &pdev->dev;
	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		parent = of_get_parent(np);
		base = of_iomap(parent, 0);
		of_node_put(parent);
		if (!base)
			return -EADDRNOTAVAIL;
	}
	port->base = base;

	/* initially disable the interrupts */
	writel(0, port->base + PINCTRL_PIN2IRQ(port));
	writel(0, port->base + PINCTRL_IRQEN(port));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
	if (irq_base < 0) {
		err = irq_base;
		goto out_iounmap;
	}

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_iounmap;
	}

	/* gpio-mxs can be a generic irq chip */
	err = mxs_gpio_init_gc(port, irq_base);
	if (err < 0)
		goto out_irqdomain_remove;

	/* setup one handler for each entry */
	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
					 port);

	err = bgpio_init(&port->gc, &pdev->dev, 4,
			 port->base + PINCTRL_DIN(port),
			 port->base + PINCTRL_DOUT(port) + MXS_SET,
			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
			 port->base + PINCTRL_DOE(port), NULL, 0);
	if (err)
		goto out_irqdomain_remove;

	port->gc.to_irq = mxs_gpio_to_irq;
	port->gc.get_direction = mxs_gpio_get_direction;
	port->gc.base = port->id * 32;

	err = gpiochip_add_data(&port->gc, port);
	if (err)
		goto out_irqdomain_remove;

	return 0;

out_irqdomain_remove:
	irq_domain_remove(port->domain);
out_iounmap:
	iounmap(port->base);
	return err;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.of_match_table = mxs_gpio_dt_ids,
		.suppress_bind_attrs = true,
	},
	.probe		= mxs_gpio_probe,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
339e7730 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	4	// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	5	//
	6	// Based on code from Freescale,
	7	// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
fba311fc	8
641d0342	9	#include <linux/err.h>
fba311fc SG	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/io.h>
	13	#include <linux/irq.h>
0b76c541	14	#include <linux/irqdomain.h>
4052d45e SG	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_device.h>
8d7cf837 SG	18	#include <linux/platform_device.h>
8d7cf837 SG	19	#include <linux/slab.h>
0f4630f3	20	#include <linux/gpio/driver.h>
bb207ef1	21	#include <linux/module.h>
fba311fc	22
8d7cf837 SG	23	#define MXS_SET 0x4
8d7cf837 SG	24	#define MXS_CLR 0x8
fba311fc	25
164387d2 SG	26	#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
	27	#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
	28	#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
	29	#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
	30	#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
	31	#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
	32	#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
	33	#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
fba311fc SG	34
	35	#define GPIO_INT_FALL_EDGE 0x0
	36	#define GPIO_INT_LOW_LEV 0x1
	37	#define GPIO_INT_RISE_EDGE 0x2
	38	#define GPIO_INT_HIGH_LEV 0x3
	39	#define GPIO_INT_LEV_MASK (1 << 0)
	40	#define GPIO_INT_POL_MASK (1 << 1)
	41
164387d2 SG	42	enum mxs_gpio_id {
	43	IMX23_GPIO,
	44	IMX28_GPIO,
	45	};
	46
7b2fa570 GL	47	struct mxs_gpio_port {
	48	void __iomem *base;
	49	int id;
	50	int irq;
0b76c541	51	struct irq_domain *domain;
0f4630f3	52	struct gpio_chip gc;
5751d3dc	53	struct device *dev;
164387d2	54	enum mxs_gpio_id devid;
66d7990e	55	u32 both_edges;
7b2fa570 GL	56	};
7b2fa570 GL	57
164387d2 SG	58	static inline int is_imx23_gpio(struct mxs_gpio_port *port)
	59	{
	60	return port->devid == IMX23_GPIO;
	61	}
	62
fba311fc SG	63	/* Note: This driver assumes 32 GPIOs are handled in one register */
fba311fc SG	64
bf0c1118	65	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	66	{
66d7990e	67	u32 val;
0b76c541	68	u32 pin_mask = 1 << d->hwirq;
498c17cf	69	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
f08ea3cc	70	struct irq_chip_type *ct = irq_data_get_chip_type(d);
498c17cf	71	struct mxs_gpio_port *port = gc->private;
fba311fc SG	72	void __iomem *pin_addr;
	73	int edge;
	74
f08ea3cc SH	75	if (!(ct->type & type))
	76	if (irq_setup_alt_chip(d, type))
	77	return -EINVAL;
	78
66d7990e	79	port->both_edges &= ~pin_mask;
fba311fc	80	switch (type) {
66d7990e	81	case IRQ_TYPE_EDGE_BOTH:
f0df462f	82	val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
66d7990e GGM	83	if (val)
	84	edge = GPIO_INT_FALL_EDGE;
	85	else
	86	edge = GPIO_INT_RISE_EDGE;
	87	port->both_edges \|= pin_mask;
	88	break;
fba311fc SG	89	case IRQ_TYPE_EDGE_RISING:
	90	edge = GPIO_INT_RISE_EDGE;
	91	break;
	92	case IRQ_TYPE_EDGE_FALLING:
	93	edge = GPIO_INT_FALL_EDGE;
	94	break;
	95	case IRQ_TYPE_LEVEL_LOW:
	96	edge = GPIO_INT_LOW_LEV;
	97	break;
	98	case IRQ_TYPE_LEVEL_HIGH:
	99	edge = GPIO_INT_HIGH_LEV;
	100	break;
	101	default:
	102	return -EINVAL;
	103	}
	104
	105	/* set level or edge */
164387d2	106	pin_addr = port->base + PINCTRL_IRQLEV(port);
f08ea3cc	107	if (edge & GPIO_INT_LEV_MASK) {
8d7cf837	108	writel(pin_mask, pin_addr + MXS_SET);
f08ea3cc SH	109	writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
f08ea3cc SH	110	} else {
8d7cf837	111	writel(pin_mask, pin_addr + MXS_CLR);
f08ea3cc SH	112	writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
f08ea3cc SH	113	}
fba311fc SG	114
fba311fc SG	115	/* set polarity */
164387d2	116	pin_addr = port->base + PINCTRL_IRQPOL(port);
fba311fc	117	if (edge & GPIO_INT_POL_MASK)
8d7cf837	118	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	119	else
8d7cf837	120	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc	121
2bee9e06	122	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc SG	123
	124	return 0;
	125	}
	126
66d7990e GGM	127	static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
	128	{
	129	u32 bit, val, edge;
	130	void __iomem *pin_addr;
	131
	132	bit = 1 << gpio;
	133
	134	pin_addr = port->base + PINCTRL_IRQPOL(port);
	135	val = readl(pin_addr);
	136	edge = val & bit;
	137
	138	if (edge)
	139	writel(bit, pin_addr + MXS_CLR);
	140	else
	141	writel(bit, pin_addr + MXS_SET);
	142	}
	143
fba311fc	144	/* MXS has one interrupt per gpio port */
bd0b9ac4	145	static void mxs_gpio_irq_handler(struct irq_desc *desc)
fba311fc SG	146	{
fba311fc SG	147	u32 irq_stat;
476f8b4c	148	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
fba311fc	149
1f6b5dd4 UKK	150	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	151
164387d2 SG	152	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
164387d2 SG	153	readl(port->base + PINCTRL_IRQEN(port));
fba311fc SG	154
	155	while (irq_stat != 0) {
	156	int irqoffset = fls(irq_stat) - 1;
66d7990e GGM	157	if (port->both_edges & (1 << irqoffset))
	158	mxs_flip_edge(port, irqoffset);
	159
dbd1c54f	160	generic_handle_domain_irq(port->domain, irqoffset);
fba311fc SG	161	irq_stat &= ~(1 << irqoffset);
	162	}
	163	}
	164
	165	/*
	166	* Set interrupt number "irq" in the GPIO as a wake-up source.
	167	* While system is running, all registered GPIO interrupts need to have
	168	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	169	* need to have wake-up enabled.
	170	* @param irq interrupt source number
	171	* @param enable enable as wake-up if equal to non-zero
	172	* @return This function returns 0 on success.
	173	*/
bf0c1118	174	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	175	{
498c17cf SG	176	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	177	struct mxs_gpio_port *port = gc->private;
fba311fc	178
6161715e SG	179	if (enable)
	180	enable_irq_wake(port->irq);
	181	else
	182	disable_irq_wake(port->irq);
fba311fc SG	183
	184	return 0;
	185	}
	186
abc8d583	187	static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
498c17cf SG	188	{
	189	struct irq_chip_generic *gc;
	190	struct irq_chip_type *ct;
5751d3dc	191	int rv;
498c17cf	192
5751d3dc BG	193	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
5751d3dc BG	194	port->base, handle_level_irq);
1bbc557d PF	195	if (!gc)
	196	return -ENOMEM;
	197
498c17cf SG	198	gc->private = port;
498c17cf SG	199
f08ea3cc SH	200	ct = &gc->chip_types[0];
	201	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
	202	ct->chip.irq_ack = irq_gc_ack_set_bit;
	203	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	204	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	205	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	206	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	207	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	208	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	209	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
	210	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
	211
	212	ct = &gc->chip_types[1];
	213	ct->type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
591567a5	214	ct->chip.irq_ack = irq_gc_ack_set_bit;
66a37c3b SH	215	ct->chip.irq_mask = irq_gc_mask_disable_reg;
66a37c3b SH	216	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
498c17cf	217	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
591567a5	218	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
f08ea3cc	219	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
164387d2	220	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
66a37c3b SH	221	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
66a37c3b SH	222	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
f08ea3cc	223	ct->handler = handle_level_irq;
498c17cf	224
5751d3dc BG	225	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
	226	IRQ_GC_INIT_NESTED_LOCK,
	227	IRQ_NOREQUEST, 0);
1bbc557d	228
5751d3dc	229	return rv;
498c17cf	230	}
fba311fc	231
cdee1d62	232	static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
fba311fc	233	{
0f4630f3	234	struct mxs_gpio_port *port = gpiochip_get_data(gc);
fba311fc	235
0b76c541	236	return irq_find_mapping(port->domain, offset);
fba311fc SG	237	}
fba311fc SG	238
cdee1d62	239	static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
c8aaa1bf	240	{
0f4630f3	241	struct mxs_gpio_port *port = gpiochip_get_data(gc);
c8aaa1bf JU	242	u32 mask = 1 << offset;
	243	u32 dir;
	244
	245	dir = readl(port->base + PINCTRL_DOE(port));
e42615ec MV	246	if (dir & mask)
	247	return GPIO_LINE_DIRECTION_OUT;
	248
	249	return GPIO_LINE_DIRECTION_IN;
c8aaa1bf JU	250	}
c8aaa1bf JU	251
4052d45e SG	252	static const struct of_device_id mxs_gpio_dt_ids[] = {
	253	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	254	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	255	{ /* sentinel */ }
	256	};
	257	MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
	258
3836309d	259	static int mxs_gpio_probe(struct platform_device *pdev)
fba311fc	260	{
4052d45e SG	261	struct device_node *np = pdev->dev.of_node;
4052d45e SG	262	struct device_node *parent;
8d7cf837 SG	263	static void __iomem *base;
8d7cf837 SG	264	struct mxs_gpio_port *port;
0b76c541	265	int irq_base;
498c17cf	266	int err;
8d7cf837	267
940a4f7b	268	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
8d7cf837 SG	269	if (!port)
	270	return -ENOMEM;
	271
99357127 FE	272	port->id = of_alias_get_id(np, "gpio");
	273	if (port->id < 0)
	274	return port->id;
1f2d357b	275	port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
5751d3dc	276	port->dev = &pdev->dev;
940a4f7b SG	277	port->irq = platform_get_irq(pdev, 0);
	278	if (port->irq < 0)
	279	return port->irq;
	280
8d7cf837 SG	281	/*
	282	* map memory region only once, as all the gpio ports
	283	* share the same one
	284	*/
	285	if (!base) {
99357127 FE	286	parent = of_get_parent(np);
	287	base = of_iomap(parent, 0);
	288	of_node_put(parent);
	289	if (!base)
	290	return -EADDRNOTAVAIL;
8d7cf837 SG	291	}
8d7cf837 SG	292	port->base = base;
fba311fc	293
f08ea3cc SH	294	/* initially disable the interrupts */
f08ea3cc SH	295	writel(0, port->base + PINCTRL_PIN2IRQ(port));
164387d2	296	writel(0, port->base + PINCTRL_IRQEN(port));
fba311fc	297
8d7cf837	298	/* clear address has to be used to clear IRQSTAT bits */
164387d2	299	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc	300
8514b543	301	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
44df0819 AY	302	if (irq_base < 0) {
	303	err = irq_base;
	304	goto out_iounmap;
	305	}
0b76c541 SG	306
	307	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	308	&irq_domain_simple_ops, NULL);
	309	if (!port->domain) {
	310	err = -ENODEV;
8514b543	311	goto out_iounmap;
0b76c541 SG	312	}
0b76c541 SG	313
498c17cf	314	/* gpio-mxs can be a generic irq chip */
1bbc557d PF	315	err = mxs_gpio_init_gc(port, irq_base);
	316	if (err < 0)
	317	goto out_irqdomain_remove;
fba311fc	318
8d7cf837	319	/* setup one handler for each entry */
a44735f4 RK	320	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
a44735f4 RK	321	port);
fba311fc	322
0f4630f3	323	err = bgpio_init(&port->gc, &pdev->dev, 4,
164387d2	324	port->base + PINCTRL_DIN(port),
90dae4eb MR	325	port->base + PINCTRL_DOUT(port) + MXS_SET,
90dae4eb MR	326	port->base + PINCTRL_DOUT(port) + MXS_CLR,
84a442b9	327	port->base + PINCTRL_DOE(port), NULL, 0);
8d7cf837	328	if (err)
0f4630f3	329	goto out_irqdomain_remove;
fba311fc	330
0f4630f3 LW	331	port->gc.to_irq = mxs_gpio_to_irq;
	332	port->gc.get_direction = mxs_gpio_get_direction;
	333	port->gc.base = port->id * 32;
06f88a8a	334
0f4630f3	335	err = gpiochip_add_data(&port->gc, port);
0b76c541	336	if (err)
0f4630f3	337	goto out_irqdomain_remove;
06f88a8a	338
8d7cf837	339	return 0;
0b76c541	340
1bbc557d PF	341	out_irqdomain_remove:
1bbc557d PF	342	irq_domain_remove(port->domain);
44df0819 AY	343	out_iounmap:
44df0819 AY	344	iounmap(port->base);
0b76c541	345	return err;
ef19660b	346	}
8d7cf837 SG	347
	348	static struct platform_driver mxs_gpio_driver = {
	349	.driver = {
	350	.name = "gpio-mxs",
4052d45e	351	.of_match_table = mxs_gpio_dt_ids,
60909ec9	352	.suppress_bind_attrs = true,
8d7cf837 SG	353	},
8d7cf837 SG	354	.probe = mxs_gpio_probe,
fba311fc	355	};
ef19660b	356
8d7cf837	357	static int __init mxs_gpio_init(void)
ef19660b	358	{
8d7cf837	359	return platform_driver_register(&mxs_gpio_driver);
ef19660b	360	}
8d7cf837 SG	361	postcore_initcall(mxs_gpio_init);
	362
	363	MODULE_AUTHOR("Freescale Semiconductor, "
	364	"Daniel Mack <danielncaiaq.de>, "
	365	"Juergen Beisert <kernel@pengutronix.de>");
	366	MODULE_DESCRIPTION("Freescale MXS GPIO");
	367	MODULE_LICENSE("GPL");