[linux-2.6-block.git] / drivers / gpio / gpio-mxs.c

// SPDX-License-Identifier: GPL-2.0+
//
// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
//
// Based on code from Freescale,
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
#define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
#define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
#define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
#define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
#define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
#define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
#define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

enum mxs_gpio_id {
	IMX23_GPIO,
	IMX28_GPIO,
};

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	struct irq_domain *domain;
	struct gpio_chip gc;
	struct device *dev;
	enum mxs_gpio_id devid;
	u32 both_edges;
};

static inline int is_imx23_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX23_GPIO;
}

static inline int is_imx28_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX28_GPIO;
}

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 val;
	u32 pin_mask = 1 << d->hwirq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct mxs_gpio_port *port = gc->private;
	void __iomem *pin_addr;
	int edge;

	if (!(ct->type & type))
		if (irq_setup_alt_chip(d, type))
			return -EINVAL;

	port->both_edges &= ~pin_mask;
	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
		if (val)
			edge = GPIO_INT_FALL_EDGE;
		else
			edge = GPIO_INT_RISE_EDGE;
		port->both_edges |= pin_mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port);
	if (edge & GPIO_INT_LEV_MASK) {
		writel(pin_mask, pin_addr + MXS_SET);
		writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
	} else {
		writel(pin_mask, pin_addr + MXS_CLR);
		writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
	}

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	return 0;
}

static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
{
	u32 bit, val, edge;
	void __iomem *pin_addr;

	bit = 1 << gpio;

	pin_addr = port->base + PINCTRL_IRQPOL(port);
	val = readl(pin_addr);
	edge = val & bit;

	if (edge)
		writel(bit, pin_addr + MXS_CLR);
	else
		writel(bit, pin_addr + MXS_SET);
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
			readl(port->base + PINCTRL_IRQEN(port));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		if (port->both_edges & (1 << irqoffset))
			mxs_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
					 port->base, handle_level_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = port;

	ct = &gc->chip_types[0];
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;

	ct = &gc->chip_types[1];
	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
	ct->handler = handle_level_irq;

	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
					 IRQ_GC_INIT_NESTED_LOCK,
					 IRQ_NOREQUEST, 0);

	return rv;
}

static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mxs_gpio_port *port = gpiochip_get_data(gc);

	return irq_find_mapping(port->domain, offset);
}

static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct mxs_gpio_port *port = gpiochip_get_data(gc);
	u32 mask = 1 << offset;
	u32 dir;

	dir = readl(port->base + PINCTRL_DOE(port));
	return !(dir & mask);
}

static const struct platform_device_id mxs_gpio_ids[] = {
	{
		.name = "imx23-gpio",
		.driver_data = IMX23_GPIO,
	}, {
		.name = "imx28-gpio",
		.driver_data = IMX28_GPIO,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);

static const struct of_device_id mxs_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);

static int mxs_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *parent;
	static void __iomem *base;
	struct mxs_gpio_port *port;
	int irq_base;
	int err;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->id = of_alias_get_id(np, "gpio");
	if (port->id < 0)
		return port->id;
	port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
	port->dev = &pdev->dev;
	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		parent = of_get_parent(np);
		base = of_iomap(parent, 0);
		of_node_put(parent);
		if (!base)
			return -EADDRNOTAVAIL;
	}
	port->base = base;

	/* initially disable the interrupts */
	writel(0, port->base + PINCTRL_PIN2IRQ(port));
	writel(0, port->base + PINCTRL_IRQEN(port));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
	if (irq_base < 0) {
		err = irq_base;
		goto out_iounmap;
	}

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_iounmap;
	}

	/* gpio-mxs can be a generic irq chip */
	err = mxs_gpio_init_gc(port, irq_base);
	if (err < 0)
		goto out_irqdomain_remove;

	/* setup one handler for each entry */
	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
					 port);

	err = bgpio_init(&port->gc, &pdev->dev, 4,
			 port->base + PINCTRL_DIN(port),
			 port->base + PINCTRL_DOUT(port) + MXS_SET,
			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
			 port->base + PINCTRL_DOE(port), NULL, 0);
	if (err)
		goto out_irqdomain_remove;

	port->gc.to_irq = mxs_gpio_to_irq;
	port->gc.get_direction = mxs_gpio_get_direction;
	port->gc.base = port->id * 32;

	err = gpiochip_add_data(&port->gc, port);
	if (err)
		goto out_irqdomain_remove;

	return 0;

out_irqdomain_remove:
	irq_domain_remove(port->domain);
out_iounmap:
	iounmap(port->base);
	return err;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.of_match_table = mxs_gpio_dt_ids,
		.suppress_bind_attrs = true,
	},
	.probe		= mxs_gpio_probe,
	.id_table	= mxs_gpio_ids,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
339e7730 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	4	// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	5	//
	6	// Based on code from Freescale,
	7	// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
fba311fc	8
641d0342	9	#include <linux/err.h>
fba311fc SG	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/io.h>
	13	#include <linux/irq.h>
0b76c541	14	#include <linux/irqdomain.h>
4052d45e SG	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_device.h>
8d7cf837 SG	18	#include <linux/platform_device.h>
8d7cf837 SG	19	#include <linux/slab.h>
0f4630f3	20	#include <linux/gpio/driver.h>
bb207ef1	21	#include <linux/module.h>
fba311fc	22
8d7cf837 SG	23	#define MXS_SET 0x4
8d7cf837 SG	24	#define MXS_CLR 0x8
fba311fc	25
164387d2 SG	26	#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
	27	#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
	28	#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
	29	#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
	30	#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
	31	#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
	32	#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
	33	#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
fba311fc SG	34
	35	#define GPIO_INT_FALL_EDGE 0x0
	36	#define GPIO_INT_LOW_LEV 0x1
	37	#define GPIO_INT_RISE_EDGE 0x2
	38	#define GPIO_INT_HIGH_LEV 0x3
	39	#define GPIO_INT_LEV_MASK (1 << 0)
	40	#define GPIO_INT_POL_MASK (1 << 1)
	41
164387d2 SG	42	enum mxs_gpio_id {
	43	IMX23_GPIO,
	44	IMX28_GPIO,
	45	};
	46
7b2fa570 GL	47	struct mxs_gpio_port {
	48	void __iomem *base;
	49	int id;
	50	int irq;
0b76c541	51	struct irq_domain *domain;
0f4630f3	52	struct gpio_chip gc;
5751d3dc	53	struct device *dev;
164387d2	54	enum mxs_gpio_id devid;
66d7990e	55	u32 both_edges;
7b2fa570 GL	56	};
7b2fa570 GL	57
164387d2 SG	58	static inline int is_imx23_gpio(struct mxs_gpio_port *port)
	59	{
	60	return port->devid == IMX23_GPIO;
	61	}
	62
	63	static inline int is_imx28_gpio(struct mxs_gpio_port *port)
	64	{
	65	return port->devid == IMX28_GPIO;
	66	}
	67
fba311fc SG	68	/* Note: This driver assumes 32 GPIOs are handled in one register */
fba311fc SG	69
bf0c1118	70	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	71	{
66d7990e	72	u32 val;
0b76c541	73	u32 pin_mask = 1 << d->hwirq;
498c17cf	74	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
f08ea3cc	75	struct irq_chip_type *ct = irq_data_get_chip_type(d);
498c17cf	76	struct mxs_gpio_port *port = gc->private;
fba311fc SG	77	void __iomem *pin_addr;
	78	int edge;
	79
f08ea3cc SH	80	if (!(ct->type & type))
	81	if (irq_setup_alt_chip(d, type))
	82	return -EINVAL;
	83
66d7990e	84	port->both_edges &= ~pin_mask;
fba311fc	85	switch (type) {
66d7990e	86	case IRQ_TYPE_EDGE_BOTH:
f0df462f	87	val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
66d7990e GGM	88	if (val)
	89	edge = GPIO_INT_FALL_EDGE;
	90	else
	91	edge = GPIO_INT_RISE_EDGE;
	92	port->both_edges \|= pin_mask;
	93	break;
fba311fc SG	94	case IRQ_TYPE_EDGE_RISING:
	95	edge = GPIO_INT_RISE_EDGE;
	96	break;
	97	case IRQ_TYPE_EDGE_FALLING:
	98	edge = GPIO_INT_FALL_EDGE;
	99	break;
	100	case IRQ_TYPE_LEVEL_LOW:
	101	edge = GPIO_INT_LOW_LEV;
	102	break;
	103	case IRQ_TYPE_LEVEL_HIGH:
	104	edge = GPIO_INT_HIGH_LEV;
	105	break;
	106	default:
	107	return -EINVAL;
	108	}
	109
	110	/* set level or edge */
164387d2	111	pin_addr = port->base + PINCTRL_IRQLEV(port);
f08ea3cc	112	if (edge & GPIO_INT_LEV_MASK) {
8d7cf837	113	writel(pin_mask, pin_addr + MXS_SET);
f08ea3cc SH	114	writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
f08ea3cc SH	115	} else {
8d7cf837	116	writel(pin_mask, pin_addr + MXS_CLR);
f08ea3cc SH	117	writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
f08ea3cc SH	118	}
fba311fc SG	119
fba311fc SG	120	/* set polarity */
164387d2	121	pin_addr = port->base + PINCTRL_IRQPOL(port);
fba311fc	122	if (edge & GPIO_INT_POL_MASK)
8d7cf837	123	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	124	else
8d7cf837	125	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc	126
2bee9e06	127	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc SG	128
	129	return 0;
	130	}
	131
66d7990e GGM	132	static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
	133	{
	134	u32 bit, val, edge;
	135	void __iomem *pin_addr;
	136
	137	bit = 1 << gpio;
	138
	139	pin_addr = port->base + PINCTRL_IRQPOL(port);
	140	val = readl(pin_addr);
	141	edge = val & bit;
	142
	143	if (edge)
	144	writel(bit, pin_addr + MXS_CLR);
	145	else
	146	writel(bit, pin_addr + MXS_SET);
	147	}
	148
fba311fc	149	/* MXS has one interrupt per gpio port */
bd0b9ac4	150	static void mxs_gpio_irq_handler(struct irq_desc *desc)
fba311fc SG	151	{
fba311fc SG	152	u32 irq_stat;
476f8b4c	153	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
fba311fc	154
1f6b5dd4 UKK	155	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	156
164387d2 SG	157	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
164387d2 SG	158	readl(port->base + PINCTRL_IRQEN(port));
fba311fc SG	159
	160	while (irq_stat != 0) {
	161	int irqoffset = fls(irq_stat) - 1;
66d7990e GGM	162	if (port->both_edges & (1 << irqoffset))
	163	mxs_flip_edge(port, irqoffset);
	164
0b76c541	165	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
fba311fc SG	166	irq_stat &= ~(1 << irqoffset);
	167	}
	168	}
	169
	170	/*
	171	* Set interrupt number "irq" in the GPIO as a wake-up source.
	172	* While system is running, all registered GPIO interrupts need to have
	173	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	174	* need to have wake-up enabled.
	175	* @param irq interrupt source number
	176	* @param enable enable as wake-up if equal to non-zero
	177	* @return This function returns 0 on success.
	178	*/
bf0c1118	179	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	180	{
498c17cf SG	181	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	182	struct mxs_gpio_port *port = gc->private;
fba311fc	183
6161715e SG	184	if (enable)
	185	enable_irq_wake(port->irq);
	186	else
	187	disable_irq_wake(port->irq);
fba311fc SG	188
	189	return 0;
	190	}
	191
abc8d583	192	static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
498c17cf SG	193	{
	194	struct irq_chip_generic *gc;
	195	struct irq_chip_type *ct;
5751d3dc	196	int rv;
498c17cf	197
5751d3dc BG	198	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
5751d3dc BG	199	port->base, handle_level_irq);
1bbc557d PF	200	if (!gc)
	201	return -ENOMEM;
	202
498c17cf SG	203	gc->private = port;
498c17cf SG	204
f08ea3cc SH	205	ct = &gc->chip_types[0];
	206	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
	207	ct->chip.irq_ack = irq_gc_ack_set_bit;
	208	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	209	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	210	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	211	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	212	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	213	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	214	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
	215	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
	216
	217	ct = &gc->chip_types[1];
	218	ct->type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
591567a5	219	ct->chip.irq_ack = irq_gc_ack_set_bit;
66a37c3b SH	220	ct->chip.irq_mask = irq_gc_mask_disable_reg;
66a37c3b SH	221	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
498c17cf	222	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
591567a5	223	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
f08ea3cc	224	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
164387d2	225	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
66a37c3b SH	226	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
66a37c3b SH	227	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
f08ea3cc	228	ct->handler = handle_level_irq;
498c17cf	229
5751d3dc BG	230	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
	231	IRQ_GC_INIT_NESTED_LOCK,
	232	IRQ_NOREQUEST, 0);
1bbc557d	233
5751d3dc	234	return rv;
498c17cf	235	}
fba311fc	236
06f88a8a	237	static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
fba311fc	238	{
0f4630f3	239	struct mxs_gpio_port *port = gpiochip_get_data(gc);
fba311fc	240
0b76c541	241	return irq_find_mapping(port->domain, offset);
fba311fc SG	242	}
fba311fc SG	243
c8aaa1bf JU	244	static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
c8aaa1bf JU	245	{
0f4630f3	246	struct mxs_gpio_port *port = gpiochip_get_data(gc);
c8aaa1bf JU	247	u32 mask = 1 << offset;
	248	u32 dir;
	249
	250	dir = readl(port->base + PINCTRL_DOE(port));
	251	return !(dir & mask);
	252	}
	253
f4f79d40	254	static const struct platform_device_id mxs_gpio_ids[] = {
164387d2 SG	255	{
	256	.name = "imx23-gpio",
	257	.driver_data = IMX23_GPIO,
	258	}, {
	259	.name = "imx28-gpio",
	260	.driver_data = IMX28_GPIO,
	261	}, {
	262	/* sentinel */
	263	}
	264	};
	265	MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
	266
4052d45e SG	267	static const struct of_device_id mxs_gpio_dt_ids[] = {
	268	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	269	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	270	{ /* sentinel */ }
	271	};
	272	MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
	273
3836309d	274	static int mxs_gpio_probe(struct platform_device *pdev)
fba311fc	275	{
4052d45e SG	276	struct device_node *np = pdev->dev.of_node;
4052d45e SG	277	struct device_node *parent;
8d7cf837 SG	278	static void __iomem *base;
8d7cf837 SG	279	struct mxs_gpio_port *port;
0b76c541	280	int irq_base;
498c17cf	281	int err;
8d7cf837	282
940a4f7b	283	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
8d7cf837 SG	284	if (!port)
	285	return -ENOMEM;
	286
99357127 FE	287	port->id = of_alias_get_id(np, "gpio");
	288	if (port->id < 0)
	289	return port->id;
1f2d357b	290	port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
5751d3dc	291	port->dev = &pdev->dev;
940a4f7b SG	292	port->irq = platform_get_irq(pdev, 0);
	293	if (port->irq < 0)
	294	return port->irq;
	295
8d7cf837 SG	296	/*
	297	* map memory region only once, as all the gpio ports
	298	* share the same one
	299	*/
	300	if (!base) {
99357127 FE	301	parent = of_get_parent(np);
	302	base = of_iomap(parent, 0);
	303	of_node_put(parent);
	304	if (!base)
	305	return -EADDRNOTAVAIL;
8d7cf837 SG	306	}
8d7cf837 SG	307	port->base = base;
fba311fc	308
f08ea3cc SH	309	/* initially disable the interrupts */
f08ea3cc SH	310	writel(0, port->base + PINCTRL_PIN2IRQ(port));
164387d2	311	writel(0, port->base + PINCTRL_IRQEN(port));
fba311fc	312
8d7cf837	313	/* clear address has to be used to clear IRQSTAT bits */
164387d2	314	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc	315
8514b543	316	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
44df0819 AY	317	if (irq_base < 0) {
	318	err = irq_base;
	319	goto out_iounmap;
	320	}
0b76c541 SG	321
	322	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	323	&irq_domain_simple_ops, NULL);
	324	if (!port->domain) {
	325	err = -ENODEV;
8514b543	326	goto out_iounmap;
0b76c541 SG	327	}
0b76c541 SG	328
498c17cf	329	/* gpio-mxs can be a generic irq chip */
1bbc557d PF	330	err = mxs_gpio_init_gc(port, irq_base);
	331	if (err < 0)
	332	goto out_irqdomain_remove;
fba311fc	333
8d7cf837	334	/* setup one handler for each entry */
a44735f4 RK	335	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
a44735f4 RK	336	port);
fba311fc	337
0f4630f3	338	err = bgpio_init(&port->gc, &pdev->dev, 4,
164387d2	339	port->base + PINCTRL_DIN(port),
90dae4eb MR	340	port->base + PINCTRL_DOUT(port) + MXS_SET,
90dae4eb MR	341	port->base + PINCTRL_DOUT(port) + MXS_CLR,
84a442b9	342	port->base + PINCTRL_DOE(port), NULL, 0);
8d7cf837	343	if (err)
0f4630f3	344	goto out_irqdomain_remove;
fba311fc	345
0f4630f3 LW	346	port->gc.to_irq = mxs_gpio_to_irq;
	347	port->gc.get_direction = mxs_gpio_get_direction;
	348	port->gc.base = port->id * 32;
06f88a8a	349
0f4630f3	350	err = gpiochip_add_data(&port->gc, port);
0b76c541	351	if (err)
0f4630f3	352	goto out_irqdomain_remove;
06f88a8a	353
8d7cf837	354	return 0;
0b76c541	355
1bbc557d PF	356	out_irqdomain_remove:
1bbc557d PF	357	irq_domain_remove(port->domain);
44df0819 AY	358	out_iounmap:
44df0819 AY	359	iounmap(port->base);
0b76c541	360	return err;
ef19660b	361	}
8d7cf837 SG	362
	363	static struct platform_driver mxs_gpio_driver = {
	364	.driver = {
	365	.name = "gpio-mxs",
4052d45e	366	.of_match_table = mxs_gpio_dt_ids,
60909ec9	367	.suppress_bind_attrs = true,
8d7cf837 SG	368	},
8d7cf837 SG	369	.probe = mxs_gpio_probe,
164387d2	370	.id_table = mxs_gpio_ids,
fba311fc	371	};
ef19660b	372
8d7cf837	373	static int __init mxs_gpio_init(void)
ef19660b	374	{
8d7cf837	375	return platform_driver_register(&mxs_gpio_driver);
ef19660b	376	}
8d7cf837 SG	377	postcore_initcall(mxs_gpio_init);
	378
	379	MODULE_AUTHOR("Freescale Semiconductor, "
	380	"Daniel Mack <danielncaiaq.de>, "
	381	"Juergen Beisert <kernel@pengutronix.de>");
	382	MODULE_DESCRIPTION("Freescale MXS GPIO");
	383	MODULE_LICENSE("GPL");