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014e420d FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | |
4 | // Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
5 | // | |
6 | // Based on code from Freescale Semiconductor, | |
7 | // Authors: Daniel Mack, Juergen Beisert. | |
8 | // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
07bd1a6c | 9 | |
2808801a | 10 | #include <linux/clk.h> |
18f92b19 | 11 | #include <linux/err.h> |
07bd1a6c | 12 | #include <linux/init.h> |
a3484ffd | 13 | #include <linux/interrupt.h> |
07bd1a6c JB |
14 | #include <linux/io.h> |
15 | #include <linux/irq.h> | |
1ab7ef15 | 16 | #include <linux/irqdomain.h> |
de88cbb7 | 17 | #include <linux/irqchip/chained_irq.h> |
b78d8e59 SG |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> | |
1a5287a3 | 20 | #include <linux/syscore_ops.h> |
0f4630f3 | 21 | #include <linux/gpio/driver.h> |
8937cb60 SG |
22 | #include <linux/of.h> |
23 | #include <linux/of_device.h> | |
16c3bd35 | 24 | #include <linux/bug.h> |
07bd1a6c | 25 | |
e7fc6ae7 SG |
26 | enum mxc_gpio_hwtype { |
27 | IMX1_GPIO, /* runs on i.mx1 */ | |
28 | IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ | |
aeb27748 BT |
29 | IMX31_GPIO, /* runs on i.mx31 */ |
30 | IMX35_GPIO, /* runs on all other i.mx */ | |
e7fc6ae7 SG |
31 | }; |
32 | ||
33 | /* device type dependent stuff */ | |
34 | struct mxc_gpio_hwdata { | |
35 | unsigned dr_reg; | |
36 | unsigned gdir_reg; | |
37 | unsigned psr_reg; | |
38 | unsigned icr1_reg; | |
39 | unsigned icr2_reg; | |
40 | unsigned imr_reg; | |
41 | unsigned isr_reg; | |
aeb27748 | 42 | int edge_sel_reg; |
e7fc6ae7 SG |
43 | unsigned low_level; |
44 | unsigned high_level; | |
45 | unsigned rise_edge; | |
46 | unsigned fall_edge; | |
47 | }; | |
48 | ||
c19fdaee AH |
49 | struct mxc_gpio_reg_saved { |
50 | u32 icr1; | |
51 | u32 icr2; | |
52 | u32 imr; | |
53 | u32 gdir; | |
54 | u32 edge_sel; | |
55 | u32 dr; | |
56 | }; | |
57 | ||
b78d8e59 SG |
58 | struct mxc_gpio_port { |
59 | struct list_head node; | |
60 | void __iomem *base; | |
2808801a | 61 | struct clk *clk; |
b78d8e59 SG |
62 | int irq; |
63 | int irq_high; | |
1ab7ef15 | 64 | struct irq_domain *domain; |
0f4630f3 | 65 | struct gpio_chip gc; |
db5270ac | 66 | struct device *dev; |
b78d8e59 | 67 | u32 both_edges; |
c19fdaee AH |
68 | struct mxc_gpio_reg_saved gpio_saved_reg; |
69 | bool power_off; | |
b78d8e59 SG |
70 | }; |
71 | ||
e7fc6ae7 SG |
72 | static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { |
73 | .dr_reg = 0x1c, | |
74 | .gdir_reg = 0x00, | |
75 | .psr_reg = 0x24, | |
76 | .icr1_reg = 0x28, | |
77 | .icr2_reg = 0x2c, | |
78 | .imr_reg = 0x30, | |
79 | .isr_reg = 0x34, | |
aeb27748 | 80 | .edge_sel_reg = -EINVAL, |
e7fc6ae7 SG |
81 | .low_level = 0x03, |
82 | .high_level = 0x02, | |
83 | .rise_edge = 0x00, | |
84 | .fall_edge = 0x01, | |
85 | }; | |
86 | ||
87 | static struct mxc_gpio_hwdata imx31_gpio_hwdata = { | |
88 | .dr_reg = 0x00, | |
89 | .gdir_reg = 0x04, | |
90 | .psr_reg = 0x08, | |
91 | .icr1_reg = 0x0c, | |
92 | .icr2_reg = 0x10, | |
93 | .imr_reg = 0x14, | |
94 | .isr_reg = 0x18, | |
aeb27748 BT |
95 | .edge_sel_reg = -EINVAL, |
96 | .low_level = 0x00, | |
97 | .high_level = 0x01, | |
98 | .rise_edge = 0x02, | |
99 | .fall_edge = 0x03, | |
100 | }; | |
101 | ||
102 | static struct mxc_gpio_hwdata imx35_gpio_hwdata = { | |
103 | .dr_reg = 0x00, | |
104 | .gdir_reg = 0x04, | |
105 | .psr_reg = 0x08, | |
106 | .icr1_reg = 0x0c, | |
107 | .icr2_reg = 0x10, | |
108 | .imr_reg = 0x14, | |
109 | .isr_reg = 0x18, | |
110 | .edge_sel_reg = 0x1c, | |
e7fc6ae7 SG |
111 | .low_level = 0x00, |
112 | .high_level = 0x01, | |
113 | .rise_edge = 0x02, | |
114 | .fall_edge = 0x03, | |
115 | }; | |
116 | ||
117 | static enum mxc_gpio_hwtype mxc_gpio_hwtype; | |
118 | static struct mxc_gpio_hwdata *mxc_gpio_hwdata; | |
119 | ||
120 | #define GPIO_DR (mxc_gpio_hwdata->dr_reg) | |
121 | #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) | |
122 | #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) | |
123 | #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) | |
124 | #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) | |
125 | #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) | |
126 | #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) | |
aeb27748 | 127 | #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) |
e7fc6ae7 SG |
128 | |
129 | #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) | |
130 | #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) | |
131 | #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) | |
132 | #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) | |
aeb27748 | 133 | #define GPIO_INT_BOTH_EDGES 0x4 |
e7fc6ae7 | 134 | |
f4f79d40 | 135 | static const struct platform_device_id mxc_gpio_devtype[] = { |
e7fc6ae7 SG |
136 | { |
137 | .name = "imx1-gpio", | |
138 | .driver_data = IMX1_GPIO, | |
139 | }, { | |
140 | .name = "imx21-gpio", | |
141 | .driver_data = IMX21_GPIO, | |
142 | }, { | |
143 | .name = "imx31-gpio", | |
144 | .driver_data = IMX31_GPIO, | |
aeb27748 BT |
145 | }, { |
146 | .name = "imx35-gpio", | |
147 | .driver_data = IMX35_GPIO, | |
e7fc6ae7 SG |
148 | }, { |
149 | /* sentinel */ | |
150 | } | |
151 | }; | |
152 | ||
8937cb60 SG |
153 | static const struct of_device_id mxc_gpio_dt_ids[] = { |
154 | { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, | |
155 | { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, | |
156 | { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, | |
aeb27748 | 157 | { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, |
c19fdaee | 158 | { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, |
8937cb60 SG |
159 | { /* sentinel */ } |
160 | }; | |
161 | ||
b78d8e59 SG |
162 | /* |
163 | * MX2 has one interrupt *for all* gpio ports. The list is used | |
164 | * to save the references to all ports, so that mx2_gpio_irq_handler | |
165 | * can walk through all interrupt status registers. | |
166 | */ | |
167 | static LIST_HEAD(mxc_gpio_ports); | |
07bd1a6c JB |
168 | |
169 | /* Note: This driver assumes 32 GPIOs are handled in one register */ | |
170 | ||
4d93579f | 171 | static int gpio_set_irq_type(struct irq_data *d, u32 type) |
07bd1a6c | 172 | { |
e4ea9333 SG |
173 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
174 | struct mxc_gpio_port *port = gc->private; | |
07bd1a6c | 175 | u32 bit, val; |
1ab7ef15 | 176 | u32 gpio_idx = d->hwirq; |
07bd1a6c JB |
177 | int edge; |
178 | void __iomem *reg = port->base; | |
179 | ||
1ab7ef15 | 180 | port->both_edges &= ~(1 << gpio_idx); |
07bd1a6c | 181 | switch (type) { |
6cab4860 | 182 | case IRQ_TYPE_EDGE_RISING: |
07bd1a6c JB |
183 | edge = GPIO_INT_RISE_EDGE; |
184 | break; | |
6cab4860 | 185 | case IRQ_TYPE_EDGE_FALLING: |
07bd1a6c JB |
186 | edge = GPIO_INT_FALL_EDGE; |
187 | break; | |
910862ec | 188 | case IRQ_TYPE_EDGE_BOTH: |
aeb27748 BT |
189 | if (GPIO_EDGE_SEL >= 0) { |
190 | edge = GPIO_INT_BOTH_EDGES; | |
910862ec | 191 | } else { |
8d0bd9a5 | 192 | val = port->gc.get(&port->gc, gpio_idx); |
aeb27748 BT |
193 | if (val) { |
194 | edge = GPIO_INT_LOW_LEV; | |
8d0bd9a5 | 195 | pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); |
aeb27748 BT |
196 | } else { |
197 | edge = GPIO_INT_HIGH_LEV; | |
8d0bd9a5 | 198 | pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); |
aeb27748 | 199 | } |
f948ad07 | 200 | port->both_edges |= 1 << gpio_idx; |
910862ec | 201 | } |
910862ec | 202 | break; |
6cab4860 | 203 | case IRQ_TYPE_LEVEL_LOW: |
07bd1a6c JB |
204 | edge = GPIO_INT_LOW_LEV; |
205 | break; | |
6cab4860 | 206 | case IRQ_TYPE_LEVEL_HIGH: |
07bd1a6c JB |
207 | edge = GPIO_INT_HIGH_LEV; |
208 | break; | |
910862ec | 209 | default: |
07bd1a6c JB |
210 | return -EINVAL; |
211 | } | |
212 | ||
aeb27748 BT |
213 | if (GPIO_EDGE_SEL >= 0) { |
214 | val = readl(port->base + GPIO_EDGE_SEL); | |
215 | if (edge == GPIO_INT_BOTH_EDGES) | |
f948ad07 | 216 | writel(val | (1 << gpio_idx), |
aeb27748 BT |
217 | port->base + GPIO_EDGE_SEL); |
218 | else | |
f948ad07 | 219 | writel(val & ~(1 << gpio_idx), |
aeb27748 BT |
220 | port->base + GPIO_EDGE_SEL); |
221 | } | |
222 | ||
223 | if (edge != GPIO_INT_BOTH_EDGES) { | |
f948ad07 LT |
224 | reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ |
225 | bit = gpio_idx & 0xf; | |
aeb27748 BT |
226 | val = readl(reg) & ~(0x3 << (bit << 1)); |
227 | writel(val | (edge << (bit << 1)), reg); | |
228 | } | |
229 | ||
1ab7ef15 | 230 | writel(1 << gpio_idx, port->base + GPIO_ISR); |
07bd1a6c JB |
231 | |
232 | return 0; | |
233 | } | |
234 | ||
910862ec GL |
235 | static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) |
236 | { | |
237 | void __iomem *reg = port->base; | |
238 | u32 bit, val; | |
239 | int edge; | |
240 | ||
241 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ | |
242 | bit = gpio & 0xf; | |
b78d8e59 | 243 | val = readl(reg); |
910862ec GL |
244 | edge = (val >> (bit << 1)) & 3; |
245 | val &= ~(0x3 << (bit << 1)); | |
3d40f7fe | 246 | if (edge == GPIO_INT_HIGH_LEV) { |
910862ec GL |
247 | edge = GPIO_INT_LOW_LEV; |
248 | pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); | |
3d40f7fe | 249 | } else if (edge == GPIO_INT_LOW_LEV) { |
910862ec GL |
250 | edge = GPIO_INT_HIGH_LEV; |
251 | pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); | |
3d40f7fe | 252 | } else { |
910862ec GL |
253 | pr_err("mxc: invalid configuration for GPIO %d: %x\n", |
254 | gpio, edge); | |
255 | return; | |
256 | } | |
b78d8e59 | 257 | writel(val | (edge << (bit << 1)), reg); |
910862ec GL |
258 | } |
259 | ||
3621f188 | 260 | /* handle 32 interrupts in one status register */ |
07bd1a6c JB |
261 | static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) |
262 | { | |
3621f188 UKK |
263 | while (irq_stat != 0) { |
264 | int irqoffset = fls(irq_stat) - 1; | |
07bd1a6c | 265 | |
3621f188 UKK |
266 | if (port->both_edges & (1 << irqoffset)) |
267 | mxc_flip_edge(port, irqoffset); | |
910862ec | 268 | |
1ab7ef15 | 269 | generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); |
910862ec | 270 | |
3621f188 | 271 | irq_stat &= ~(1 << irqoffset); |
07bd1a6c JB |
272 | } |
273 | } | |
274 | ||
cfca8b53 | 275 | /* MX1 and MX3 has one interrupt *per* gpio port */ |
bd0b9ac4 | 276 | static void mx3_gpio_irq_handler(struct irq_desc *desc) |
07bd1a6c JB |
277 | { |
278 | u32 irq_stat; | |
476f8b4c JL |
279 | struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); |
280 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0e44b6ec SG |
281 | |
282 | chained_irq_enter(chip, desc); | |
07bd1a6c | 283 | |
b78d8e59 | 284 | irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); |
e2c97e7f | 285 | |
07bd1a6c | 286 | mxc_gpio_irq_handler(port, irq_stat); |
0e44b6ec SG |
287 | |
288 | chained_irq_exit(chip, desc); | |
07bd1a6c | 289 | } |
07bd1a6c | 290 | |
07bd1a6c | 291 | /* MX2 has one interrupt *for all* gpio ports */ |
bd0b9ac4 | 292 | static void mx2_gpio_irq_handler(struct irq_desc *desc) |
07bd1a6c | 293 | { |
07bd1a6c | 294 | u32 irq_msk, irq_stat; |
b78d8e59 | 295 | struct mxc_gpio_port *port; |
476f8b4c | 296 | struct irq_chip *chip = irq_desc_get_chip(desc); |
c0e811d9 UKK |
297 | |
298 | chained_irq_enter(chip, desc); | |
07bd1a6c JB |
299 | |
300 | /* walk through all interrupt status registers */ | |
b78d8e59 SG |
301 | list_for_each_entry(port, &mxc_gpio_ports, node) { |
302 | irq_msk = readl(port->base + GPIO_IMR); | |
07bd1a6c JB |
303 | if (!irq_msk) |
304 | continue; | |
305 | ||
b78d8e59 | 306 | irq_stat = readl(port->base + GPIO_ISR) & irq_msk; |
07bd1a6c | 307 | if (irq_stat) |
b78d8e59 | 308 | mxc_gpio_irq_handler(port, irq_stat); |
07bd1a6c | 309 | } |
c0e811d9 | 310 | chained_irq_exit(chip, desc); |
07bd1a6c | 311 | } |
07bd1a6c | 312 | |
a3484ffd DN |
313 | /* |
314 | * Set interrupt number "irq" in the GPIO as a wake-up source. | |
315 | * While system is running, all registered GPIO interrupts need to have | |
316 | * wake-up enabled. When system is suspended, only selected GPIO interrupts | |
317 | * need to have wake-up enabled. | |
318 | * @param irq interrupt source number | |
319 | * @param enable enable as wake-up if equal to non-zero | |
320 | * @return This function returns 0 on success. | |
321 | */ | |
4d93579f | 322 | static int gpio_set_wake_irq(struct irq_data *d, u32 enable) |
a3484ffd | 323 | { |
e4ea9333 SG |
324 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
325 | struct mxc_gpio_port *port = gc->private; | |
1ab7ef15 | 326 | u32 gpio_idx = d->hwirq; |
77a4d757 | 327 | int ret; |
a3484ffd DN |
328 | |
329 | if (enable) { | |
330 | if (port->irq_high && (gpio_idx >= 16)) | |
77a4d757 | 331 | ret = enable_irq_wake(port->irq_high); |
a3484ffd | 332 | else |
77a4d757 | 333 | ret = enable_irq_wake(port->irq); |
a3484ffd DN |
334 | } else { |
335 | if (port->irq_high && (gpio_idx >= 16)) | |
77a4d757 | 336 | ret = disable_irq_wake(port->irq_high); |
a3484ffd | 337 | else |
77a4d757 | 338 | ret = disable_irq_wake(port->irq); |
a3484ffd DN |
339 | } |
340 | ||
77a4d757 | 341 | return ret; |
a3484ffd DN |
342 | } |
343 | ||
9e26b0b1 | 344 | static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) |
e4ea9333 SG |
345 | { |
346 | struct irq_chip_generic *gc; | |
347 | struct irq_chip_type *ct; | |
db5270ac | 348 | int rv; |
e4ea9333 | 349 | |
db5270ac BG |
350 | gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, |
351 | port->base, handle_level_irq); | |
9e26b0b1 PF |
352 | if (!gc) |
353 | return -ENOMEM; | |
e4ea9333 SG |
354 | gc->private = port; |
355 | ||
356 | ct = gc->chip_types; | |
591567a5 | 357 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
e4ea9333 SG |
358 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
359 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
360 | ct->chip.irq_set_type = gpio_set_irq_type; | |
591567a5 | 361 | ct->chip.irq_set_wake = gpio_set_wake_irq; |
952cfbd3 | 362 | ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; |
e4ea9333 SG |
363 | ct->regs.ack = GPIO_ISR; |
364 | ct->regs.mask = GPIO_IMR; | |
365 | ||
db5270ac BG |
366 | rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), |
367 | IRQ_GC_INIT_NESTED_LOCK, | |
368 | IRQ_NOREQUEST, 0); | |
9e26b0b1 | 369 | |
db5270ac | 370 | return rv; |
e4ea9333 | 371 | } |
b5eee2fd | 372 | |
3836309d | 373 | static void mxc_gpio_get_hw(struct platform_device *pdev) |
e7fc6ae7 | 374 | { |
8937cb60 SG |
375 | const struct of_device_id *of_id = |
376 | of_match_device(mxc_gpio_dt_ids, &pdev->dev); | |
377 | enum mxc_gpio_hwtype hwtype; | |
378 | ||
379 | if (of_id) | |
380 | pdev->id_entry = of_id->data; | |
381 | hwtype = pdev->id_entry->driver_data; | |
e7fc6ae7 SG |
382 | |
383 | if (mxc_gpio_hwtype) { | |
384 | /* | |
385 | * The driver works with a reasonable presupposition, | |
386 | * that is all gpio ports must be the same type when | |
387 | * running on one soc. | |
388 | */ | |
389 | BUG_ON(mxc_gpio_hwtype != hwtype); | |
390 | return; | |
391 | } | |
392 | ||
aeb27748 BT |
393 | if (hwtype == IMX35_GPIO) |
394 | mxc_gpio_hwdata = &imx35_gpio_hwdata; | |
395 | else if (hwtype == IMX31_GPIO) | |
e7fc6ae7 SG |
396 | mxc_gpio_hwdata = &imx31_gpio_hwdata; |
397 | else | |
398 | mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; | |
399 | ||
400 | mxc_gpio_hwtype = hwtype; | |
401 | } | |
402 | ||
09ad8039 SG |
403 | static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
404 | { | |
0f4630f3 | 405 | struct mxc_gpio_port *port = gpiochip_get_data(gc); |
09ad8039 | 406 | |
1ab7ef15 | 407 | return irq_find_mapping(port->domain, offset); |
09ad8039 SG |
408 | } |
409 | ||
3836309d | 410 | static int mxc_gpio_probe(struct platform_device *pdev) |
07bd1a6c | 411 | { |
8937cb60 | 412 | struct device_node *np = pdev->dev.of_node; |
b78d8e59 | 413 | struct mxc_gpio_port *port; |
1ab7ef15 | 414 | int irq_base; |
e4ea9333 | 415 | int err; |
b78d8e59 | 416 | |
e7fc6ae7 SG |
417 | mxc_gpio_get_hw(pdev); |
418 | ||
8cd73e4e | 419 | port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); |
b78d8e59 SG |
420 | if (!port) |
421 | return -ENOMEM; | |
07bd1a6c | 422 | |
db5270ac BG |
423 | port->dev = &pdev->dev; |
424 | ||
123ac0e5 | 425 | port->base = devm_platform_ioremap_resource(pdev, 0); |
8cd73e4e FE |
426 | if (IS_ERR(port->base)) |
427 | return PTR_ERR(port->base); | |
b78d8e59 SG |
428 | |
429 | port->irq_high = platform_get_irq(pdev, 1); | |
cc9269f8 PR |
430 | if (port->irq_high < 0) |
431 | port->irq_high = 0; | |
432 | ||
b78d8e59 | 433 | port->irq = platform_get_irq(pdev, 0); |
8cd73e4e | 434 | if (port->irq < 0) |
5ea80e49 | 435 | return port->irq; |
b78d8e59 | 436 | |
2808801a AH |
437 | /* the controller clock is optional */ |
438 | port->clk = devm_clk_get(&pdev->dev, NULL); | |
a329bbe7 AH |
439 | if (IS_ERR(port->clk)) { |
440 | if (PTR_ERR(port->clk) == -EPROBE_DEFER) | |
441 | return -EPROBE_DEFER; | |
2808801a | 442 | port->clk = NULL; |
a329bbe7 | 443 | } |
2808801a AH |
444 | |
445 | err = clk_prepare_enable(port->clk); | |
446 | if (err) { | |
447 | dev_err(&pdev->dev, "Unable to enable clock.\n"); | |
448 | return err; | |
449 | } | |
450 | ||
c19fdaee AH |
451 | if (of_device_is_compatible(np, "fsl,imx7d-gpio")) |
452 | port->power_off = true; | |
453 | ||
b78d8e59 SG |
454 | /* disable the interrupt and clear the status */ |
455 | writel(0, port->base + GPIO_IMR); | |
456 | writel(~0, port->base + GPIO_ISR); | |
457 | ||
e7fc6ae7 | 458 | if (mxc_gpio_hwtype == IMX21_GPIO) { |
33a4e985 UKK |
459 | /* |
460 | * Setup one handler for all GPIO interrupts. Actually setting | |
461 | * the handler is needed only once, but doing it for every port | |
462 | * is more robust and easier. | |
463 | */ | |
464 | irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); | |
b78d8e59 SG |
465 | } else { |
466 | /* setup one handler for each entry */ | |
e65eea54 RK |
467 | irq_set_chained_handler_and_data(port->irq, |
468 | mx3_gpio_irq_handler, port); | |
469 | if (port->irq_high > 0) | |
b78d8e59 | 470 | /* setup handler for GPIO 16 to 31 */ |
e65eea54 RK |
471 | irq_set_chained_handler_and_data(port->irq_high, |
472 | mx3_gpio_irq_handler, | |
473 | port); | |
07bd1a6c JB |
474 | } |
475 | ||
0f4630f3 | 476 | err = bgpio_init(&port->gc, &pdev->dev, 4, |
2ce420da SG |
477 | port->base + GPIO_PSR, |
478 | port->base + GPIO_DR, NULL, | |
442b2494 VZ |
479 | port->base + GPIO_GDIR, NULL, |
480 | BGPIOF_READ_OUTPUT_REG_SET); | |
2ce420da | 481 | if (err) |
8cd73e4e | 482 | goto out_bgio; |
b78d8e59 | 483 | |
4c806c98 VZ |
484 | if (of_property_read_bool(np, "gpio-ranges")) { |
485 | port->gc.request = gpiochip_generic_request; | |
486 | port->gc.free = gpiochip_generic_free; | |
487 | } | |
488 | ||
0f4630f3 LW |
489 | port->gc.to_irq = mxc_gpio_to_irq; |
490 | port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : | |
7e6086d9 | 491 | pdev->id * 32; |
b78d8e59 | 492 | |
ffc56630 | 493 | err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); |
b78d8e59 | 494 | if (err) |
0f4630f3 | 495 | goto out_bgio; |
b78d8e59 | 496 | |
c553c3c4 | 497 | irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); |
1ab7ef15 SG |
498 | if (irq_base < 0) { |
499 | err = irq_base; | |
ffc56630 | 500 | goto out_bgio; |
1ab7ef15 SG |
501 | } |
502 | ||
503 | port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, | |
504 | &irq_domain_simple_ops, NULL); | |
505 | if (!port->domain) { | |
506 | err = -ENODEV; | |
c553c3c4 | 507 | goto out_bgio; |
1ab7ef15 | 508 | } |
8937cb60 SG |
509 | |
510 | /* gpio-mxc can be a generic irq chip */ | |
9e26b0b1 PF |
511 | err = mxc_gpio_init_gc(port, irq_base); |
512 | if (err < 0) | |
513 | goto out_irqdomain_remove; | |
8937cb60 | 514 | |
b78d8e59 SG |
515 | list_add_tail(&port->node, &mxc_gpio_ports); |
516 | ||
c19fdaee AH |
517 | platform_set_drvdata(pdev, port); |
518 | ||
07bd1a6c | 519 | return 0; |
b78d8e59 | 520 | |
9e26b0b1 PF |
521 | out_irqdomain_remove: |
522 | irq_domain_remove(port->domain); | |
8cd73e4e | 523 | out_bgio: |
2808801a | 524 | clk_disable_unprepare(port->clk); |
b78d8e59 SG |
525 | dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); |
526 | return err; | |
07bd1a6c | 527 | } |
b78d8e59 | 528 | |
c19fdaee AH |
529 | static void mxc_gpio_save_regs(struct mxc_gpio_port *port) |
530 | { | |
531 | if (!port->power_off) | |
532 | return; | |
533 | ||
534 | port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); | |
535 | port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); | |
536 | port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); | |
537 | port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); | |
538 | port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); | |
539 | port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); | |
540 | } | |
541 | ||
542 | static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) | |
543 | { | |
544 | if (!port->power_off) | |
545 | return; | |
546 | ||
547 | writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); | |
548 | writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); | |
549 | writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); | |
550 | writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); | |
551 | writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); | |
552 | writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); | |
553 | } | |
554 | ||
1a5287a3 | 555 | static int mxc_gpio_syscore_suspend(void) |
c19fdaee | 556 | { |
1a5287a3 | 557 | struct mxc_gpio_port *port; |
c19fdaee | 558 | |
1a5287a3 AH |
559 | /* walk through all ports */ |
560 | list_for_each_entry(port, &mxc_gpio_ports, node) { | |
561 | mxc_gpio_save_regs(port); | |
562 | clk_disable_unprepare(port->clk); | |
563 | } | |
c19fdaee AH |
564 | |
565 | return 0; | |
566 | } | |
567 | ||
1a5287a3 | 568 | static void mxc_gpio_syscore_resume(void) |
c19fdaee | 569 | { |
1a5287a3 | 570 | struct mxc_gpio_port *port; |
c19fdaee AH |
571 | int ret; |
572 | ||
1a5287a3 AH |
573 | /* walk through all ports */ |
574 | list_for_each_entry(port, &mxc_gpio_ports, node) { | |
575 | ret = clk_prepare_enable(port->clk); | |
576 | if (ret) { | |
577 | pr_err("mxc: failed to enable gpio clock %d\n", ret); | |
578 | return; | |
579 | } | |
580 | mxc_gpio_restore_regs(port); | |
581 | } | |
c19fdaee AH |
582 | } |
583 | ||
1a5287a3 AH |
584 | static struct syscore_ops mxc_gpio_syscore_ops = { |
585 | .suspend = mxc_gpio_syscore_suspend, | |
586 | .resume = mxc_gpio_syscore_resume, | |
c19fdaee AH |
587 | }; |
588 | ||
b78d8e59 SG |
589 | static struct platform_driver mxc_gpio_driver = { |
590 | .driver = { | |
591 | .name = "gpio-mxc", | |
8937cb60 | 592 | .of_match_table = mxc_gpio_dt_ids, |
90e1fc4c | 593 | .suppress_bind_attrs = true, |
b78d8e59 SG |
594 | }, |
595 | .probe = mxc_gpio_probe, | |
e7fc6ae7 | 596 | .id_table = mxc_gpio_devtype, |
b78d8e59 SG |
597 | }; |
598 | ||
599 | static int __init gpio_mxc_init(void) | |
600 | { | |
1a5287a3 AH |
601 | register_syscore_ops(&mxc_gpio_syscore_ops); |
602 | ||
b78d8e59 SG |
603 | return platform_driver_register(&mxc_gpio_driver); |
604 | } | |
e188cbf7 | 605 | subsys_initcall(gpio_mxc_init); |