[linux-2.6-block.git] / drivers / gpio / gpio-mxc.c

// SPDX-License-Identifier: GPL-2.0+
//
// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
//
// Based on code from Freescale Semiconductor,
// Authors: Daniel Mack, Juergen Beisert.
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/bug.h>

enum mxc_gpio_hwtype {
	IMX1_GPIO,	/* runs on i.mx1 */
	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
	IMX31_GPIO,	/* runs on i.mx31 */
	IMX35_GPIO,	/* runs on all other i.mx */
};

/* device type dependent stuff */
struct mxc_gpio_hwdata {
	unsigned dr_reg;
	unsigned gdir_reg;
	unsigned psr_reg;
	unsigned icr1_reg;
	unsigned icr2_reg;
	unsigned imr_reg;
	unsigned isr_reg;
	int edge_sel_reg;
	unsigned low_level;
	unsigned high_level;
	unsigned rise_edge;
	unsigned fall_edge;
};

struct mxc_gpio_reg_saved {
	u32 icr1;
	u32 icr2;
	u32 imr;
	u32 gdir;
	u32 edge_sel;
	u32 dr;
};

struct mxc_gpio_port {
	struct list_head node;
	void __iomem *base;
	struct clk *clk;
	int irq;
	int irq_high;
	struct irq_domain *domain;
	struct gpio_chip gc;
	struct device *dev;
	u32 both_edges;
	struct mxc_gpio_reg_saved gpio_saved_reg;
	bool power_off;
};

static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	.dr_reg		= 0x1c,
	.gdir_reg	= 0x00,
	.psr_reg	= 0x24,
	.icr1_reg	= 0x28,
	.icr2_reg	= 0x2c,
	.imr_reg	= 0x30,
	.isr_reg	= 0x34,
	.edge_sel_reg	= -EINVAL,
	.low_level	= 0x03,
	.high_level	= 0x02,
	.rise_edge	= 0x00,
	.fall_edge	= 0x01,
};

static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	.dr_reg		= 0x00,
	.gdir_reg	= 0x04,
	.psr_reg	= 0x08,
	.icr1_reg	= 0x0c,
	.icr2_reg	= 0x10,
	.imr_reg	= 0x14,
	.isr_reg	= 0x18,
	.edge_sel_reg	= -EINVAL,
	.low_level	= 0x00,
	.high_level	= 0x01,
	.rise_edge	= 0x02,
	.fall_edge	= 0x03,
};

static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
	.dr_reg		= 0x00,
	.gdir_reg	= 0x04,
	.psr_reg	= 0x08,
	.icr1_reg	= 0x0c,
	.icr2_reg	= 0x10,
	.imr_reg	= 0x14,
	.isr_reg	= 0x18,
	.edge_sel_reg	= 0x1c,
	.low_level	= 0x00,
	.high_level	= 0x01,
	.rise_edge	= 0x02,
	.fall_edge	= 0x03,
};

static enum mxc_gpio_hwtype mxc_gpio_hwtype;
static struct mxc_gpio_hwdata *mxc_gpio_hwdata;

#define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
#define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
#define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
#define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
#define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
#define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
#define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)
#define GPIO_EDGE_SEL		(mxc_gpio_hwdata->edge_sel_reg)

#define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
#define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
#define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
#define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
#define GPIO_INT_BOTH_EDGES	0x4

static const struct platform_device_id mxc_gpio_devtype[] = {
	{
		.name = "imx1-gpio",
		.driver_data = IMX1_GPIO,
	}, {
		.name = "imx21-gpio",
		.driver_data = IMX21_GPIO,
	}, {
		.name = "imx31-gpio",
		.driver_data = IMX31_GPIO,
	}, {
		.name = "imx35-gpio",
		.driver_data = IMX35_GPIO,
	}, {
		/* sentinel */
	}
};

static const struct of_device_id mxc_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
	{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
	{ .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
	{ /* sentinel */ }
};

/*
 * MX2 has one interrupt *for all* gpio ports. The list is used
 * to save the references to all ports, so that mx2_gpio_irq_handler
 * can walk through all interrupt status registers.
 */
static LIST_HEAD(mxc_gpio_ports);

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 bit, val;
	u32 gpio_idx = d->hwirq;
	int edge;
	void __iomem *reg = port->base;

	port->both_edges &= ~(1 << gpio_idx);
	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (GPIO_EDGE_SEL >= 0) {
			edge = GPIO_INT_BOTH_EDGES;
		} else {
			val = port->gc.get(&port->gc, gpio_idx);
			if (val) {
				edge = GPIO_INT_LOW_LEV;
				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
			} else {
				edge = GPIO_INT_HIGH_LEV;
				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
			}
			port->both_edges |= 1 << gpio_idx;
		}
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	if (GPIO_EDGE_SEL >= 0) {
		val = readl(port->base + GPIO_EDGE_SEL);
		if (edge == GPIO_INT_BOTH_EDGES)
			writel(val | (1 << gpio_idx),
				port->base + GPIO_EDGE_SEL);
		else
			writel(val & ~(1 << gpio_idx),
				port->base + GPIO_EDGE_SEL);
	}

	if (edge != GPIO_INT_BOTH_EDGES) {
		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
		bit = gpio_idx & 0xf;
		val = readl(reg) & ~(0x3 << (bit << 1));
		writel(val | (edge << (bit << 1)), reg);
	}

	writel(1 << gpio_idx, port->base + GPIO_ISR);

	return 0;
}

static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
{
	void __iomem *reg = port->base;
	u32 bit, val;
	int edge;

	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	bit = gpio & 0xf;
	val = readl(reg);
	edge = (val >> (bit << 1)) & 3;
	val &= ~(0x3 << (bit << 1));
	if (edge == GPIO_INT_HIGH_LEV) {
		edge = GPIO_INT_LOW_LEV;
		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
	} else if (edge == GPIO_INT_LOW_LEV) {
		edge = GPIO_INT_HIGH_LEV;
		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
	} else {
		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
		       gpio, edge);
		return;
	}
	writel(val | (edge << (bit << 1)), reg);
}

/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;

		if (port->both_edges & (1 << irqoffset))
			mxc_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));

		irq_stat &= ~(1 << irqoffset);
	}
}

/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);

	mxc_gpio_irq_handler(port, irq_stat);

	chained_irq_exit(chip, desc);
}

/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_msk, irq_stat;
	struct mxc_gpio_port *port;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	/* walk through all interrupt status registers */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		irq_msk = readl(port->base + GPIO_IMR);
		if (!irq_msk)
			continue;

		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
		if (irq_stat)
			mxc_gpio_irq_handler(port, irq_stat);
	}
	chained_irq_exit(chip, desc);
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 gpio_idx = d->hwirq;
	int ret;

	if (enable) {
		if (port->irq_high && (gpio_idx >= 16))
			ret = enable_irq_wake(port->irq_high);
		else
			ret = enable_irq_wake(port->irq);
	} else {
		if (port->irq_high && (gpio_idx >= 16))
			ret = disable_irq_wake(port->irq_high);
		else
			ret = disable_irq_wake(port->irq);
	}

	return ret;
}

static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
					 port->base, handle_level_irq);
	if (!gc)
		return -ENOMEM;
	gc->private = port;

	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = gpio_set_irq_type;
	ct->chip.irq_set_wake = gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
	ct->regs.ack = GPIO_ISR;
	ct->regs.mask = GPIO_IMR;

	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
					 IRQ_GC_INIT_NESTED_LOCK,
					 IRQ_NOREQUEST, 0);

	return rv;
}

static void mxc_gpio_get_hw(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
	enum mxc_gpio_hwtype hwtype;

	if (of_id)
		pdev->id_entry = of_id->data;
	hwtype = pdev->id_entry->driver_data;

	if (mxc_gpio_hwtype) {
		/*
		 * The driver works with a reasonable presupposition,
		 * that is all gpio ports must be the same type when
		 * running on one soc.
		 */
		BUG_ON(mxc_gpio_hwtype != hwtype);
		return;
	}

	if (hwtype == IMX35_GPIO)
		mxc_gpio_hwdata = &imx35_gpio_hwdata;
	else if (hwtype == IMX31_GPIO)
		mxc_gpio_hwdata = &imx31_gpio_hwdata;
	else
		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;

	mxc_gpio_hwtype = hwtype;
}

static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mxc_gpio_port *port = gpiochip_get_data(gc);

	return irq_find_mapping(port->domain, offset);
}

static int mxc_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxc_gpio_port *port;
	struct resource *iores;
	int irq_base;
	int err;

	mxc_gpio_get_hw(pdev);

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->dev = &pdev->dev;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	port->base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(port->base))
		return PTR_ERR(port->base);

	port->irq_high = platform_get_irq(pdev, 1);
	if (port->irq_high < 0)
		port->irq_high = 0;

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/* the controller clock is optional */
	port->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(port->clk)) {
		if (PTR_ERR(port->clk) == -EPROBE_DEFER)
			return -EPROBE_DEFER;
		port->clk = NULL;
	}

	err = clk_prepare_enable(port->clk);
	if (err) {
		dev_err(&pdev->dev, "Unable to enable clock.\n");
		return err;
	}

	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
		port->power_off = true;

	/* disable the interrupt and clear the status */
	writel(0, port->base + GPIO_IMR);
	writel(~0, port->base + GPIO_ISR);

	if (mxc_gpio_hwtype == IMX21_GPIO) {
		/*
		 * Setup one handler for all GPIO interrupts. Actually setting
		 * the handler is needed only once, but doing it for every port
		 * is more robust and easier.
		 */
		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
	} else {
		/* setup one handler for each entry */
		irq_set_chained_handler_and_data(port->irq,
						 mx3_gpio_irq_handler, port);
		if (port->irq_high > 0)
			/* setup handler for GPIO 16 to 31 */
			irq_set_chained_handler_and_data(port->irq_high,
							 mx3_gpio_irq_handler,
							 port);
	}

	err = bgpio_init(&port->gc, &pdev->dev, 4,
			 port->base + GPIO_PSR,
			 port->base + GPIO_DR, NULL,
			 port->base + GPIO_GDIR, NULL,
			 BGPIOF_READ_OUTPUT_REG_SET);
	if (err)
		goto out_bgio;

	if (of_property_read_bool(np, "gpio-ranges")) {
		port->gc.request = gpiochip_generic_request;
		port->gc.free = gpiochip_generic_free;
	}

	port->gc.to_irq = mxc_gpio_to_irq;
	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
					     pdev->id * 32;

	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
	if (err)
		goto out_bgio;

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
	if (irq_base < 0) {
		err = irq_base;
		goto out_bgio;
	}

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_bgio;
	}

	/* gpio-mxc can be a generic irq chip */
	err = mxc_gpio_init_gc(port, irq_base);
	if (err < 0)
		goto out_irqdomain_remove;

	list_add_tail(&port->node, &mxc_gpio_ports);

	platform_set_drvdata(pdev, port);

	return 0;

out_irqdomain_remove:
	irq_domain_remove(port->domain);
out_bgio:
	clk_disable_unprepare(port->clk);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	return err;
}

static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
{
	if (!port->power_off)
		return;

	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
}

static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
{
	if (!port->power_off)
		return;

	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
}

static int mxc_gpio_syscore_suspend(void)
{
	struct mxc_gpio_port *port;

	/* walk through all ports */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		mxc_gpio_save_regs(port);
		clk_disable_unprepare(port->clk);
	}

	return 0;
}

static void mxc_gpio_syscore_resume(void)
{
	struct mxc_gpio_port *port;
	int ret;

	/* walk through all ports */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		ret = clk_prepare_enable(port->clk);
		if (ret) {
			pr_err("mxc: failed to enable gpio clock %d\n", ret);
			return;
		}
		mxc_gpio_restore_regs(port);
	}
}

static struct syscore_ops mxc_gpio_syscore_ops = {
	.suspend = mxc_gpio_syscore_suspend,
	.resume = mxc_gpio_syscore_resume,
};

static struct platform_driver mxc_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxc",
		.of_match_table = mxc_gpio_dt_ids,
		.suppress_bind_attrs = true,
	},
	.probe		= mxc_gpio_probe,
	.id_table	= mxc_gpio_devtype,
};

static int __init gpio_mxc_init(void)
{
	register_syscore_ops(&mxc_gpio_syscore_ops);

	return platform_driver_register(&mxc_gpio_driver);
}
subsys_initcall(gpio_mxc_init);
Commit	Line	Data
014e420d FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	4	// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	5	//
	6	// Based on code from Freescale Semiconductor,
	7	// Authors: Daniel Mack, Juergen Beisert.
	8	// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
07bd1a6c	9
2808801a	10	#include <linux/clk.h>
18f92b19	11	#include <linux/err.h>
07bd1a6c	12	#include <linux/init.h>
a3484ffd	13	#include <linux/interrupt.h>
07bd1a6c JB	14	#include <linux/io.h>
07bd1a6c JB	15	#include <linux/irq.h>
1ab7ef15	16	#include <linux/irqdomain.h>
de88cbb7	17	#include <linux/irqchip/chained_irq.h>
b78d8e59 SG	18	#include <linux/platform_device.h>
b78d8e59 SG	19	#include <linux/slab.h>
1a5287a3	20	#include <linux/syscore_ops.h>
0f4630f3	21	#include <linux/gpio/driver.h>
8937cb60 SG	22	#include <linux/of.h>
8937cb60 SG	23	#include <linux/of_device.h>
16c3bd35	24	#include <linux/bug.h>
07bd1a6c	25
e7fc6ae7 SG	26	enum mxc_gpio_hwtype {
	27	IMX1_GPIO, /* runs on i.mx1 */
	28	IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
aeb27748 BT	29	IMX31_GPIO, /* runs on i.mx31 */
aeb27748 BT	30	IMX35_GPIO, /* runs on all other i.mx */
e7fc6ae7 SG	31	};
	32
	33	/* device type dependent stuff */
	34	struct mxc_gpio_hwdata {
	35	unsigned dr_reg;
	36	unsigned gdir_reg;
	37	unsigned psr_reg;
	38	unsigned icr1_reg;
	39	unsigned icr2_reg;
	40	unsigned imr_reg;
	41	unsigned isr_reg;
aeb27748	42	int edge_sel_reg;
e7fc6ae7 SG	43	unsigned low_level;
	44	unsigned high_level;
	45	unsigned rise_edge;
	46	unsigned fall_edge;
	47	};
	48
c19fdaee AH	49	struct mxc_gpio_reg_saved {
	50	u32 icr1;
	51	u32 icr2;
	52	u32 imr;
	53	u32 gdir;
	54	u32 edge_sel;
	55	u32 dr;
	56	};
	57
b78d8e59 SG	58	struct mxc_gpio_port {
	59	struct list_head node;
	60	void __iomem *base;
2808801a	61	struct clk *clk;
b78d8e59 SG	62	int irq;
b78d8e59 SG	63	int irq_high;
1ab7ef15	64	struct irq_domain *domain;
0f4630f3	65	struct gpio_chip gc;
db5270ac	66	struct device *dev;
b78d8e59	67	u32 both_edges;
c19fdaee AH	68	struct mxc_gpio_reg_saved gpio_saved_reg;
c19fdaee AH	69	bool power_off;
b78d8e59 SG	70	};
b78d8e59 SG	71
e7fc6ae7 SG	72	static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	73	.dr_reg = 0x1c,
	74	.gdir_reg = 0x00,
	75	.psr_reg = 0x24,
	76	.icr1_reg = 0x28,
	77	.icr2_reg = 0x2c,
	78	.imr_reg = 0x30,
	79	.isr_reg = 0x34,
aeb27748	80	.edge_sel_reg = -EINVAL,
e7fc6ae7 SG	81	.low_level = 0x03,
	82	.high_level = 0x02,
	83	.rise_edge = 0x00,
	84	.fall_edge = 0x01,
	85	};
	86
	87	static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	88	.dr_reg = 0x00,
	89	.gdir_reg = 0x04,
	90	.psr_reg = 0x08,
	91	.icr1_reg = 0x0c,
	92	.icr2_reg = 0x10,
	93	.imr_reg = 0x14,
	94	.isr_reg = 0x18,
aeb27748 BT	95	.edge_sel_reg = -EINVAL,
	96	.low_level = 0x00,
	97	.high_level = 0x01,
	98	.rise_edge = 0x02,
	99	.fall_edge = 0x03,
	100	};
	101
	102	static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
	103	.dr_reg = 0x00,
	104	.gdir_reg = 0x04,
	105	.psr_reg = 0x08,
	106	.icr1_reg = 0x0c,
	107	.icr2_reg = 0x10,
	108	.imr_reg = 0x14,
	109	.isr_reg = 0x18,
	110	.edge_sel_reg = 0x1c,
e7fc6ae7 SG	111	.low_level = 0x00,
	112	.high_level = 0x01,
	113	.rise_edge = 0x02,
	114	.fall_edge = 0x03,
	115	};
	116
	117	static enum mxc_gpio_hwtype mxc_gpio_hwtype;
	118	static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
	119
	120	#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
	121	#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
	122	#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
	123	#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
	124	#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
	125	#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
	126	#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
aeb27748	127	#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
e7fc6ae7 SG	128
	129	#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
	130	#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
	131	#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
	132	#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
aeb27748	133	#define GPIO_INT_BOTH_EDGES 0x4
e7fc6ae7	134
f4f79d40	135	static const struct platform_device_id mxc_gpio_devtype[] = {
e7fc6ae7 SG	136	{
	137	.name = "imx1-gpio",
	138	.driver_data = IMX1_GPIO,
	139	}, {
	140	.name = "imx21-gpio",
	141	.driver_data = IMX21_GPIO,
	142	}, {
	143	.name = "imx31-gpio",
	144	.driver_data = IMX31_GPIO,
aeb27748 BT	145	}, {
	146	.name = "imx35-gpio",
	147	.driver_data = IMX35_GPIO,
e7fc6ae7 SG	148	}, {
	149	/* sentinel */
	150	}
	151	};
	152
8937cb60 SG	153	static const struct of_device_id mxc_gpio_dt_ids[] = {
	154	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
	155	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
	156	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
aeb27748	157	{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
c19fdaee	158	{ .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
8937cb60 SG	159	{ /* sentinel */ }
	160	};
	161
b78d8e59 SG	162	/*
	163	* MX2 has one interrupt for all gpio ports. The list is used
	164	* to save the references to all ports, so that mx2_gpio_irq_handler
	165	* can walk through all interrupt status registers.
	166	*/
	167	static LIST_HEAD(mxc_gpio_ports);
07bd1a6c JB	168
	169	/* Note: This driver assumes 32 GPIOs are handled in one register */
	170
4d93579f	171	static int gpio_set_irq_type(struct irq_data *d, u32 type)
07bd1a6c	172	{
e4ea9333 SG	173	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	174	struct mxc_gpio_port *port = gc->private;
07bd1a6c	175	u32 bit, val;
1ab7ef15	176	u32 gpio_idx = d->hwirq;
07bd1a6c JB	177	int edge;
	178	void __iomem *reg = port->base;
	179
1ab7ef15	180	port->both_edges &= ~(1 << gpio_idx);
07bd1a6c	181	switch (type) {
6cab4860	182	case IRQ_TYPE_EDGE_RISING:
07bd1a6c JB	183	edge = GPIO_INT_RISE_EDGE;
07bd1a6c JB	184	break;
6cab4860	185	case IRQ_TYPE_EDGE_FALLING:
07bd1a6c JB	186	edge = GPIO_INT_FALL_EDGE;
07bd1a6c JB	187	break;
910862ec	188	case IRQ_TYPE_EDGE_BOTH:
aeb27748 BT	189	if (GPIO_EDGE_SEL >= 0) {
aeb27748 BT	190	edge = GPIO_INT_BOTH_EDGES;
910862ec	191	} else {
8d0bd9a5	192	val = port->gc.get(&port->gc, gpio_idx);
aeb27748 BT	193	if (val) {
aeb27748 BT	194	edge = GPIO_INT_LOW_LEV;
8d0bd9a5	195	pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
aeb27748 BT	196	} else {
aeb27748 BT	197	edge = GPIO_INT_HIGH_LEV;
8d0bd9a5	198	pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
aeb27748	199	}
f948ad07	200	port->both_edges \|= 1 << gpio_idx;
910862ec	201	}
910862ec	202	break;
6cab4860	203	case IRQ_TYPE_LEVEL_LOW:
07bd1a6c JB	204	edge = GPIO_INT_LOW_LEV;
07bd1a6c JB	205	break;
6cab4860	206	case IRQ_TYPE_LEVEL_HIGH:
07bd1a6c JB	207	edge = GPIO_INT_HIGH_LEV;
07bd1a6c JB	208	break;
910862ec	209	default:
07bd1a6c JB	210	return -EINVAL;
	211	}
	212
aeb27748 BT	213	if (GPIO_EDGE_SEL >= 0) {
	214	val = readl(port->base + GPIO_EDGE_SEL);
	215	if (edge == GPIO_INT_BOTH_EDGES)
f948ad07	216	writel(val \| (1 << gpio_idx),
aeb27748 BT	217	port->base + GPIO_EDGE_SEL);
aeb27748 BT	218	else
f948ad07	219	writel(val & ~(1 << gpio_idx),
aeb27748 BT	220	port->base + GPIO_EDGE_SEL);
	221	}
	222
	223	if (edge != GPIO_INT_BOTH_EDGES) {
f948ad07 LT	224	reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
f948ad07 LT	225	bit = gpio_idx & 0xf;
aeb27748 BT	226	val = readl(reg) & ~(0x3 << (bit << 1));
	227	writel(val \| (edge << (bit << 1)), reg);
	228	}
	229
1ab7ef15	230	writel(1 << gpio_idx, port->base + GPIO_ISR);
07bd1a6c JB	231
	232	return 0;
	233	}
	234
910862ec GL	235	static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
	236	{
	237	void __iomem *reg = port->base;
	238	u32 bit, val;
	239	int edge;
	240
	241	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	242	bit = gpio & 0xf;
b78d8e59	243	val = readl(reg);
910862ec GL	244	edge = (val >> (bit << 1)) & 3;
910862ec GL	245	val &= ~(0x3 << (bit << 1));
3d40f7fe	246	if (edge == GPIO_INT_HIGH_LEV) {
910862ec GL	247	edge = GPIO_INT_LOW_LEV;
910862ec GL	248	pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
3d40f7fe	249	} else if (edge == GPIO_INT_LOW_LEV) {
910862ec GL	250	edge = GPIO_INT_HIGH_LEV;
910862ec GL	251	pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
3d40f7fe	252	} else {
910862ec GL	253	pr_err("mxc: invalid configuration for GPIO %d: %x\n",
	254	gpio, edge);
	255	return;
	256	}
b78d8e59	257	writel(val \| (edge << (bit << 1)), reg);
910862ec GL	258	}
910862ec GL	259
3621f188	260	/* handle 32 interrupts in one status register */
07bd1a6c JB	261	static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
07bd1a6c JB	262	{
3621f188 UKK	263	while (irq_stat != 0) {
3621f188 UKK	264	int irqoffset = fls(irq_stat) - 1;
07bd1a6c	265
3621f188 UKK	266	if (port->both_edges & (1 << irqoffset))
3621f188 UKK	267	mxc_flip_edge(port, irqoffset);
910862ec	268
1ab7ef15	269	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
910862ec	270
3621f188	271	irq_stat &= ~(1 << irqoffset);
07bd1a6c JB	272	}
	273	}
	274
cfca8b53	275	/* MX1 and MX3 has one interrupt per gpio port */
bd0b9ac4	276	static void mx3_gpio_irq_handler(struct irq_desc *desc)
07bd1a6c JB	277	{
07bd1a6c JB	278	u32 irq_stat;
476f8b4c JL	279	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
476f8b4c JL	280	struct irq_chip *chip = irq_desc_get_chip(desc);
0e44b6ec SG	281
0e44b6ec SG	282	chained_irq_enter(chip, desc);
07bd1a6c	283
b78d8e59	284	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
e2c97e7f	285
07bd1a6c	286	mxc_gpio_irq_handler(port, irq_stat);
0e44b6ec SG	287
0e44b6ec SG	288	chained_irq_exit(chip, desc);
07bd1a6c	289	}
07bd1a6c	290
07bd1a6c	291	/* MX2 has one interrupt for all gpio ports */
bd0b9ac4	292	static void mx2_gpio_irq_handler(struct irq_desc *desc)
07bd1a6c	293	{
07bd1a6c	294	u32 irq_msk, irq_stat;
b78d8e59	295	struct mxc_gpio_port *port;
476f8b4c	296	struct irq_chip *chip = irq_desc_get_chip(desc);
c0e811d9 UKK	297
c0e811d9 UKK	298	chained_irq_enter(chip, desc);
07bd1a6c JB	299
07bd1a6c JB	300	/* walk through all interrupt status registers */
b78d8e59 SG	301	list_for_each_entry(port, &mxc_gpio_ports, node) {
b78d8e59 SG	302	irq_msk = readl(port->base + GPIO_IMR);
07bd1a6c JB	303	if (!irq_msk)
	304	continue;
	305
b78d8e59	306	irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
07bd1a6c	307	if (irq_stat)
b78d8e59	308	mxc_gpio_irq_handler(port, irq_stat);
07bd1a6c	309	}
c0e811d9	310	chained_irq_exit(chip, desc);
07bd1a6c	311	}
07bd1a6c	312
a3484ffd DN	313	/*
	314	* Set interrupt number "irq" in the GPIO as a wake-up source.
	315	* While system is running, all registered GPIO interrupts need to have
	316	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	317	* need to have wake-up enabled.
	318	* @param irq interrupt source number
	319	* @param enable enable as wake-up if equal to non-zero
	320	* @return This function returns 0 on success.
	321	*/
4d93579f	322	static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
a3484ffd	323	{
e4ea9333 SG	324	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	325	struct mxc_gpio_port *port = gc->private;
1ab7ef15	326	u32 gpio_idx = d->hwirq;
77a4d757	327	int ret;
a3484ffd DN	328
	329	if (enable) {
	330	if (port->irq_high && (gpio_idx >= 16))
77a4d757	331	ret = enable_irq_wake(port->irq_high);
a3484ffd	332	else
77a4d757	333	ret = enable_irq_wake(port->irq);
a3484ffd DN	334	} else {
a3484ffd DN	335	if (port->irq_high && (gpio_idx >= 16))
77a4d757	336	ret = disable_irq_wake(port->irq_high);
a3484ffd	337	else
77a4d757	338	ret = disable_irq_wake(port->irq);
a3484ffd DN	339	}
a3484ffd DN	340
77a4d757	341	return ret;
a3484ffd DN	342	}
a3484ffd DN	343
9e26b0b1	344	static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
e4ea9333 SG	345	{
	346	struct irq_chip_generic *gc;
	347	struct irq_chip_type *ct;
db5270ac	348	int rv;
e4ea9333	349
db5270ac BG	350	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
db5270ac BG	351	port->base, handle_level_irq);
9e26b0b1 PF	352	if (!gc)
9e26b0b1 PF	353	return -ENOMEM;
e4ea9333 SG	354	gc->private = port;
	355
	356	ct = gc->chip_types;
591567a5	357	ct->chip.irq_ack = irq_gc_ack_set_bit;
e4ea9333 SG	358	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	359	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	360	ct->chip.irq_set_type = gpio_set_irq_type;
591567a5	361	ct->chip.irq_set_wake = gpio_set_wake_irq;
952cfbd3	362	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
e4ea9333 SG	363	ct->regs.ack = GPIO_ISR;
	364	ct->regs.mask = GPIO_IMR;
	365
db5270ac BG	366	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
	367	IRQ_GC_INIT_NESTED_LOCK,
	368	IRQ_NOREQUEST, 0);
9e26b0b1	369
db5270ac	370	return rv;
e4ea9333	371	}
b5eee2fd	372
3836309d	373	static void mxc_gpio_get_hw(struct platform_device *pdev)
e7fc6ae7	374	{
8937cb60 SG	375	const struct of_device_id *of_id =
	376	of_match_device(mxc_gpio_dt_ids, &pdev->dev);
	377	enum mxc_gpio_hwtype hwtype;
	378
	379	if (of_id)
	380	pdev->id_entry = of_id->data;
	381	hwtype = pdev->id_entry->driver_data;
e7fc6ae7 SG	382
	383	if (mxc_gpio_hwtype) {
	384	/*
	385	* The driver works with a reasonable presupposition,
	386	* that is all gpio ports must be the same type when
	387	* running on one soc.
	388	*/
	389	BUG_ON(mxc_gpio_hwtype != hwtype);
	390	return;
	391	}
	392
aeb27748 BT	393	if (hwtype == IMX35_GPIO)
	394	mxc_gpio_hwdata = &imx35_gpio_hwdata;
	395	else if (hwtype == IMX31_GPIO)
e7fc6ae7 SG	396	mxc_gpio_hwdata = &imx31_gpio_hwdata;
	397	else
	398	mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
	399
	400	mxc_gpio_hwtype = hwtype;
	401	}
	402
09ad8039 SG	403	static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
09ad8039 SG	404	{
0f4630f3	405	struct mxc_gpio_port *port = gpiochip_get_data(gc);
09ad8039	406
1ab7ef15	407	return irq_find_mapping(port->domain, offset);
09ad8039 SG	408	}
09ad8039 SG	409
3836309d	410	static int mxc_gpio_probe(struct platform_device *pdev)
07bd1a6c	411	{
8937cb60	412	struct device_node *np = pdev->dev.of_node;
b78d8e59 SG	413	struct mxc_gpio_port *port;
b78d8e59 SG	414	struct resource *iores;
1ab7ef15	415	int irq_base;
e4ea9333	416	int err;
b78d8e59	417
e7fc6ae7 SG	418	mxc_gpio_get_hw(pdev);
e7fc6ae7 SG	419
8cd73e4e	420	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
b78d8e59 SG	421	if (!port)
b78d8e59 SG	422	return -ENOMEM;
07bd1a6c	423
db5270ac BG	424	port->dev = &pdev->dev;
db5270ac BG	425
b78d8e59	426	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cd73e4e FE	427	port->base = devm_ioremap_resource(&pdev->dev, iores);
	428	if (IS_ERR(port->base))
	429	return PTR_ERR(port->base);
b78d8e59 SG	430
b78d8e59 SG	431	port->irq_high = platform_get_irq(pdev, 1);
cc9269f8 PR	432	if (port->irq_high < 0)
	433	port->irq_high = 0;
	434
b78d8e59	435	port->irq = platform_get_irq(pdev, 0);
8cd73e4e	436	if (port->irq < 0)
5ea80e49	437	return port->irq;
b78d8e59	438
2808801a AH	439	/* the controller clock is optional */
2808801a AH	440	port->clk = devm_clk_get(&pdev->dev, NULL);
a329bbe7 AH	441	if (IS_ERR(port->clk)) {
	442	if (PTR_ERR(port->clk) == -EPROBE_DEFER)
	443	return -EPROBE_DEFER;
2808801a	444	port->clk = NULL;
a329bbe7	445	}
2808801a AH	446
	447	err = clk_prepare_enable(port->clk);
	448	if (err) {
	449	dev_err(&pdev->dev, "Unable to enable clock.\n");
	450	return err;
	451	}
	452
c19fdaee AH	453	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
	454	port->power_off = true;
	455
b78d8e59 SG	456	/* disable the interrupt and clear the status */
	457	writel(0, port->base + GPIO_IMR);
	458	writel(~0, port->base + GPIO_ISR);
	459
e7fc6ae7	460	if (mxc_gpio_hwtype == IMX21_GPIO) {
33a4e985 UKK	461	/*
	462	* Setup one handler for all GPIO interrupts. Actually setting
	463	* the handler is needed only once, but doing it for every port
	464	* is more robust and easier.
	465	*/
	466	irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
b78d8e59 SG	467	} else {
b78d8e59 SG	468	/* setup one handler for each entry */
e65eea54 RK	469	irq_set_chained_handler_and_data(port->irq,
	470	mx3_gpio_irq_handler, port);
	471	if (port->irq_high > 0)
b78d8e59	472	/* setup handler for GPIO 16 to 31 */
e65eea54 RK	473	irq_set_chained_handler_and_data(port->irq_high,
	474	mx3_gpio_irq_handler,
	475	port);
07bd1a6c JB	476	}
07bd1a6c JB	477
0f4630f3	478	err = bgpio_init(&port->gc, &pdev->dev, 4,
2ce420da SG	479	port->base + GPIO_PSR,
2ce420da SG	480	port->base + GPIO_DR, NULL,
442b2494 VZ	481	port->base + GPIO_GDIR, NULL,
442b2494 VZ	482	BGPIOF_READ_OUTPUT_REG_SET);
2ce420da	483	if (err)
8cd73e4e	484	goto out_bgio;
b78d8e59	485
4c806c98 VZ	486	if (of_property_read_bool(np, "gpio-ranges")) {
	487	port->gc.request = gpiochip_generic_request;
	488	port->gc.free = gpiochip_generic_free;
	489	}
	490
0f4630f3 LW	491	port->gc.to_irq = mxc_gpio_to_irq;
0f4630f3 LW	492	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
7e6086d9	493	pdev->id * 32;
b78d8e59	494
ffc56630	495	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
b78d8e59	496	if (err)
0f4630f3	497	goto out_bgio;
b78d8e59	498
c553c3c4	499	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
1ab7ef15 SG	500	if (irq_base < 0) {
1ab7ef15 SG	501	err = irq_base;
ffc56630	502	goto out_bgio;
1ab7ef15 SG	503	}
	504
	505	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	506	&irq_domain_simple_ops, NULL);
	507	if (!port->domain) {
	508	err = -ENODEV;
c553c3c4	509	goto out_bgio;
1ab7ef15	510	}
8937cb60 SG	511
8937cb60 SG	512	/* gpio-mxc can be a generic irq chip */
9e26b0b1 PF	513	err = mxc_gpio_init_gc(port, irq_base);
	514	if (err < 0)
	515	goto out_irqdomain_remove;
8937cb60	516
b78d8e59 SG	517	list_add_tail(&port->node, &mxc_gpio_ports);
b78d8e59 SG	518
c19fdaee AH	519	platform_set_drvdata(pdev, port);
c19fdaee AH	520
07bd1a6c	521	return 0;
b78d8e59	522
9e26b0b1 PF	523	out_irqdomain_remove:
9e26b0b1 PF	524	irq_domain_remove(port->domain);
8cd73e4e	525	out_bgio:
2808801a	526	clk_disable_unprepare(port->clk);
b78d8e59 SG	527	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
b78d8e59 SG	528	return err;
07bd1a6c	529	}
b78d8e59	530
c19fdaee AH	531	static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
	532	{
	533	if (!port->power_off)
	534	return;
	535
	536	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
	537	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
	538	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
	539	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
	540	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
	541	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
	542	}
	543
	544	static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
	545	{
	546	if (!port->power_off)
	547	return;
	548
	549	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
	550	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
	551	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
	552	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
	553	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
	554	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
	555	}
	556
1a5287a3	557	static int mxc_gpio_syscore_suspend(void)
c19fdaee	558	{
1a5287a3	559	struct mxc_gpio_port *port;
c19fdaee	560
1a5287a3 AH	561	/* walk through all ports */
	562	list_for_each_entry(port, &mxc_gpio_ports, node) {
	563	mxc_gpio_save_regs(port);
	564	clk_disable_unprepare(port->clk);
	565	}
c19fdaee AH	566
	567	return 0;
	568	}
	569
1a5287a3	570	static void mxc_gpio_syscore_resume(void)
c19fdaee	571	{
1a5287a3	572	struct mxc_gpio_port *port;
c19fdaee AH	573	int ret;
c19fdaee AH	574
1a5287a3 AH	575	/* walk through all ports */
	576	list_for_each_entry(port, &mxc_gpio_ports, node) {
	577	ret = clk_prepare_enable(port->clk);
	578	if (ret) {
	579	pr_err("mxc: failed to enable gpio clock %d\n", ret);
	580	return;
	581	}
	582	mxc_gpio_restore_regs(port);
	583	}
c19fdaee AH	584	}
c19fdaee AH	585
1a5287a3 AH	586	static struct syscore_ops mxc_gpio_syscore_ops = {
	587	.suspend = mxc_gpio_syscore_suspend,
	588	.resume = mxc_gpio_syscore_resume,
c19fdaee AH	589	};
c19fdaee AH	590
b78d8e59 SG	591	static struct platform_driver mxc_gpio_driver = {
	592	.driver = {
	593	.name = "gpio-mxc",
8937cb60	594	.of_match_table = mxc_gpio_dt_ids,
90e1fc4c	595	.suppress_bind_attrs = true,
b78d8e59 SG	596	},
b78d8e59 SG	597	.probe = mxc_gpio_probe,
e7fc6ae7	598	.id_table = mxc_gpio_devtype,
b78d8e59 SG	599	};
	600
	601	static int __init gpio_mxc_init(void)
	602	{
1a5287a3 AH	603	register_syscore_ops(&mxc_gpio_syscore_ops);
1a5287a3 AH	604
b78d8e59 SG	605	return platform_driver_register(&mxc_gpio_driver);
b78d8e59 SG	606	}
e188cbf7	607	subsys_initcall(gpio_mxc_init);