[linux-2.6-block.git] / drivers / gpio / gpio-mxc.c

// SPDX-License-Identifier: GPL-2.0+
//
// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
//
// Based on code from Freescale Semiconductor,
// Authors: Daniel Mack, Juergen Beisert.
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/bug.h>

/* device type dependent stuff */
struct mxc_gpio_hwdata {
	unsigned dr_reg;
	unsigned gdir_reg;
	unsigned psr_reg;
	unsigned icr1_reg;
	unsigned icr2_reg;
	unsigned imr_reg;
	unsigned isr_reg;
	int edge_sel_reg;
	unsigned low_level;
	unsigned high_level;
	unsigned rise_edge;
	unsigned fall_edge;
};

struct mxc_gpio_reg_saved {
	u32 icr1;
	u32 icr2;
	u32 imr;
	u32 gdir;
	u32 edge_sel;
	u32 dr;
};

struct mxc_gpio_port {
	struct list_head node;
	void __iomem *base;
	struct clk *clk;
	int irq;
	int irq_high;
	struct irq_domain *domain;
	struct gpio_chip gc;
	struct device *dev;
	u32 both_edges;
	struct mxc_gpio_reg_saved gpio_saved_reg;
	bool power_off;
	const struct mxc_gpio_hwdata *hwdata;
};

static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	.dr_reg		= 0x1c,
	.gdir_reg	= 0x00,
	.psr_reg	= 0x24,
	.icr1_reg	= 0x28,
	.icr2_reg	= 0x2c,
	.imr_reg	= 0x30,
	.isr_reg	= 0x34,
	.edge_sel_reg	= -EINVAL,
	.low_level	= 0x03,
	.high_level	= 0x02,
	.rise_edge	= 0x00,
	.fall_edge	= 0x01,
};

static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	.dr_reg		= 0x00,
	.gdir_reg	= 0x04,
	.psr_reg	= 0x08,
	.icr1_reg	= 0x0c,
	.icr2_reg	= 0x10,
	.imr_reg	= 0x14,
	.isr_reg	= 0x18,
	.edge_sel_reg	= -EINVAL,
	.low_level	= 0x00,
	.high_level	= 0x01,
	.rise_edge	= 0x02,
	.fall_edge	= 0x03,
};

static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
	.dr_reg		= 0x00,
	.gdir_reg	= 0x04,
	.psr_reg	= 0x08,
	.icr1_reg	= 0x0c,
	.icr2_reg	= 0x10,
	.imr_reg	= 0x14,
	.isr_reg	= 0x18,
	.edge_sel_reg	= 0x1c,
	.low_level	= 0x00,
	.high_level	= 0x01,
	.rise_edge	= 0x02,
	.fall_edge	= 0x03,
};

#define GPIO_DR			(port->hwdata->dr_reg)
#define GPIO_GDIR		(port->hwdata->gdir_reg)
#define GPIO_PSR		(port->hwdata->psr_reg)
#define GPIO_ICR1		(port->hwdata->icr1_reg)
#define GPIO_ICR2		(port->hwdata->icr2_reg)
#define GPIO_IMR		(port->hwdata->imr_reg)
#define GPIO_ISR		(port->hwdata->isr_reg)
#define GPIO_EDGE_SEL		(port->hwdata->edge_sel_reg)

#define GPIO_INT_LOW_LEV	(port->hwdata->low_level)
#define GPIO_INT_HIGH_LEV	(port->hwdata->high_level)
#define GPIO_INT_RISE_EDGE	(port->hwdata->rise_edge)
#define GPIO_INT_FALL_EDGE	(port->hwdata->fall_edge)
#define GPIO_INT_BOTH_EDGES	0x4

static const struct of_device_id mxc_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx1-gpio", .data =  &imx1_imx21_gpio_hwdata },
	{ .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
	{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
	{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
	{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);

/*
 * MX2 has one interrupt *for all* gpio ports. The list is used
 * to save the references to all ports, so that mx2_gpio_irq_handler
 * can walk through all interrupt status registers.
 */
static LIST_HEAD(mxc_gpio_ports);

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 bit, val;
	u32 gpio_idx = d->hwirq;
	int edge;
	void __iomem *reg = port->base;

	port->both_edges &= ~(1 << gpio_idx);
	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (GPIO_EDGE_SEL >= 0) {
			edge = GPIO_INT_BOTH_EDGES;
		} else {
			val = port->gc.get(&port->gc, gpio_idx);
			if (val) {
				edge = GPIO_INT_LOW_LEV;
				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
			} else {
				edge = GPIO_INT_HIGH_LEV;
				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
			}
			port->both_edges |= 1 << gpio_idx;
		}
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	if (GPIO_EDGE_SEL >= 0) {
		val = readl(port->base + GPIO_EDGE_SEL);
		if (edge == GPIO_INT_BOTH_EDGES)
			writel(val | (1 << gpio_idx),
				port->base + GPIO_EDGE_SEL);
		else
			writel(val & ~(1 << gpio_idx),
				port->base + GPIO_EDGE_SEL);
	}

	if (edge != GPIO_INT_BOTH_EDGES) {
		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
		bit = gpio_idx & 0xf;
		val = readl(reg) & ~(0x3 << (bit << 1));
		writel(val | (edge << (bit << 1)), reg);
	}

	writel(1 << gpio_idx, port->base + GPIO_ISR);

	return 0;
}

static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
{
	void __iomem *reg = port->base;
	u32 bit, val;
	int edge;

	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	bit = gpio & 0xf;
	val = readl(reg);
	edge = (val >> (bit << 1)) & 3;
	val &= ~(0x3 << (bit << 1));
	if (edge == GPIO_INT_HIGH_LEV) {
		edge = GPIO_INT_LOW_LEV;
		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
	} else if (edge == GPIO_INT_LOW_LEV) {
		edge = GPIO_INT_HIGH_LEV;
		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
	} else {
		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
		       gpio, edge);
		return;
	}
	writel(val | (edge << (bit << 1)), reg);
}

/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;

		if (port->both_edges & (1 << irqoffset))
			mxc_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));

		irq_stat &= ~(1 << irqoffset);
	}
}

/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);

	mxc_gpio_irq_handler(port, irq_stat);

	chained_irq_exit(chip, desc);
}

/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_msk, irq_stat;
	struct mxc_gpio_port *port;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	/* walk through all interrupt status registers */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		irq_msk = readl(port->base + GPIO_IMR);
		if (!irq_msk)
			continue;

		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
		if (irq_stat)
			mxc_gpio_irq_handler(port, irq_stat);
	}
	chained_irq_exit(chip, desc);
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxc_gpio_port *port = gc->private;
	u32 gpio_idx = d->hwirq;
	int ret;

	if (enable) {
		if (port->irq_high && (gpio_idx >= 16))
			ret = enable_irq_wake(port->irq_high);
		else
			ret = enable_irq_wake(port->irq);
	} else {
		if (port->irq_high && (gpio_idx >= 16))
			ret = disable_irq_wake(port->irq_high);
		else
			ret = disable_irq_wake(port->irq);
	}

	return ret;
}

static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
					 port->base, handle_level_irq);
	if (!gc)
		return -ENOMEM;
	gc->private = port;

	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = gpio_set_irq_type;
	ct->chip.irq_set_wake = gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
	ct->regs.ack = GPIO_ISR;
	ct->regs.mask = GPIO_IMR;

	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
					 IRQ_GC_INIT_NESTED_LOCK,
					 IRQ_NOREQUEST, 0);

	return rv;
}

static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mxc_gpio_port *port = gpiochip_get_data(gc);

	return irq_find_mapping(port->domain, offset);
}

static int mxc_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxc_gpio_port *port;
	int irq_count;
	int irq_base;
	int err;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->dev = &pdev->dev;

	port->hwdata = device_get_match_data(&pdev->dev);

	port->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(port->base))
		return PTR_ERR(port->base);

	irq_count = platform_irq_count(pdev);
	if (irq_count < 0)
		return irq_count;

	if (irq_count > 1) {
		port->irq_high = platform_get_irq(pdev, 1);
		if (port->irq_high < 0)
			port->irq_high = 0;
	}

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/* the controller clock is optional */
	port->clk = devm_clk_get_optional(&pdev->dev, NULL);
	if (IS_ERR(port->clk))
		return PTR_ERR(port->clk);

	err = clk_prepare_enable(port->clk);
	if (err) {
		dev_err(&pdev->dev, "Unable to enable clock.\n");
		return err;
	}

	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
		port->power_off = true;

	/* disable the interrupt and clear the status */
	writel(0, port->base + GPIO_IMR);
	writel(~0, port->base + GPIO_ISR);

	if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
		/*
		 * Setup one handler for all GPIO interrupts. Actually setting
		 * the handler is needed only once, but doing it for every port
		 * is more robust and easier.
		 */
		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
	} else {
		/* setup one handler for each entry */
		irq_set_chained_handler_and_data(port->irq,
						 mx3_gpio_irq_handler, port);
		if (port->irq_high > 0)
			/* setup handler for GPIO 16 to 31 */
			irq_set_chained_handler_and_data(port->irq_high,
							 mx3_gpio_irq_handler,
							 port);
	}

	err = bgpio_init(&port->gc, &pdev->dev, 4,
			 port->base + GPIO_PSR,
			 port->base + GPIO_DR, NULL,
			 port->base + GPIO_GDIR, NULL,
			 BGPIOF_READ_OUTPUT_REG_SET);
	if (err)
		goto out_bgio;

	port->gc.request = gpiochip_generic_request;
	port->gc.free = gpiochip_generic_free;
	port->gc.to_irq = mxc_gpio_to_irq;
	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
					     pdev->id * 32;

	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
	if (err)
		goto out_bgio;

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
	if (irq_base < 0) {
		err = irq_base;
		goto out_bgio;
	}

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_bgio;
	}

	/* gpio-mxc can be a generic irq chip */
	err = mxc_gpio_init_gc(port, irq_base);
	if (err < 0)
		goto out_irqdomain_remove;

	list_add_tail(&port->node, &mxc_gpio_ports);

	platform_set_drvdata(pdev, port);

	return 0;

out_irqdomain_remove:
	irq_domain_remove(port->domain);
out_bgio:
	clk_disable_unprepare(port->clk);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	return err;
}

static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
{
	if (!port->power_off)
		return;

	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
}

static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
{
	if (!port->power_off)
		return;

	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
}

static int mxc_gpio_syscore_suspend(void)
{
	struct mxc_gpio_port *port;

	/* walk through all ports */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		mxc_gpio_save_regs(port);
		clk_disable_unprepare(port->clk);
	}

	return 0;
}

static void mxc_gpio_syscore_resume(void)
{
	struct mxc_gpio_port *port;
	int ret;

	/* walk through all ports */
	list_for_each_entry(port, &mxc_gpio_ports, node) {
		ret = clk_prepare_enable(port->clk);
		if (ret) {
			pr_err("mxc: failed to enable gpio clock %d\n", ret);
			return;
		}
		mxc_gpio_restore_regs(port);
	}
}

static struct syscore_ops mxc_gpio_syscore_ops = {
	.suspend = mxc_gpio_syscore_suspend,
	.resume = mxc_gpio_syscore_resume,
};

static struct platform_driver mxc_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxc",
		.of_match_table = mxc_gpio_dt_ids,
		.suppress_bind_attrs = true,
	},
	.probe		= mxc_gpio_probe,
};

static int __init gpio_mxc_init(void)
{
	register_syscore_ops(&mxc_gpio_syscore_ops);

	return platform_driver_register(&mxc_gpio_driver);
}
subsys_initcall(gpio_mxc_init);

MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("i.MX GPIO Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
014e420d FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	4	// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	5	//
	6	// Based on code from Freescale Semiconductor,
	7	// Authors: Daniel Mack, Juergen Beisert.
	8	// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
07bd1a6c	9
2808801a	10	#include <linux/clk.h>
18f92b19	11	#include <linux/err.h>
07bd1a6c	12	#include <linux/init.h>
a3484ffd	13	#include <linux/interrupt.h>
07bd1a6c JB	14	#include <linux/io.h>
07bd1a6c JB	15	#include <linux/irq.h>
1ab7ef15	16	#include <linux/irqdomain.h>
de88cbb7	17	#include <linux/irqchip/chained_irq.h>
12d16b39	18	#include <linux/module.h>
b78d8e59 SG	19	#include <linux/platform_device.h>
b78d8e59 SG	20	#include <linux/slab.h>
1a5287a3	21	#include <linux/syscore_ops.h>
0f4630f3	22	#include <linux/gpio/driver.h>
8937cb60 SG	23	#include <linux/of.h>
8937cb60 SG	24	#include <linux/of_device.h>
16c3bd35	25	#include <linux/bug.h>
07bd1a6c	26
e7fc6ae7 SG	27	/* device type dependent stuff */
	28	struct mxc_gpio_hwdata {
	29	unsigned dr_reg;
	30	unsigned gdir_reg;
	31	unsigned psr_reg;
	32	unsigned icr1_reg;
	33	unsigned icr2_reg;
	34	unsigned imr_reg;
	35	unsigned isr_reg;
aeb27748	36	int edge_sel_reg;
e7fc6ae7 SG	37	unsigned low_level;
	38	unsigned high_level;
	39	unsigned rise_edge;
	40	unsigned fall_edge;
	41	};
	42
c19fdaee AH	43	struct mxc_gpio_reg_saved {
	44	u32 icr1;
	45	u32 icr2;
	46	u32 imr;
	47	u32 gdir;
	48	u32 edge_sel;
	49	u32 dr;
	50	};
	51
b78d8e59 SG	52	struct mxc_gpio_port {
	53	struct list_head node;
	54	void __iomem *base;
2808801a	55	struct clk *clk;
b78d8e59 SG	56	int irq;
b78d8e59 SG	57	int irq_high;
1ab7ef15	58	struct irq_domain *domain;
0f4630f3	59	struct gpio_chip gc;
db5270ac	60	struct device *dev;
b78d8e59	61	u32 both_edges;
c19fdaee AH	62	struct mxc_gpio_reg_saved gpio_saved_reg;
c19fdaee AH	63	bool power_off;
0f2c7af4	64	const struct mxc_gpio_hwdata *hwdata;
b78d8e59 SG	65	};
b78d8e59 SG	66
e7fc6ae7 SG	67	static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
	68	.dr_reg = 0x1c,
	69	.gdir_reg = 0x00,
	70	.psr_reg = 0x24,
	71	.icr1_reg = 0x28,
	72	.icr2_reg = 0x2c,
	73	.imr_reg = 0x30,
	74	.isr_reg = 0x34,
aeb27748	75	.edge_sel_reg = -EINVAL,
e7fc6ae7 SG	76	.low_level = 0x03,
	77	.high_level = 0x02,
	78	.rise_edge = 0x00,
	79	.fall_edge = 0x01,
	80	};
	81
	82	static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
	83	.dr_reg = 0x00,
	84	.gdir_reg = 0x04,
	85	.psr_reg = 0x08,
	86	.icr1_reg = 0x0c,
	87	.icr2_reg = 0x10,
	88	.imr_reg = 0x14,
	89	.isr_reg = 0x18,
aeb27748 BT	90	.edge_sel_reg = -EINVAL,
	91	.low_level = 0x00,
	92	.high_level = 0x01,
	93	.rise_edge = 0x02,
	94	.fall_edge = 0x03,
	95	};
	96
	97	static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
	98	.dr_reg = 0x00,
	99	.gdir_reg = 0x04,
	100	.psr_reg = 0x08,
	101	.icr1_reg = 0x0c,
	102	.icr2_reg = 0x10,
	103	.imr_reg = 0x14,
	104	.isr_reg = 0x18,
	105	.edge_sel_reg = 0x1c,
e7fc6ae7 SG	106	.low_level = 0x00,
	107	.high_level = 0x01,
	108	.rise_edge = 0x02,
	109	.fall_edge = 0x03,
	110	};
	111
0f2c7af4 FE	112	#define GPIO_DR (port->hwdata->dr_reg)
	113	#define GPIO_GDIR (port->hwdata->gdir_reg)
	114	#define GPIO_PSR (port->hwdata->psr_reg)
	115	#define GPIO_ICR1 (port->hwdata->icr1_reg)
	116	#define GPIO_ICR2 (port->hwdata->icr2_reg)
	117	#define GPIO_IMR (port->hwdata->imr_reg)
	118	#define GPIO_ISR (port->hwdata->isr_reg)
	119	#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
	120
	121	#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
	122	#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
	123	#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
	124	#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
aeb27748	125	#define GPIO_INT_BOTH_EDGES 0x4
e7fc6ae7	126
8937cb60	127	static const struct of_device_id mxc_gpio_dt_ids[] = {
0f2c7af4 FE	128	{ .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
	129	{ .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
	130	{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
	131	{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
	132	{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
8937cb60 SG	133	{ /* sentinel */ }
8937cb60 SG	134	};
12d16b39	135	MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
8937cb60	136
b78d8e59 SG	137	/*
	138	* MX2 has one interrupt for all gpio ports. The list is used
	139	* to save the references to all ports, so that mx2_gpio_irq_handler
	140	* can walk through all interrupt status registers.
	141	*/
	142	static LIST_HEAD(mxc_gpio_ports);
07bd1a6c JB	143
	144	/* Note: This driver assumes 32 GPIOs are handled in one register */
	145
4d93579f	146	static int gpio_set_irq_type(struct irq_data *d, u32 type)
07bd1a6c	147	{
e4ea9333 SG	148	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	149	struct mxc_gpio_port *port = gc->private;
07bd1a6c	150	u32 bit, val;
1ab7ef15	151	u32 gpio_idx = d->hwirq;
07bd1a6c JB	152	int edge;
	153	void __iomem *reg = port->base;
	154
1ab7ef15	155	port->both_edges &= ~(1 << gpio_idx);
07bd1a6c	156	switch (type) {
6cab4860	157	case IRQ_TYPE_EDGE_RISING:
07bd1a6c JB	158	edge = GPIO_INT_RISE_EDGE;
07bd1a6c JB	159	break;
6cab4860	160	case IRQ_TYPE_EDGE_FALLING:
07bd1a6c JB	161	edge = GPIO_INT_FALL_EDGE;
07bd1a6c JB	162	break;
910862ec	163	case IRQ_TYPE_EDGE_BOTH:
aeb27748 BT	164	if (GPIO_EDGE_SEL >= 0) {
aeb27748 BT	165	edge = GPIO_INT_BOTH_EDGES;
910862ec	166	} else {
8d0bd9a5	167	val = port->gc.get(&port->gc, gpio_idx);
aeb27748 BT	168	if (val) {
aeb27748 BT	169	edge = GPIO_INT_LOW_LEV;
8d0bd9a5	170	pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
aeb27748 BT	171	} else {
aeb27748 BT	172	edge = GPIO_INT_HIGH_LEV;
8d0bd9a5	173	pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
aeb27748	174	}
f948ad07	175	port->both_edges \|= 1 << gpio_idx;
910862ec	176	}
910862ec	177	break;
6cab4860	178	case IRQ_TYPE_LEVEL_LOW:
07bd1a6c JB	179	edge = GPIO_INT_LOW_LEV;
07bd1a6c JB	180	break;
6cab4860	181	case IRQ_TYPE_LEVEL_HIGH:
07bd1a6c JB	182	edge = GPIO_INT_HIGH_LEV;
07bd1a6c JB	183	break;
910862ec	184	default:
07bd1a6c JB	185	return -EINVAL;
	186	}
	187
aeb27748 BT	188	if (GPIO_EDGE_SEL >= 0) {
	189	val = readl(port->base + GPIO_EDGE_SEL);
	190	if (edge == GPIO_INT_BOTH_EDGES)
f948ad07	191	writel(val \| (1 << gpio_idx),
aeb27748 BT	192	port->base + GPIO_EDGE_SEL);
aeb27748 BT	193	else
f948ad07	194	writel(val & ~(1 << gpio_idx),
aeb27748 BT	195	port->base + GPIO_EDGE_SEL);
	196	}
	197
	198	if (edge != GPIO_INT_BOTH_EDGES) {
f948ad07 LT	199	reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
f948ad07 LT	200	bit = gpio_idx & 0xf;
aeb27748 BT	201	val = readl(reg) & ~(0x3 << (bit << 1));
	202	writel(val \| (edge << (bit << 1)), reg);
	203	}
	204
1ab7ef15	205	writel(1 << gpio_idx, port->base + GPIO_ISR);
07bd1a6c JB	206
	207	return 0;
	208	}
	209
910862ec GL	210	static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
	211	{
	212	void __iomem *reg = port->base;
	213	u32 bit, val;
	214	int edge;
	215
	216	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
	217	bit = gpio & 0xf;
b78d8e59	218	val = readl(reg);
910862ec GL	219	edge = (val >> (bit << 1)) & 3;
910862ec GL	220	val &= ~(0x3 << (bit << 1));
3d40f7fe	221	if (edge == GPIO_INT_HIGH_LEV) {
910862ec GL	222	edge = GPIO_INT_LOW_LEV;
910862ec GL	223	pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
3d40f7fe	224	} else if (edge == GPIO_INT_LOW_LEV) {
910862ec GL	225	edge = GPIO_INT_HIGH_LEV;
910862ec GL	226	pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
3d40f7fe	227	} else {
910862ec GL	228	pr_err("mxc: invalid configuration for GPIO %d: %x\n",
	229	gpio, edge);
	230	return;
	231	}
b78d8e59	232	writel(val \| (edge << (bit << 1)), reg);
910862ec GL	233	}
910862ec GL	234
3621f188	235	/* handle 32 interrupts in one status register */
07bd1a6c JB	236	static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
07bd1a6c JB	237	{
3621f188 UKK	238	while (irq_stat != 0) {
3621f188 UKK	239	int irqoffset = fls(irq_stat) - 1;
07bd1a6c	240
3621f188 UKK	241	if (port->both_edges & (1 << irqoffset))
3621f188 UKK	242	mxc_flip_edge(port, irqoffset);
910862ec	243
1ab7ef15	244	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
910862ec	245
3621f188	246	irq_stat &= ~(1 << irqoffset);
07bd1a6c JB	247	}
	248	}
	249
cfca8b53	250	/* MX1 and MX3 has one interrupt per gpio port */
bd0b9ac4	251	static void mx3_gpio_irq_handler(struct irq_desc *desc)
07bd1a6c JB	252	{
07bd1a6c JB	253	u32 irq_stat;
476f8b4c JL	254	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
476f8b4c JL	255	struct irq_chip *chip = irq_desc_get_chip(desc);
0e44b6ec SG	256
0e44b6ec SG	257	chained_irq_enter(chip, desc);
07bd1a6c	258
b78d8e59	259	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
e2c97e7f	260
07bd1a6c	261	mxc_gpio_irq_handler(port, irq_stat);
0e44b6ec SG	262
0e44b6ec SG	263	chained_irq_exit(chip, desc);
07bd1a6c	264	}
07bd1a6c	265
07bd1a6c	266	/* MX2 has one interrupt for all gpio ports */
bd0b9ac4	267	static void mx2_gpio_irq_handler(struct irq_desc *desc)
07bd1a6c	268	{
07bd1a6c	269	u32 irq_msk, irq_stat;
b78d8e59	270	struct mxc_gpio_port *port;
476f8b4c	271	struct irq_chip *chip = irq_desc_get_chip(desc);
c0e811d9 UKK	272
c0e811d9 UKK	273	chained_irq_enter(chip, desc);
07bd1a6c JB	274
07bd1a6c JB	275	/* walk through all interrupt status registers */
b78d8e59 SG	276	list_for_each_entry(port, &mxc_gpio_ports, node) {
b78d8e59 SG	277	irq_msk = readl(port->base + GPIO_IMR);
07bd1a6c JB	278	if (!irq_msk)
	279	continue;
	280
b78d8e59	281	irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
07bd1a6c	282	if (irq_stat)
b78d8e59	283	mxc_gpio_irq_handler(port, irq_stat);
07bd1a6c	284	}
c0e811d9	285	chained_irq_exit(chip, desc);
07bd1a6c	286	}
07bd1a6c	287
a3484ffd DN	288	/*
	289	* Set interrupt number "irq" in the GPIO as a wake-up source.
	290	* While system is running, all registered GPIO interrupts need to have
	291	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	292	* need to have wake-up enabled.
	293	* @param irq interrupt source number
	294	* @param enable enable as wake-up if equal to non-zero
	295	* @return This function returns 0 on success.
	296	*/
4d93579f	297	static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
a3484ffd	298	{
e4ea9333 SG	299	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
e4ea9333 SG	300	struct mxc_gpio_port *port = gc->private;
1ab7ef15	301	u32 gpio_idx = d->hwirq;
77a4d757	302	int ret;
a3484ffd DN	303
	304	if (enable) {
	305	if (port->irq_high && (gpio_idx >= 16))
77a4d757	306	ret = enable_irq_wake(port->irq_high);
a3484ffd	307	else
77a4d757	308	ret = enable_irq_wake(port->irq);
a3484ffd DN	309	} else {
a3484ffd DN	310	if (port->irq_high && (gpio_idx >= 16))
77a4d757	311	ret = disable_irq_wake(port->irq_high);
a3484ffd	312	else
77a4d757	313	ret = disable_irq_wake(port->irq);
a3484ffd DN	314	}
a3484ffd DN	315
77a4d757	316	return ret;
a3484ffd DN	317	}
a3484ffd DN	318
9e26b0b1	319	static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
e4ea9333 SG	320	{
	321	struct irq_chip_generic *gc;
	322	struct irq_chip_type *ct;
db5270ac	323	int rv;
e4ea9333	324
db5270ac BG	325	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
db5270ac BG	326	port->base, handle_level_irq);
9e26b0b1 PF	327	if (!gc)
9e26b0b1 PF	328	return -ENOMEM;
e4ea9333 SG	329	gc->private = port;
	330
	331	ct = gc->chip_types;
591567a5	332	ct->chip.irq_ack = irq_gc_ack_set_bit;
e4ea9333 SG	333	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	334	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	335	ct->chip.irq_set_type = gpio_set_irq_type;
591567a5	336	ct->chip.irq_set_wake = gpio_set_wake_irq;
952cfbd3	337	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
e4ea9333 SG	338	ct->regs.ack = GPIO_ISR;
	339	ct->regs.mask = GPIO_IMR;
	340
db5270ac BG	341	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
	342	IRQ_GC_INIT_NESTED_LOCK,
	343	IRQ_NOREQUEST, 0);
9e26b0b1	344
db5270ac	345	return rv;
e4ea9333	346	}
b5eee2fd	347
09ad8039 SG	348	static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
09ad8039 SG	349	{
0f4630f3	350	struct mxc_gpio_port *port = gpiochip_get_data(gc);
09ad8039	351
1ab7ef15	352	return irq_find_mapping(port->domain, offset);
09ad8039 SG	353	}
09ad8039 SG	354
3836309d	355	static int mxc_gpio_probe(struct platform_device *pdev)
07bd1a6c	356	{
8937cb60	357	struct device_node *np = pdev->dev.of_node;
b78d8e59	358	struct mxc_gpio_port *port;
c8f3d144	359	int irq_count;
1ab7ef15	360	int irq_base;
e4ea9333	361	int err;
b78d8e59	362
8cd73e4e	363	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
b78d8e59 SG	364	if (!port)
b78d8e59 SG	365	return -ENOMEM;
07bd1a6c	366
db5270ac BG	367	port->dev = &pdev->dev;
db5270ac BG	368
0f2c7af4 FE	369	port->hwdata = device_get_match_data(&pdev->dev);
0f2c7af4 FE	370
123ac0e5	371	port->base = devm_platform_ioremap_resource(pdev, 0);
8cd73e4e FE	372	if (IS_ERR(port->base))
8cd73e4e FE	373	return PTR_ERR(port->base);
b78d8e59	374
c8f3d144 AH	375	irq_count = platform_irq_count(pdev);
	376	if (irq_count < 0)
	377	return irq_count;
	378
	379	if (irq_count > 1) {
	380	port->irq_high = platform_get_irq(pdev, 1);
	381	if (port->irq_high < 0)
	382	port->irq_high = 0;
	383	}
cc9269f8	384
b78d8e59	385	port->irq = platform_get_irq(pdev, 0);
8cd73e4e	386	if (port->irq < 0)
5ea80e49	387	return port->irq;
b78d8e59	388
2808801a	389	/* the controller clock is optional */
7beb620f AH	390	port->clk = devm_clk_get_optional(&pdev->dev, NULL);
	391	if (IS_ERR(port->clk))
	392	return PTR_ERR(port->clk);
2808801a AH	393
	394	err = clk_prepare_enable(port->clk);
	395	if (err) {
	396	dev_err(&pdev->dev, "Unable to enable clock.\n");
	397	return err;
	398	}
	399
c19fdaee AH	400	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
	401	port->power_off = true;
	402
b78d8e59 SG	403	/* disable the interrupt and clear the status */
	404	writel(0, port->base + GPIO_IMR);
	405	writel(~0, port->base + GPIO_ISR);
	406
0f2c7af4	407	if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
33a4e985 UKK	408	/*
	409	* Setup one handler for all GPIO interrupts. Actually setting
	410	* the handler is needed only once, but doing it for every port
	411	* is more robust and easier.
	412	*/
	413	irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
b78d8e59 SG	414	} else {
b78d8e59 SG	415	/* setup one handler for each entry */
e65eea54 RK	416	irq_set_chained_handler_and_data(port->irq,
	417	mx3_gpio_irq_handler, port);
	418	if (port->irq_high > 0)
b78d8e59	419	/* setup handler for GPIO 16 to 31 */
e65eea54 RK	420	irq_set_chained_handler_and_data(port->irq_high,
	421	mx3_gpio_irq_handler,
	422	port);
07bd1a6c JB	423	}
07bd1a6c JB	424
0f4630f3	425	err = bgpio_init(&port->gc, &pdev->dev, 4,
2ce420da SG	426	port->base + GPIO_PSR,
2ce420da SG	427	port->base + GPIO_DR, NULL,
442b2494 VZ	428	port->base + GPIO_GDIR, NULL,
442b2494 VZ	429	BGPIOF_READ_OUTPUT_REG_SET);
2ce420da	430	if (err)
8cd73e4e	431	goto out_bgio;
b78d8e59	432
f0254b51 TR	433	port->gc.request = gpiochip_generic_request;
f0254b51 TR	434	port->gc.free = gpiochip_generic_free;
0f4630f3 LW	435	port->gc.to_irq = mxc_gpio_to_irq;
0f4630f3 LW	436	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
7e6086d9	437	pdev->id * 32;
b78d8e59	438
ffc56630	439	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
b78d8e59	440	if (err)
0f4630f3	441	goto out_bgio;
b78d8e59	442
c553c3c4	443	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
1ab7ef15 SG	444	if (irq_base < 0) {
1ab7ef15 SG	445	err = irq_base;
ffc56630	446	goto out_bgio;
1ab7ef15 SG	447	}
	448
	449	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	450	&irq_domain_simple_ops, NULL);
	451	if (!port->domain) {
	452	err = -ENODEV;
c553c3c4	453	goto out_bgio;
1ab7ef15	454	}
8937cb60 SG	455
8937cb60 SG	456	/* gpio-mxc can be a generic irq chip */
9e26b0b1 PF	457	err = mxc_gpio_init_gc(port, irq_base);
	458	if (err < 0)
	459	goto out_irqdomain_remove;
8937cb60	460
b78d8e59 SG	461	list_add_tail(&port->node, &mxc_gpio_ports);
b78d8e59 SG	462
c19fdaee AH	463	platform_set_drvdata(pdev, port);
c19fdaee AH	464
07bd1a6c	465	return 0;
b78d8e59	466
9e26b0b1 PF	467	out_irqdomain_remove:
9e26b0b1 PF	468	irq_domain_remove(port->domain);
8cd73e4e	469	out_bgio:
2808801a	470	clk_disable_unprepare(port->clk);
b78d8e59 SG	471	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
b78d8e59 SG	472	return err;
07bd1a6c	473	}
b78d8e59	474
c19fdaee AH	475	static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
	476	{
	477	if (!port->power_off)
	478	return;
	479
	480	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
	481	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
	482	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
	483	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
	484	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
	485	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
	486	}
	487
	488	static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
	489	{
	490	if (!port->power_off)
	491	return;
	492
	493	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
	494	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
	495	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
	496	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
	497	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
	498	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
	499	}
	500
1a5287a3	501	static int mxc_gpio_syscore_suspend(void)
c19fdaee	502	{
1a5287a3	503	struct mxc_gpio_port *port;
c19fdaee	504
1a5287a3 AH	505	/* walk through all ports */
	506	list_for_each_entry(port, &mxc_gpio_ports, node) {
	507	mxc_gpio_save_regs(port);
	508	clk_disable_unprepare(port->clk);
	509	}
c19fdaee AH	510
	511	return 0;
	512	}
	513
1a5287a3	514	static void mxc_gpio_syscore_resume(void)
c19fdaee	515	{
1a5287a3	516	struct mxc_gpio_port *port;
c19fdaee AH	517	int ret;
c19fdaee AH	518
1a5287a3 AH	519	/* walk through all ports */
	520	list_for_each_entry(port, &mxc_gpio_ports, node) {
	521	ret = clk_prepare_enable(port->clk);
	522	if (ret) {
	523	pr_err("mxc: failed to enable gpio clock %d\n", ret);
	524	return;
	525	}
	526	mxc_gpio_restore_regs(port);
	527	}
c19fdaee AH	528	}
c19fdaee AH	529
1a5287a3 AH	530	static struct syscore_ops mxc_gpio_syscore_ops = {
	531	.suspend = mxc_gpio_syscore_suspend,
	532	.resume = mxc_gpio_syscore_resume,
c19fdaee AH	533	};
c19fdaee AH	534
b78d8e59 SG	535	static struct platform_driver mxc_gpio_driver = {
	536	.driver = {
	537	.name = "gpio-mxc",
8937cb60	538	.of_match_table = mxc_gpio_dt_ids,
90e1fc4c	539	.suppress_bind_attrs = true,
b78d8e59 SG	540	},
	541	.probe = mxc_gpio_probe,
	542	};
	543
	544	static int __init gpio_mxc_init(void)
	545	{
1a5287a3 AH	546	register_syscore_ops(&mxc_gpio_syscore_ops);
1a5287a3 AH	547
b78d8e59 SG	548	return platform_driver_register(&mxc_gpio_driver);
b78d8e59 SG	549	}
e188cbf7	550	subsys_initcall(gpio_mxc_init);
12d16b39 AH	551
	552	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	553	MODULE_DESCRIPTION("i.MX GPIO Driver");
	554	MODULE_LICENSE("GPL");