Commit | Line | Data |
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3bb16560 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
fefe7b09 TP |
2 | /* |
3 | * GPIO driver for Marvell SoCs | |
4 | * | |
5 | * Copyright (C) 2012 Marvell | |
6 | * | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * Andrew Lunn <andrew@lunn.ch> | |
9 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
10 | * | |
fefe7b09 TP |
11 | * This driver is a fairly straightforward GPIO driver for the |
12 | * complete family of Marvell EBU SoC platforms (Orion, Dove, | |
13 | * Kirkwood, Discovery, Armada 370/XP). The only complexity of this | |
14 | * driver is the different register layout that exists between the | |
15 | * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP | |
16 | * platforms (MV78200 from the Discovery family and the Armada | |
17 | * XP). Therefore, this driver handles three variants of the GPIO | |
18 | * block: | |
19 | * - the basic variant, called "orion-gpio", with the simplest | |
20 | * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and | |
21 | * non-SMP Discovery systems | |
22 | * - the mv78200 variant for MV78200 Discovery systems. This variant | |
23 | * turns the edge mask and level mask registers into CPU0 edge | |
24 | * mask/level mask registers, and adds CPU1 edge mask/level mask | |
25 | * registers. | |
26 | * - the armadaxp variant for Armada XP systems. This variant keeps | |
27 | * the normal cause/edge mask/level mask registers when the global | |
28 | * interrupts are used, but adds per-CPU cause/edge mask/level mask | |
29 | * registers n a separate memory area for the per-CPU GPIO | |
30 | * interrupts. | |
31 | */ | |
32 | ||
6ec015d6 GC |
33 | #include <linux/bitops.h> |
34 | #include <linux/clk.h> | |
641d0342 | 35 | #include <linux/err.h> |
ba78d83b LW |
36 | #include <linux/gpio/driver.h> |
37 | #include <linux/gpio/consumer.h> | |
5923ea6c | 38 | #include <linux/gpio/machine.h> |
6ec015d6 GC |
39 | #include <linux/init.h> |
40 | #include <linux/io.h> | |
fefe7b09 | 41 | #include <linux/irq.h> |
6ec015d6 | 42 | #include <linux/irqchip/chained_irq.h> |
fefe7b09 | 43 | #include <linux/irqdomain.h> |
b6730b20 | 44 | #include <linux/mfd/syscon.h> |
fefe7b09 | 45 | #include <linux/of_device.h> |
fefe7b09 | 46 | #include <linux/pinctrl/consumer.h> |
757642f9 | 47 | #include <linux/platform_device.h> |
6ec015d6 | 48 | #include <linux/pwm.h> |
2233bf7a | 49 | #include <linux/regmap.h> |
6ec015d6 | 50 | #include <linux/slab.h> |
fefe7b09 TP |
51 | |
52 | /* | |
53 | * GPIO unit register offsets. | |
54 | */ | |
757642f9 AL |
55 | #define GPIO_OUT_OFF 0x0000 |
56 | #define GPIO_IO_CONF_OFF 0x0004 | |
57 | #define GPIO_BLINK_EN_OFF 0x0008 | |
58 | #define GPIO_IN_POL_OFF 0x000c | |
59 | #define GPIO_DATA_IN_OFF 0x0010 | |
60 | #define GPIO_EDGE_CAUSE_OFF 0x0014 | |
61 | #define GPIO_EDGE_MASK_OFF 0x0018 | |
62 | #define GPIO_LEVEL_MASK_OFF 0x001c | |
63 | #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 | |
64 | ||
65 | /* | |
66 | * PWM register offsets. | |
67 | */ | |
68 | #define PWM_BLINK_ON_DURATION_OFF 0x0 | |
69 | #define PWM_BLINK_OFF_DURATION_OFF 0x4 | |
85b7d8ab | 70 | #define PWM_BLINK_COUNTER_B_OFF 0x8 |
757642f9 | 71 | |
85b7d8ab BS |
72 | /* Armada 8k variant gpios register offsets */ |
73 | #define AP80X_GPIO0_OFF_A8K 0x1040 | |
74 | #define CP11X_GPIO0_OFF_A8K 0x100 | |
75 | #define CP11X_GPIO1_OFF_A8K 0x140 | |
fefe7b09 TP |
76 | |
77 | /* The MV78200 has per-CPU registers for edge mask and level mask */ | |
a4319a61 | 78 | #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) |
fefe7b09 TP |
79 | #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) |
80 | ||
7077f4cc RS |
81 | /* |
82 | * The Armada XP has per-CPU registers for interrupt cause, interrupt | |
64b19f6a | 83 | * mask and interrupt level mask. Those are in percpu_regs range. |
7077f4cc | 84 | */ |
fefe7b09 TP |
85 | #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) |
86 | #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) | |
87 | #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) | |
88 | ||
a4319a61 AL |
89 | #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 |
90 | #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 | |
fefe7b09 | 91 | #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 |
b6730b20 | 92 | #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 |
fefe7b09 | 93 | |
a4319a61 | 94 | #define MVEBU_MAX_GPIO_PER_BANK 32 |
fefe7b09 | 95 | |
757642f9 | 96 | struct mvebu_pwm { |
48f32a83 | 97 | struct regmap *regs; |
85b7d8ab | 98 | u32 offset; |
757642f9 AL |
99 | unsigned long clk_rate; |
100 | struct gpio_desc *gpiod; | |
101 | struct pwm_chip chip; | |
102 | spinlock_t lock; | |
103 | struct mvebu_gpio_chip *mvchip; | |
104 | ||
105 | /* Used to preserve GPIO/PWM registers across suspend/resume */ | |
106 | u32 blink_select; | |
107 | u32 blink_on_duration; | |
108 | u32 blink_off_duration; | |
109 | }; | |
110 | ||
fefe7b09 TP |
111 | struct mvebu_gpio_chip { |
112 | struct gpio_chip chip; | |
2233bf7a | 113 | struct regmap *regs; |
b6730b20 | 114 | u32 offset; |
2233bf7a | 115 | struct regmap *percpu_regs; |
d5359226 | 116 | int irqbase; |
fefe7b09 | 117 | struct irq_domain *domain; |
a4319a61 | 118 | int soc_variant; |
b5b7b487 | 119 | |
757642f9 AL |
120 | /* Used for PWM support */ |
121 | struct clk *clk; | |
122 | struct mvebu_pwm *mvpwm; | |
123 | ||
a4319a61 | 124 | /* Used to preserve GPIO registers across suspend/resume */ |
f4c240ca RS |
125 | u32 out_reg; |
126 | u32 io_conf_reg; | |
127 | u32 blink_en_reg; | |
128 | u32 in_pol_reg; | |
129 | u32 edge_mask_regs[4]; | |
130 | u32 level_mask_regs[4]; | |
fefe7b09 TP |
131 | }; |
132 | ||
133 | /* | |
134 | * Functions returning addresses of individual registers for a given | |
135 | * GPIO controller. | |
136 | */ | |
fefe7b09 | 137 | |
2233bf7a TP |
138 | static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, |
139 | struct regmap **map, unsigned int *offset) | |
e9133760 | 140 | { |
2233bf7a | 141 | int cpu; |
e9133760 | 142 | |
2233bf7a TP |
143 | switch (mvchip->soc_variant) { |
144 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
145 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
b6730b20 | 146 | case MVEBU_GPIO_SOC_VARIANT_A8K: |
2233bf7a | 147 | *map = mvchip->regs; |
b6730b20 | 148 | *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; |
2233bf7a TP |
149 | break; |
150 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
151 | cpu = smp_processor_id(); | |
152 | *map = mvchip->percpu_regs; | |
153 | *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); | |
154 | break; | |
155 | default: | |
156 | BUG(); | |
157 | } | |
757642f9 AL |
158 | } |
159 | ||
2233bf7a TP |
160 | static u32 |
161 | mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) | |
fefe7b09 | 162 | { |
2233bf7a TP |
163 | struct regmap *map; |
164 | unsigned int offset; | |
165 | u32 val; | |
fefe7b09 | 166 | |
2233bf7a TP |
167 | mvebu_gpioreg_edge_cause(mvchip, &map, &offset); |
168 | regmap_read(map, offset, &val); | |
169 | ||
170 | return val; | |
fefe7b09 TP |
171 | } |
172 | ||
2233bf7a TP |
173 | static void |
174 | mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) | |
fefe7b09 | 175 | { |
2233bf7a TP |
176 | struct regmap *map; |
177 | unsigned int offset; | |
178 | ||
179 | mvebu_gpioreg_edge_cause(mvchip, &map, &offset); | |
180 | regmap_write(map, offset, val); | |
fefe7b09 TP |
181 | } |
182 | ||
2233bf7a TP |
183 | static inline void |
184 | mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, | |
185 | struct regmap **map, unsigned int *offset) | |
fefe7b09 TP |
186 | { |
187 | int cpu; | |
188 | ||
f4dcd2d9 | 189 | switch (mvchip->soc_variant) { |
fefe7b09 | 190 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
b6730b20 | 191 | case MVEBU_GPIO_SOC_VARIANT_A8K: |
2233bf7a | 192 | *map = mvchip->regs; |
b6730b20 | 193 | *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; |
2233bf7a | 194 | break; |
fefe7b09 | 195 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
2233bf7a TP |
196 | cpu = smp_processor_id(); |
197 | *map = mvchip->regs; | |
198 | *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); | |
199 | break; | |
fefe7b09 TP |
200 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
201 | cpu = smp_processor_id(); | |
2233bf7a TP |
202 | *map = mvchip->percpu_regs; |
203 | *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); | |
204 | break; | |
fefe7b09 TP |
205 | default: |
206 | BUG(); | |
207 | } | |
208 | } | |
209 | ||
2233bf7a TP |
210 | static u32 |
211 | mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) | |
fefe7b09 | 212 | { |
2233bf7a TP |
213 | struct regmap *map; |
214 | unsigned int offset; | |
215 | u32 val; | |
fefe7b09 | 216 | |
2233bf7a TP |
217 | mvebu_gpioreg_edge_mask(mvchip, &map, &offset); |
218 | regmap_read(map, offset, &val); | |
219 | ||
220 | return val; | |
fefe7b09 TP |
221 | } |
222 | ||
2233bf7a TP |
223 | static void |
224 | mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) | |
225 | { | |
226 | struct regmap *map; | |
227 | unsigned int offset; | |
228 | ||
229 | mvebu_gpioreg_edge_mask(mvchip, &map, &offset); | |
230 | regmap_write(map, offset, val); | |
231 | } | |
232 | ||
233 | static void | |
234 | mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, | |
235 | struct regmap **map, unsigned int *offset) | |
fefe7b09 TP |
236 | { |
237 | int cpu; | |
238 | ||
f4dcd2d9 | 239 | switch (mvchip->soc_variant) { |
fefe7b09 | 240 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
b6730b20 | 241 | case MVEBU_GPIO_SOC_VARIANT_A8K: |
2233bf7a | 242 | *map = mvchip->regs; |
b6730b20 | 243 | *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; |
2233bf7a | 244 | break; |
fefe7b09 TP |
245 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
246 | cpu = smp_processor_id(); | |
2233bf7a TP |
247 | *map = mvchip->regs; |
248 | *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); | |
249 | break; | |
fefe7b09 TP |
250 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
251 | cpu = smp_processor_id(); | |
2233bf7a TP |
252 | *map = mvchip->percpu_regs; |
253 | *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); | |
254 | break; | |
fefe7b09 TP |
255 | default: |
256 | BUG(); | |
257 | } | |
258 | } | |
259 | ||
2233bf7a TP |
260 | static u32 |
261 | mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) | |
262 | { | |
263 | struct regmap *map; | |
264 | unsigned int offset; | |
265 | u32 val; | |
266 | ||
267 | mvebu_gpioreg_level_mask(mvchip, &map, &offset); | |
268 | regmap_read(map, offset, &val); | |
269 | ||
270 | return val; | |
271 | } | |
272 | ||
273 | static void | |
274 | mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) | |
275 | { | |
276 | struct regmap *map; | |
277 | unsigned int offset; | |
278 | ||
279 | mvebu_gpioreg_level_mask(mvchip, &map, &offset); | |
280 | regmap_write(map, offset, val); | |
281 | } | |
282 | ||
757642f9 | 283 | /* |
48f32a83 | 284 | * Functions returning offsets of individual registers for a given |
757642f9 AL |
285 | * PWM controller. |
286 | */ | |
48f32a83 | 287 | static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) |
757642f9 | 288 | { |
85b7d8ab | 289 | return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; |
757642f9 AL |
290 | } |
291 | ||
48f32a83 | 292 | static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) |
757642f9 | 293 | { |
85b7d8ab | 294 | return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; |
757642f9 AL |
295 | } |
296 | ||
fefe7b09 TP |
297 | /* |
298 | * Functions implementing the gpio_chip methods | |
299 | */ | |
d276de70 | 300 | static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) |
fefe7b09 | 301 | { |
bbe76004 | 302 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 | 303 | |
b6730b20 | 304 | regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, |
2233bf7a | 305 | BIT(pin), value ? BIT(pin) : 0); |
fefe7b09 TP |
306 | } |
307 | ||
d276de70 | 308 | static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 309 | { |
bbe76004 | 310 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
311 | u32 u; |
312 | ||
b6730b20 | 313 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); |
2233bf7a TP |
314 | |
315 | if (u & BIT(pin)) { | |
316 | u32 data_in, in_pol; | |
317 | ||
b6730b20 GC |
318 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, |
319 | &data_in); | |
320 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, | |
321 | &in_pol); | |
2233bf7a | 322 | u = data_in ^ in_pol; |
fefe7b09 | 323 | } else { |
b6730b20 | 324 | regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); |
fefe7b09 TP |
325 | } |
326 | ||
327 | return (u >> pin) & 1; | |
328 | } | |
329 | ||
d276de70 RS |
330 | static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, |
331 | int value) | |
e9133760 | 332 | { |
bbe76004 | 333 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
e9133760 | 334 | |
b6730b20 | 335 | regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, |
2233bf7a | 336 | BIT(pin), value ? BIT(pin) : 0); |
e9133760 JL |
337 | } |
338 | ||
d276de70 | 339 | static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 340 | { |
bbe76004 | 341 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 | 342 | int ret; |
fefe7b09 | 343 | |
7077f4cc RS |
344 | /* |
345 | * Check with the pinctrl driver whether this pin is usable as | |
346 | * an input GPIO | |
347 | */ | |
fefe7b09 TP |
348 | ret = pinctrl_gpio_direction_input(chip->base + pin); |
349 | if (ret) | |
350 | return ret; | |
351 | ||
b6730b20 | 352 | regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, |
43a2dcec | 353 | BIT(pin), BIT(pin)); |
fefe7b09 TP |
354 | |
355 | return 0; | |
356 | } | |
357 | ||
d276de70 | 358 | static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, |
fefe7b09 TP |
359 | int value) |
360 | { | |
bbe76004 | 361 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 | 362 | int ret; |
fefe7b09 | 363 | |
7077f4cc RS |
364 | /* |
365 | * Check with the pinctrl driver whether this pin is usable as | |
366 | * an output GPIO | |
367 | */ | |
fefe7b09 TP |
368 | ret = pinctrl_gpio_direction_output(chip->base + pin); |
369 | if (ret) | |
370 | return ret; | |
371 | ||
e9133760 | 372 | mvebu_gpio_blink(chip, pin, 0); |
c57d75c0 TP |
373 | mvebu_gpio_set(chip, pin, value); |
374 | ||
b6730b20 | 375 | regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, |
2233bf7a | 376 | BIT(pin), 0); |
fefe7b09 TP |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
e8dacf59 BS |
381 | static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) |
382 | { | |
383 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); | |
384 | u32 u; | |
385 | ||
386 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); | |
387 | ||
e42615ec MV |
388 | if (u & BIT(pin)) |
389 | return GPIO_LINE_DIRECTION_IN; | |
390 | ||
391 | return GPIO_LINE_DIRECTION_OUT; | |
e8dacf59 BS |
392 | } |
393 | ||
d276de70 | 394 | static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 395 | { |
bbe76004 | 396 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
163ad364 | 397 | |
fefe7b09 TP |
398 | return irq_create_mapping(mvchip->domain, pin); |
399 | } | |
400 | ||
401 | /* | |
402 | * Functions implementing the irq_chip methods | |
403 | */ | |
404 | static void mvebu_gpio_irq_ack(struct irq_data *d) | |
405 | { | |
406 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
407 | struct mvebu_gpio_chip *mvchip = gc->private; | |
812d4788 | 408 | u32 mask = d->mask; |
fefe7b09 TP |
409 | |
410 | irq_gc_lock(gc); | |
2233bf7a | 411 | mvebu_gpio_write_edge_cause(mvchip, ~mask); |
fefe7b09 TP |
412 | irq_gc_unlock(gc); |
413 | } | |
414 | ||
415 | static void mvebu_gpio_edge_irq_mask(struct irq_data *d) | |
416 | { | |
417 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
418 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 419 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 420 | u32 mask = d->mask; |
fefe7b09 TP |
421 | |
422 | irq_gc_lock(gc); | |
61819549 | 423 | ct->mask_cache_priv &= ~mask; |
2233bf7a | 424 | mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); |
fefe7b09 TP |
425 | irq_gc_unlock(gc); |
426 | } | |
427 | ||
428 | static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) | |
429 | { | |
430 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
431 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 432 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 433 | u32 mask = d->mask; |
fefe7b09 TP |
434 | |
435 | irq_gc_lock(gc); | |
d5331ec2 | 436 | mvebu_gpio_write_edge_cause(mvchip, ~mask); |
61819549 | 437 | ct->mask_cache_priv |= mask; |
2233bf7a | 438 | mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); |
fefe7b09 TP |
439 | irq_gc_unlock(gc); |
440 | } | |
441 | ||
442 | static void mvebu_gpio_level_irq_mask(struct irq_data *d) | |
443 | { | |
444 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
445 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 446 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 447 | u32 mask = d->mask; |
fefe7b09 TP |
448 | |
449 | irq_gc_lock(gc); | |
61819549 | 450 | ct->mask_cache_priv &= ~mask; |
2233bf7a | 451 | mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); |
fefe7b09 TP |
452 | irq_gc_unlock(gc); |
453 | } | |
454 | ||
455 | static void mvebu_gpio_level_irq_unmask(struct irq_data *d) | |
456 | { | |
457 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
458 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 459 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 460 | u32 mask = d->mask; |
fefe7b09 TP |
461 | |
462 | irq_gc_lock(gc); | |
61819549 | 463 | ct->mask_cache_priv |= mask; |
2233bf7a | 464 | mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); |
fefe7b09 TP |
465 | irq_gc_unlock(gc); |
466 | } | |
467 | ||
468 | /***************************************************************************** | |
469 | * MVEBU GPIO IRQ | |
470 | * | |
471 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same | |
472 | * value of the line or the opposite value. | |
473 | * | |
474 | * Level IRQ handlers: DATA_IN is used directly as cause register. | |
a4319a61 | 475 | * Interrupt are masked by LEVEL_MASK registers. |
fefe7b09 | 476 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. |
a4319a61 | 477 | * Interrupt are masked by EDGE_MASK registers. |
fefe7b09 | 478 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps |
a4319a61 AL |
479 | * the polarity to catch the next line transaction. |
480 | * This is a race condition that might not perfectly | |
481 | * work on some use cases. | |
fefe7b09 TP |
482 | * |
483 | * Every eight GPIO lines are grouped (OR'ed) before going up to main | |
484 | * cause register. | |
485 | * | |
a4319a61 AL |
486 | * EDGE cause mask |
487 | * data-in /--------| |-----| |----\ | |
488 | * -----| |----- ---- to main cause reg | |
489 | * X \----------------| |----/ | |
490 | * polarity LEVEL mask | |
fefe7b09 TP |
491 | * |
492 | ****************************************************************************/ | |
493 | ||
494 | static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
495 | { | |
496 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
497 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
498 | struct mvebu_gpio_chip *mvchip = gc->private; | |
499 | int pin; | |
500 | u32 u; | |
501 | ||
502 | pin = d->hwirq; | |
503 | ||
b6730b20 | 504 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); |
2233bf7a | 505 | if ((u & BIT(pin)) == 0) |
fefe7b09 | 506 | return -EINVAL; |
fefe7b09 TP |
507 | |
508 | type &= IRQ_TYPE_SENSE_MASK; | |
509 | if (type == IRQ_TYPE_NONE) | |
510 | return -EINVAL; | |
511 | ||
512 | /* Check if we need to change chip and handler */ | |
513 | if (!(ct->type & type)) | |
514 | if (irq_setup_alt_chip(d, type)) | |
515 | return -EINVAL; | |
516 | ||
517 | /* | |
518 | * Configure interrupt polarity. | |
519 | */ | |
f4dcd2d9 | 520 | switch (type) { |
fefe7b09 TP |
521 | case IRQ_TYPE_EDGE_RISING: |
522 | case IRQ_TYPE_LEVEL_HIGH: | |
b6730b20 GC |
523 | regmap_update_bits(mvchip->regs, |
524 | GPIO_IN_POL_OFF + mvchip->offset, | |
2233bf7a | 525 | BIT(pin), 0); |
7cf8c9f7 | 526 | break; |
fefe7b09 TP |
527 | case IRQ_TYPE_EDGE_FALLING: |
528 | case IRQ_TYPE_LEVEL_LOW: | |
b6730b20 GC |
529 | regmap_update_bits(mvchip->regs, |
530 | GPIO_IN_POL_OFF + mvchip->offset, | |
43a2dcec | 531 | BIT(pin), BIT(pin)); |
7cf8c9f7 | 532 | break; |
fefe7b09 | 533 | case IRQ_TYPE_EDGE_BOTH: { |
2233bf7a | 534 | u32 data_in, in_pol, val; |
fefe7b09 | 535 | |
b6730b20 GC |
536 | regmap_read(mvchip->regs, |
537 | GPIO_IN_POL_OFF + mvchip->offset, &in_pol); | |
538 | regmap_read(mvchip->regs, | |
539 | GPIO_DATA_IN_OFF + mvchip->offset, &data_in); | |
fefe7b09 TP |
540 | |
541 | /* | |
542 | * set initial polarity based on current input level | |
543 | */ | |
2233bf7a TP |
544 | if ((data_in ^ in_pol) & BIT(pin)) |
545 | val = BIT(pin); /* falling */ | |
fefe7b09 | 546 | else |
2233bf7a TP |
547 | val = 0; /* raising */ |
548 | ||
b6730b20 GC |
549 | regmap_update_bits(mvchip->regs, |
550 | GPIO_IN_POL_OFF + mvchip->offset, | |
2233bf7a | 551 | BIT(pin), val); |
7cf8c9f7 | 552 | break; |
fefe7b09 TP |
553 | } |
554 | } | |
555 | return 0; | |
556 | } | |
557 | ||
bd0b9ac4 | 558 | static void mvebu_gpio_irq_handler(struct irq_desc *desc) |
fefe7b09 | 559 | { |
476f8b4c | 560 | struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); |
01ca59f1 | 561 | struct irq_chip *chip = irq_desc_get_chip(desc); |
2233bf7a | 562 | u32 cause, type, data_in, level_mask, edge_cause, edge_mask; |
fefe7b09 TP |
563 | int i; |
564 | ||
565 | if (mvchip == NULL) | |
566 | return; | |
567 | ||
01ca59f1 TP |
568 | chained_irq_enter(chip, desc); |
569 | ||
b6730b20 | 570 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); |
2233bf7a TP |
571 | level_mask = mvebu_gpio_read_level_mask(mvchip); |
572 | edge_cause = mvebu_gpio_read_edge_cause(mvchip); | |
573 | edge_mask = mvebu_gpio_read_edge_mask(mvchip); | |
574 | ||
3f13b6a2 | 575 | cause = (data_in & level_mask) | (edge_cause & edge_mask); |
fefe7b09 TP |
576 | |
577 | for (i = 0; i < mvchip->chip.ngpio; i++) { | |
578 | int irq; | |
579 | ||
812d4788 | 580 | irq = irq_find_mapping(mvchip->domain, i); |
fefe7b09 | 581 | |
d2cabc4a | 582 | if (!(cause & BIT(i))) |
fefe7b09 TP |
583 | continue; |
584 | ||
fb90c22a | 585 | type = irq_get_trigger_type(irq); |
fefe7b09 TP |
586 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
587 | /* Swap polarity (race with GPIO line) */ | |
588 | u32 polarity; | |
589 | ||
b6730b20 GC |
590 | regmap_read(mvchip->regs, |
591 | GPIO_IN_POL_OFF + mvchip->offset, | |
592 | &polarity); | |
d2cabc4a | 593 | polarity ^= BIT(i); |
b6730b20 GC |
594 | regmap_write(mvchip->regs, |
595 | GPIO_IN_POL_OFF + mvchip->offset, | |
596 | polarity); | |
fefe7b09 | 597 | } |
01ca59f1 | 598 | |
fefe7b09 TP |
599 | generic_handle_irq(irq); |
600 | } | |
01ca59f1 TP |
601 | |
602 | chained_irq_exit(chip, desc); | |
fefe7b09 TP |
603 | } |
604 | ||
48f32a83 BS |
605 | static const struct regmap_config mvebu_gpio_regmap_config = { |
606 | .reg_bits = 32, | |
607 | .reg_stride = 4, | |
608 | .val_bits = 32, | |
609 | .fast_io = true, | |
610 | }; | |
611 | ||
757642f9 AL |
612 | /* |
613 | * Functions implementing the pwm_chip methods | |
614 | */ | |
615 | static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) | |
616 | { | |
617 | return container_of(chip, struct mvebu_pwm, chip); | |
618 | } | |
619 | ||
620 | static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
621 | { | |
622 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); | |
623 | struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; | |
624 | struct gpio_desc *desc; | |
625 | unsigned long flags; | |
626 | int ret = 0; | |
627 | ||
628 | spin_lock_irqsave(&mvpwm->lock, flags); | |
629 | ||
630 | if (mvpwm->gpiod) { | |
631 | ret = -EBUSY; | |
632 | } else { | |
ba78d83b | 633 | desc = gpiochip_request_own_desc(&mvchip->chip, |
5923ea6c LW |
634 | pwm->hwpwm, "mvebu-pwm", |
635 | GPIO_ACTIVE_HIGH, | |
636 | GPIOD_OUT_LOW); | |
ba78d83b LW |
637 | if (IS_ERR(desc)) { |
638 | ret = PTR_ERR(desc); | |
757642f9 | 639 | goto out; |
757642f9 AL |
640 | } |
641 | ||
642 | mvpwm->gpiod = desc; | |
643 | } | |
644 | out: | |
645 | spin_unlock_irqrestore(&mvpwm->lock, flags); | |
646 | return ret; | |
647 | } | |
648 | ||
649 | static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
650 | { | |
651 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); | |
652 | unsigned long flags; | |
653 | ||
654 | spin_lock_irqsave(&mvpwm->lock, flags); | |
ba78d83b | 655 | gpiochip_free_own_desc(mvpwm->gpiod); |
757642f9 AL |
656 | mvpwm->gpiod = NULL; |
657 | spin_unlock_irqrestore(&mvpwm->lock, flags); | |
658 | } | |
659 | ||
6c452cff UKK |
660 | static int mvebu_pwm_get_state(struct pwm_chip *chip, |
661 | struct pwm_device *pwm, | |
662 | struct pwm_state *state) | |
663 | { | |
757642f9 AL |
664 | |
665 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); | |
666 | struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; | |
667 | unsigned long long val; | |
668 | unsigned long flags; | |
669 | u32 u; | |
670 | ||
671 | spin_lock_irqsave(&mvpwm->lock, flags); | |
672 | ||
48f32a83 | 673 | regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); |
0b68d02b BS |
674 | /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ |
675 | if (u > 0) | |
676 | val = u; | |
757642f9 | 677 | else |
0b68d02b BS |
678 | val = UINT_MAX + 1ULL; |
679 | state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, | |
680 | mvpwm->clk_rate); | |
757642f9 | 681 | |
48f32a83 | 682 | regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); |
0b68d02b BS |
683 | /* period = on + off duration */ |
684 | if (u > 0) | |
685 | val += u; | |
e73b0101 | 686 | else |
0b68d02b BS |
687 | val += UINT_MAX + 1ULL; |
688 | state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); | |
757642f9 | 689 | |
b6730b20 | 690 | regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); |
757642f9 AL |
691 | if (u) |
692 | state->enabled = true; | |
693 | else | |
694 | state->enabled = false; | |
695 | ||
696 | spin_unlock_irqrestore(&mvpwm->lock, flags); | |
6c452cff UKK |
697 | |
698 | return 0; | |
757642f9 AL |
699 | } |
700 | ||
701 | static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
71523d18 | 702 | const struct pwm_state *state) |
757642f9 AL |
703 | { |
704 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); | |
705 | struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; | |
706 | unsigned long long val; | |
707 | unsigned long flags; | |
708 | unsigned int on, off; | |
709 | ||
3ecb1017 UKK |
710 | if (state->polarity != PWM_POLARITY_NORMAL) |
711 | return -EINVAL; | |
712 | ||
757642f9 AL |
713 | val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; |
714 | do_div(val, NSEC_PER_SEC); | |
0b68d02b | 715 | if (val > UINT_MAX + 1ULL) |
757642f9 | 716 | return -EINVAL; |
0b68d02b BS |
717 | /* |
718 | * Zero on/off values don't work as expected. Experimentation shows | |
719 | * that zero value is treated as 2^32. This behavior is not documented. | |
720 | */ | |
721 | if (val == UINT_MAX + 1ULL) | |
722 | on = 0; | |
723 | else if (val) | |
757642f9 AL |
724 | on = val; |
725 | else | |
726 | on = 1; | |
727 | ||
aa37e27f | 728 | val = (unsigned long long) mvpwm->clk_rate * state->period; |
757642f9 | 729 | do_div(val, NSEC_PER_SEC); |
aa37e27f | 730 | val -= on; |
0b68d02b | 731 | if (val > UINT_MAX + 1ULL) |
757642f9 | 732 | return -EINVAL; |
0b68d02b BS |
733 | if (val == UINT_MAX + 1ULL) |
734 | off = 0; | |
735 | else if (val) | |
757642f9 AL |
736 | off = val; |
737 | else | |
738 | off = 1; | |
739 | ||
740 | spin_lock_irqsave(&mvpwm->lock, flags); | |
741 | ||
48f32a83 BS |
742 | regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); |
743 | regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); | |
757642f9 AL |
744 | if (state->enabled) |
745 | mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); | |
746 | else | |
747 | mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); | |
748 | ||
749 | spin_unlock_irqrestore(&mvpwm->lock, flags); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | static const struct pwm_ops mvebu_pwm_ops = { | |
755 | .request = mvebu_pwm_request, | |
756 | .free = mvebu_pwm_free, | |
757 | .get_state = mvebu_pwm_get_state, | |
758 | .apply = mvebu_pwm_apply, | |
759 | .owner = THIS_MODULE, | |
760 | }; | |
761 | ||
762 | static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) | |
763 | { | |
764 | struct mvebu_pwm *mvpwm = mvchip->mvpwm; | |
765 | ||
b6730b20 | 766 | regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, |
2233bf7a | 767 | &mvpwm->blink_select); |
48f32a83 BS |
768 | regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), |
769 | &mvpwm->blink_on_duration); | |
770 | regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), | |
771 | &mvpwm->blink_off_duration); | |
757642f9 AL |
772 | } |
773 | ||
774 | static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) | |
775 | { | |
776 | struct mvebu_pwm *mvpwm = mvchip->mvpwm; | |
777 | ||
b6730b20 | 778 | regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, |
2233bf7a | 779 | mvpwm->blink_select); |
48f32a83 BS |
780 | regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), |
781 | mvpwm->blink_on_duration); | |
782 | regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), | |
783 | mvpwm->blink_off_duration); | |
757642f9 AL |
784 | } |
785 | ||
786 | static int mvebu_pwm_probe(struct platform_device *pdev, | |
787 | struct mvebu_gpio_chip *mvchip, | |
788 | int id) | |
789 | { | |
790 | struct device *dev = &pdev->dev; | |
791 | struct mvebu_pwm *mvpwm; | |
48f32a83 | 792 | void __iomem *base; |
85b7d8ab | 793 | u32 offset; |
757642f9 AL |
794 | u32 set; |
795 | ||
4335417d PR |
796 | if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { |
797 | int ret = of_property_read_u32(dev->of_node, | |
798 | "marvell,pwm-offset", &offset); | |
799 | if (ret < 0) | |
800 | return 0; | |
801 | } else { | |
85b7d8ab BS |
802 | /* |
803 | * There are only two sets of PWM configuration registers for | |
804 | * all the GPIO lines on those SoCs which this driver reserves | |
805 | * for the first two GPIO chips. So if the resource is missing | |
806 | * we can't treat it as an error. | |
807 | */ | |
808 | if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) | |
809 | return 0; | |
810 | offset = 0; | |
85b7d8ab | 811 | } |
19c26d90 | 812 | |
c8da642d UKK |
813 | if (IS_ERR(mvchip->clk)) |
814 | return PTR_ERR(mvchip->clk); | |
815 | ||
757642f9 AL |
816 | mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); |
817 | if (!mvpwm) | |
818 | return -ENOMEM; | |
819 | mvchip->mvpwm = mvpwm; | |
820 | mvpwm->mvchip = mvchip; | |
85b7d8ab BS |
821 | mvpwm->offset = offset; |
822 | ||
823 | if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { | |
824 | mvpwm->regs = mvchip->regs; | |
825 | ||
826 | switch (mvchip->offset) { | |
827 | case AP80X_GPIO0_OFF_A8K: | |
828 | case CP11X_GPIO0_OFF_A8K: | |
829 | /* Blink counter A */ | |
830 | set = 0; | |
831 | break; | |
832 | case CP11X_GPIO1_OFF_A8K: | |
833 | /* Blink counter B */ | |
834 | set = U32_MAX; | |
835 | mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; | |
836 | break; | |
837 | default: | |
838 | return -EINVAL; | |
839 | } | |
840 | } else { | |
841 | base = devm_platform_ioremap_resource_byname(pdev, "pwm"); | |
842 | if (IS_ERR(base)) | |
843 | return PTR_ERR(base); | |
757642f9 | 844 | |
85b7d8ab BS |
845 | mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, |
846 | &mvebu_gpio_regmap_config); | |
847 | if (IS_ERR(mvpwm->regs)) | |
848 | return PTR_ERR(mvpwm->regs); | |
48f32a83 | 849 | |
85b7d8ab BS |
850 | /* |
851 | * Use set A for lines of GPIO chip with id 0, B for GPIO chip | |
852 | * with id 1. Don't allow further GPIO chips to be used for PWM. | |
853 | */ | |
854 | if (id == 0) | |
855 | set = 0; | |
856 | else if (id == 1) | |
857 | set = U32_MAX; | |
858 | else | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | regmap_write(mvchip->regs, | |
863 | GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); | |
757642f9 AL |
864 | |
865 | mvpwm->clk_rate = clk_get_rate(mvchip->clk); | |
866 | if (!mvpwm->clk_rate) { | |
867 | dev_err(dev, "failed to get clock rate\n"); | |
868 | return -EINVAL; | |
869 | } | |
870 | ||
871 | mvpwm->chip.dev = dev; | |
872 | mvpwm->chip.ops = &mvebu_pwm_ops; | |
873 | mvpwm->chip.npwm = mvchip->chip.ngpio; | |
874 | ||
875 | spin_lock_init(&mvpwm->lock); | |
876 | ||
1945063e | 877 | return devm_pwmchip_add(dev, &mvpwm->chip); |
757642f9 AL |
878 | } |
879 | ||
a4ba5e1b SG |
880 | #ifdef CONFIG_DEBUG_FS |
881 | #include <linux/seq_file.h> | |
882 | ||
883 | static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
884 | { | |
bbe76004 | 885 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
a4ba5e1b | 886 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; |
86661fd7 | 887 | const char *label; |
a4ba5e1b SG |
888 | int i; |
889 | ||
b6730b20 GC |
890 | regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); |
891 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); | |
892 | regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); | |
893 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); | |
894 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); | |
2233bf7a TP |
895 | cause = mvebu_gpio_read_edge_cause(mvchip); |
896 | edg_msk = mvebu_gpio_read_edge_mask(mvchip); | |
897 | lvl_msk = mvebu_gpio_read_level_mask(mvchip); | |
a4ba5e1b | 898 | |
86661fd7 | 899 | for_each_requested_gpio(chip, i, label) { |
a4ba5e1b SG |
900 | u32 msk; |
901 | bool is_out; | |
902 | ||
d2cabc4a | 903 | msk = BIT(i); |
a4ba5e1b SG |
904 | is_out = !(io_conf & msk); |
905 | ||
906 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); | |
907 | ||
908 | if (is_out) { | |
909 | seq_printf(s, " out %s %s\n", | |
910 | out & msk ? "hi" : "lo", | |
911 | blink & msk ? "(blink )" : ""); | |
912 | continue; | |
913 | } | |
914 | ||
915 | seq_printf(s, " in %s (act %s) - IRQ", | |
916 | (data_in ^ in_pol) & msk ? "hi" : "lo", | |
917 | in_pol & msk ? "lo" : "hi"); | |
918 | if (!((edg_msk | lvl_msk) & msk)) { | |
a4319a61 | 919 | seq_puts(s, " disabled\n"); |
a4ba5e1b SG |
920 | continue; |
921 | } | |
922 | if (edg_msk & msk) | |
a4319a61 | 923 | seq_puts(s, " edge "); |
a4ba5e1b | 924 | if (lvl_msk & msk) |
a4319a61 | 925 | seq_puts(s, " level"); |
a4ba5e1b SG |
926 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); |
927 | } | |
928 | } | |
929 | #else | |
930 | #define mvebu_gpio_dbg_show NULL | |
931 | #endif | |
932 | ||
271b17b6 | 933 | static const struct of_device_id mvebu_gpio_of_match[] = { |
fefe7b09 TP |
934 | { |
935 | .compatible = "marvell,orion-gpio", | |
a4319a61 | 936 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
fefe7b09 TP |
937 | }, |
938 | { | |
939 | .compatible = "marvell,mv78200-gpio", | |
a4319a61 | 940 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, |
fefe7b09 TP |
941 | }, |
942 | { | |
943 | .compatible = "marvell,armadaxp-gpio", | |
a4319a61 | 944 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, |
fefe7b09 | 945 | }, |
757642f9 | 946 | { |
6c7515c6 | 947 | .compatible = "marvell,armada-370-gpio", |
757642f9 AL |
948 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
949 | }, | |
b6730b20 GC |
950 | { |
951 | .compatible = "marvell,armada-8k-gpio", | |
952 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, | |
953 | }, | |
fefe7b09 TP |
954 | { |
955 | /* sentinel */ | |
956 | }, | |
957 | }; | |
fefe7b09 | 958 | |
b5b7b487 TP |
959 | static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) |
960 | { | |
961 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
962 | int i; | |
963 | ||
b6730b20 GC |
964 | regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, |
965 | &mvchip->out_reg); | |
966 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, | |
967 | &mvchip->io_conf_reg); | |
968 | regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, | |
969 | &mvchip->blink_en_reg); | |
970 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, | |
971 | &mvchip->in_pol_reg); | |
b5b7b487 TP |
972 | |
973 | switch (mvchip->soc_variant) { | |
974 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
b6730b20 GC |
975 | case MVEBU_GPIO_SOC_VARIANT_A8K: |
976 | regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, | |
2233bf7a | 977 | &mvchip->edge_mask_regs[0]); |
b6730b20 | 978 | regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, |
2233bf7a | 979 | &mvchip->level_mask_regs[0]); |
b5b7b487 TP |
980 | break; |
981 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
982 | for (i = 0; i < 2; i++) { | |
2233bf7a TP |
983 | regmap_read(mvchip->regs, |
984 | GPIO_EDGE_MASK_MV78200_OFF(i), | |
985 | &mvchip->edge_mask_regs[i]); | |
986 | regmap_read(mvchip->regs, | |
987 | GPIO_LEVEL_MASK_MV78200_OFF(i), | |
988 | &mvchip->level_mask_regs[i]); | |
b5b7b487 TP |
989 | } |
990 | break; | |
991 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
992 | for (i = 0; i < 4; i++) { | |
2233bf7a TP |
993 | regmap_read(mvchip->regs, |
994 | GPIO_EDGE_MASK_ARMADAXP_OFF(i), | |
995 | &mvchip->edge_mask_regs[i]); | |
996 | regmap_read(mvchip->regs, | |
997 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i), | |
998 | &mvchip->level_mask_regs[i]); | |
b5b7b487 TP |
999 | } |
1000 | break; | |
1001 | default: | |
1002 | BUG(); | |
1003 | } | |
1004 | ||
3101b1e4 | 1005 | if (IS_REACHABLE(CONFIG_PWM)) |
757642f9 AL |
1006 | mvebu_pwm_suspend(mvchip); |
1007 | ||
b5b7b487 TP |
1008 | return 0; |
1009 | } | |
1010 | ||
1011 | static int mvebu_gpio_resume(struct platform_device *pdev) | |
1012 | { | |
1013 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
1014 | int i; | |
1015 | ||
b6730b20 GC |
1016 | regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, |
1017 | mvchip->out_reg); | |
1018 | regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, | |
1019 | mvchip->io_conf_reg); | |
1020 | regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, | |
1021 | mvchip->blink_en_reg); | |
1022 | regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, | |
1023 | mvchip->in_pol_reg); | |
b5b7b487 TP |
1024 | |
1025 | switch (mvchip->soc_variant) { | |
1026 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
b6730b20 GC |
1027 | case MVEBU_GPIO_SOC_VARIANT_A8K: |
1028 | regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, | |
2233bf7a | 1029 | mvchip->edge_mask_regs[0]); |
b6730b20 | 1030 | regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, |
2233bf7a | 1031 | mvchip->level_mask_regs[0]); |
b5b7b487 TP |
1032 | break; |
1033 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
1034 | for (i = 0; i < 2; i++) { | |
2233bf7a TP |
1035 | regmap_write(mvchip->regs, |
1036 | GPIO_EDGE_MASK_MV78200_OFF(i), | |
1037 | mvchip->edge_mask_regs[i]); | |
1038 | regmap_write(mvchip->regs, | |
1039 | GPIO_LEVEL_MASK_MV78200_OFF(i), | |
1040 | mvchip->level_mask_regs[i]); | |
b5b7b487 TP |
1041 | } |
1042 | break; | |
1043 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
1044 | for (i = 0; i < 4; i++) { | |
2233bf7a TP |
1045 | regmap_write(mvchip->regs, |
1046 | GPIO_EDGE_MASK_ARMADAXP_OFF(i), | |
1047 | mvchip->edge_mask_regs[i]); | |
1048 | regmap_write(mvchip->regs, | |
1049 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i), | |
1050 | mvchip->level_mask_regs[i]); | |
b5b7b487 TP |
1051 | } |
1052 | break; | |
1053 | default: | |
1054 | BUG(); | |
1055 | } | |
1056 | ||
3101b1e4 | 1057 | if (IS_REACHABLE(CONFIG_PWM)) |
757642f9 AL |
1058 | mvebu_pwm_resume(mvchip); |
1059 | ||
b5b7b487 TP |
1060 | return 0; |
1061 | } | |
1062 | ||
b6730b20 GC |
1063 | static int mvebu_gpio_probe_raw(struct platform_device *pdev, |
1064 | struct mvebu_gpio_chip *mvchip) | |
1065 | { | |
b6730b20 GC |
1066 | void __iomem *base; |
1067 | ||
dc02a0ca | 1068 | base = devm_platform_ioremap_resource(pdev, 0); |
b6730b20 GC |
1069 | if (IS_ERR(base)) |
1070 | return PTR_ERR(base); | |
1071 | ||
1072 | mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, | |
1073 | &mvebu_gpio_regmap_config); | |
1074 | if (IS_ERR(mvchip->regs)) | |
1075 | return PTR_ERR(mvchip->regs); | |
1076 | ||
1077 | /* | |
1078 | * For the legacy SoCs, the regmap directly maps to the GPIO | |
1079 | * registers, so no offset is needed. | |
1080 | */ | |
1081 | mvchip->offset = 0; | |
1082 | ||
1083 | /* | |
1084 | * The Armada XP has a second range of registers for the | |
1085 | * per-CPU registers | |
1086 | */ | |
1087 | if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { | |
dc02a0ca | 1088 | base = devm_platform_ioremap_resource(pdev, 1); |
b6730b20 GC |
1089 | if (IS_ERR(base)) |
1090 | return PTR_ERR(base); | |
1091 | ||
1092 | mvchip->percpu_regs = | |
1093 | devm_regmap_init_mmio(&pdev->dev, base, | |
1094 | &mvebu_gpio_regmap_config); | |
1095 | if (IS_ERR(mvchip->percpu_regs)) | |
1096 | return PTR_ERR(mvchip->percpu_regs); | |
1097 | } | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int mvebu_gpio_probe_syscon(struct platform_device *pdev, | |
1103 | struct mvebu_gpio_chip *mvchip) | |
1104 | { | |
1105 | mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); | |
1106 | if (IS_ERR(mvchip->regs)) | |
1107 | return PTR_ERR(mvchip->regs); | |
1108 | ||
1109 | if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) | |
1110 | return -EINVAL; | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
644ee702 BG |
1115 | static void mvebu_gpio_remove_irq_domain(void *data) |
1116 | { | |
1117 | struct irq_domain *domain = data; | |
1118 | ||
1119 | irq_domain_remove(domain); | |
1120 | } | |
1121 | ||
3836309d | 1122 | static int mvebu_gpio_probe(struct platform_device *pdev) |
fefe7b09 TP |
1123 | { |
1124 | struct mvebu_gpio_chip *mvchip; | |
1125 | const struct of_device_id *match; | |
1126 | struct device_node *np = pdev->dev.of_node; | |
fefe7b09 TP |
1127 | struct irq_chip_generic *gc; |
1128 | struct irq_chip_type *ct; | |
1129 | unsigned int ngpios; | |
812d4788 | 1130 | bool have_irqs; |
fefe7b09 TP |
1131 | int soc_variant; |
1132 | int i, cpu, id; | |
f1d2d081 | 1133 | int err; |
fefe7b09 TP |
1134 | |
1135 | match = of_match_device(mvebu_gpio_of_match, &pdev->dev); | |
1136 | if (match) | |
f0d50460 | 1137 | soc_variant = (unsigned long) match->data; |
fefe7b09 TP |
1138 | else |
1139 | soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; | |
1140 | ||
812d4788 | 1141 | /* Some gpio controllers do not provide irq support */ |
0c21639f PF |
1142 | err = platform_irq_count(pdev); |
1143 | if (err < 0) | |
1144 | return err; | |
1145 | ||
1146 | have_irqs = err != 0; | |
812d4788 | 1147 | |
a4319a61 AL |
1148 | mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), |
1149 | GFP_KERNEL); | |
6c8365f6 | 1150 | if (!mvchip) |
fefe7b09 | 1151 | return -ENOMEM; |
fefe7b09 | 1152 | |
b5b7b487 TP |
1153 | platform_set_drvdata(pdev, mvchip); |
1154 | ||
fefe7b09 TP |
1155 | if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { |
1156 | dev_err(&pdev->dev, "Missing ngpios OF property\n"); | |
1157 | return -ENODEV; | |
1158 | } | |
1159 | ||
1160 | id = of_alias_get_id(pdev->dev.of_node, "gpio"); | |
1161 | if (id < 0) { | |
1162 | dev_err(&pdev->dev, "Couldn't get OF id\n"); | |
1163 | return id; | |
1164 | } | |
1165 | ||
757642f9 | 1166 | mvchip->clk = devm_clk_get(&pdev->dev, NULL); |
de88747f | 1167 | /* Not all SoCs require a clock.*/ |
757642f9 AL |
1168 | if (!IS_ERR(mvchip->clk)) |
1169 | clk_prepare_enable(mvchip->clk); | |
de88747f | 1170 | |
fefe7b09 TP |
1171 | mvchip->soc_variant = soc_variant; |
1172 | mvchip->chip.label = dev_name(&pdev->dev); | |
58383c78 | 1173 | mvchip->chip.parent = &pdev->dev; |
203f0daa JG |
1174 | mvchip->chip.request = gpiochip_generic_request; |
1175 | mvchip->chip.free = gpiochip_generic_free; | |
e8dacf59 | 1176 | mvchip->chip.get_direction = mvebu_gpio_get_direction; |
fefe7b09 TP |
1177 | mvchip->chip.direction_input = mvebu_gpio_direction_input; |
1178 | mvchip->chip.get = mvebu_gpio_get; | |
1179 | mvchip->chip.direction_output = mvebu_gpio_direction_output; | |
1180 | mvchip->chip.set = mvebu_gpio_set; | |
812d4788 JG |
1181 | if (have_irqs) |
1182 | mvchip->chip.to_irq = mvebu_gpio_to_irq; | |
fefe7b09 TP |
1183 | mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; |
1184 | mvchip->chip.ngpio = ngpios; | |
9fb1f39e | 1185 | mvchip->chip.can_sleep = false; |
a4ba5e1b | 1186 | mvchip->chip.dbg_show = mvebu_gpio_dbg_show; |
fefe7b09 | 1187 | |
b6730b20 GC |
1188 | if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) |
1189 | err = mvebu_gpio_probe_syscon(pdev, mvchip); | |
1190 | else | |
1191 | err = mvebu_gpio_probe_raw(pdev, mvchip); | |
fefe7b09 | 1192 | |
b6730b20 GC |
1193 | if (err) |
1194 | return err; | |
fefe7b09 TP |
1195 | |
1196 | /* | |
1197 | * Mask and clear GPIO interrupts. | |
1198 | */ | |
f4dcd2d9 | 1199 | switch (soc_variant) { |
fefe7b09 | 1200 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
b6730b20 GC |
1201 | case MVEBU_GPIO_SOC_VARIANT_A8K: |
1202 | regmap_write(mvchip->regs, | |
1203 | GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); | |
1204 | regmap_write(mvchip->regs, | |
1205 | GPIO_EDGE_MASK_OFF + mvchip->offset, 0); | |
1206 | regmap_write(mvchip->regs, | |
1207 | GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); | |
fefe7b09 TP |
1208 | break; |
1209 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
2233bf7a | 1210 | regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); |
fefe7b09 | 1211 | for (cpu = 0; cpu < 2; cpu++) { |
2233bf7a TP |
1212 | regmap_write(mvchip->regs, |
1213 | GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); | |
1214 | regmap_write(mvchip->regs, | |
1215 | GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); | |
fefe7b09 TP |
1216 | } |
1217 | break; | |
1218 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
2233bf7a TP |
1219 | regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); |
1220 | regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); | |
1221 | regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); | |
fefe7b09 | 1222 | for (cpu = 0; cpu < 4; cpu++) { |
2233bf7a TP |
1223 | regmap_write(mvchip->percpu_regs, |
1224 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); | |
1225 | regmap_write(mvchip->percpu_regs, | |
1226 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); | |
1227 | regmap_write(mvchip->percpu_regs, | |
1228 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); | |
fefe7b09 TP |
1229 | } |
1230 | break; | |
1231 | default: | |
1232 | BUG(); | |
1233 | } | |
1234 | ||
00b9ab4a | 1235 | devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); |
fefe7b09 | 1236 | |
7ee1a01e | 1237 | /* Some MVEBU SoCs have simple PWM support for GPIO lines */ |
3101b1e4 | 1238 | if (IS_REACHABLE(CONFIG_PWM)) { |
7ee1a01e BS |
1239 | err = mvebu_pwm_probe(pdev, mvchip, id); |
1240 | if (err) | |
1241 | return err; | |
1242 | } | |
1243 | ||
fefe7b09 | 1244 | /* Some gpio controllers do not provide irq support */ |
812d4788 | 1245 | if (!have_irqs) |
fefe7b09 TP |
1246 | return 0; |
1247 | ||
812d4788 JG |
1248 | mvchip->domain = |
1249 | irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); | |
1250 | if (!mvchip->domain) { | |
1251 | dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", | |
1252 | mvchip->chip.label); | |
1945063e | 1253 | return -ENODEV; |
fefe7b09 TP |
1254 | } |
1255 | ||
644ee702 BG |
1256 | err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, |
1257 | mvchip->domain); | |
1258 | if (err) | |
1259 | return err; | |
1260 | ||
812d4788 JG |
1261 | err = irq_alloc_domain_generic_chips( |
1262 | mvchip->domain, ngpios, 2, np->name, handle_level_irq, | |
1263 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); | |
1264 | if (err) { | |
1265 | dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", | |
1266 | mvchip->chip.label); | |
644ee702 | 1267 | return err; |
fefe7b09 TP |
1268 | } |
1269 | ||
899c37ed RS |
1270 | /* |
1271 | * NOTE: The common accessors cannot be used because of the percpu | |
812d4788 JG |
1272 | * access to the mask registers |
1273 | */ | |
1274 | gc = irq_get_domain_generic_chip(mvchip->domain, 0); | |
fefe7b09 TP |
1275 | gc->private = mvchip; |
1276 | ct = &gc->chip_types[0]; | |
1277 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
1278 | ct->chip.irq_mask = mvebu_gpio_level_irq_mask; | |
1279 | ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; | |
1280 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
1281 | ct->chip.name = mvchip->chip.label; | |
1282 | ||
1283 | ct = &gc->chip_types[1]; | |
1284 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
1285 | ct->chip.irq_ack = mvebu_gpio_irq_ack; | |
1286 | ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; | |
1287 | ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; | |
1288 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
1289 | ct->handler = handle_edge_irq; | |
1290 | ct->chip.name = mvchip->chip.label; | |
1291 | ||
899c37ed RS |
1292 | /* |
1293 | * Setup the interrupt handlers. Each chip can have up to 4 | |
812d4788 JG |
1294 | * interrupt handlers, with each handler dealing with 8 GPIO |
1295 | * pins. | |
1296 | */ | |
1297 | for (i = 0; i < 4; i++) { | |
525b0858 | 1298 | int irq = platform_get_irq_optional(pdev, i); |
fefe7b09 | 1299 | |
812d4788 JG |
1300 | if (irq < 0) |
1301 | continue; | |
1302 | irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, | |
1303 | mvchip); | |
fefe7b09 TP |
1304 | } |
1305 | ||
1306 | return 0; | |
1307 | } | |
1308 | ||
1309 | static struct platform_driver mvebu_gpio_driver = { | |
1310 | .driver = { | |
a4319a61 | 1311 | .name = "mvebu-gpio", |
fefe7b09 TP |
1312 | .of_match_table = mvebu_gpio_of_match, |
1313 | }, | |
1314 | .probe = mvebu_gpio_probe, | |
b5b7b487 TP |
1315 | .suspend = mvebu_gpio_suspend, |
1316 | .resume = mvebu_gpio_resume, | |
fefe7b09 | 1317 | }; |
ed329f3a | 1318 | builtin_platform_driver(mvebu_gpio_driver); |