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fefe7b09 TP |
1 | /* |
2 | * GPIO driver for Marvell SoCs | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * Andrew Lunn <andrew@lunn.ch> | |
8 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * This driver is a fairly straightforward GPIO driver for the | |
15 | * complete family of Marvell EBU SoC platforms (Orion, Dove, | |
16 | * Kirkwood, Discovery, Armada 370/XP). The only complexity of this | |
17 | * driver is the different register layout that exists between the | |
18 | * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP | |
19 | * platforms (MV78200 from the Discovery family and the Armada | |
20 | * XP). Therefore, this driver handles three variants of the GPIO | |
21 | * block: | |
22 | * - the basic variant, called "orion-gpio", with the simplest | |
23 | * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and | |
24 | * non-SMP Discovery systems | |
25 | * - the mv78200 variant for MV78200 Discovery systems. This variant | |
26 | * turns the edge mask and level mask registers into CPU0 edge | |
27 | * mask/level mask registers, and adds CPU1 edge mask/level mask | |
28 | * registers. | |
29 | * - the armadaxp variant for Armada XP systems. This variant keeps | |
30 | * the normal cause/edge mask/level mask registers when the global | |
31 | * interrupts are used, but adds per-CPU cause/edge mask/level mask | |
32 | * registers n a separate memory area for the per-CPU GPIO | |
33 | * interrupts. | |
34 | */ | |
35 | ||
641d0342 | 36 | #include <linux/err.h> |
ed329f3a | 37 | #include <linux/init.h> |
fefe7b09 TP |
38 | #include <linux/gpio.h> |
39 | #include <linux/irq.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/irqdomain.h> | |
42 | #include <linux/io.h> | |
43 | #include <linux/of_irq.h> | |
44 | #include <linux/of_device.h> | |
de88747f | 45 | #include <linux/clk.h> |
fefe7b09 | 46 | #include <linux/pinctrl/consumer.h> |
01ca59f1 | 47 | #include <linux/irqchip/chained_irq.h> |
fefe7b09 TP |
48 | |
49 | /* | |
50 | * GPIO unit register offsets. | |
51 | */ | |
52 | #define GPIO_OUT_OFF 0x0000 | |
53 | #define GPIO_IO_CONF_OFF 0x0004 | |
54 | #define GPIO_BLINK_EN_OFF 0x0008 | |
55 | #define GPIO_IN_POL_OFF 0x000c | |
56 | #define GPIO_DATA_IN_OFF 0x0010 | |
57 | #define GPIO_EDGE_CAUSE_OFF 0x0014 | |
58 | #define GPIO_EDGE_MASK_OFF 0x0018 | |
59 | #define GPIO_LEVEL_MASK_OFF 0x001c | |
60 | ||
61 | /* The MV78200 has per-CPU registers for edge mask and level mask */ | |
a4319a61 | 62 | #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) |
fefe7b09 TP |
63 | #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) |
64 | ||
7077f4cc RS |
65 | /* |
66 | * The Armada XP has per-CPU registers for interrupt cause, interrupt | |
fefe7b09 | 67 | * mask and interrupt level mask. Those are relative to the |
7077f4cc RS |
68 | * percpu_membase. |
69 | */ | |
fefe7b09 TP |
70 | #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) |
71 | #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) | |
72 | #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) | |
73 | ||
a4319a61 AL |
74 | #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 |
75 | #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 | |
fefe7b09 TP |
76 | #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 |
77 | ||
a4319a61 | 78 | #define MVEBU_MAX_GPIO_PER_BANK 32 |
fefe7b09 TP |
79 | |
80 | struct mvebu_gpio_chip { | |
81 | struct gpio_chip chip; | |
82 | spinlock_t lock; | |
83 | void __iomem *membase; | |
84 | void __iomem *percpu_membase; | |
d5359226 | 85 | int irqbase; |
fefe7b09 | 86 | struct irq_domain *domain; |
a4319a61 | 87 | int soc_variant; |
b5b7b487 | 88 | |
a4319a61 | 89 | /* Used to preserve GPIO registers across suspend/resume */ |
b5b7b487 TP |
90 | u32 out_reg; |
91 | u32 io_conf_reg; | |
92 | u32 blink_en_reg; | |
93 | u32 in_pol_reg; | |
94 | u32 edge_mask_regs[4]; | |
95 | u32 level_mask_regs[4]; | |
fefe7b09 TP |
96 | }; |
97 | ||
98 | /* | |
99 | * Functions returning addresses of individual registers for a given | |
100 | * GPIO controller. | |
101 | */ | |
102 | static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) | |
103 | { | |
104 | return mvchip->membase + GPIO_OUT_OFF; | |
105 | } | |
106 | ||
e9133760 JL |
107 | static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) |
108 | { | |
109 | return mvchip->membase + GPIO_BLINK_EN_OFF; | |
110 | } | |
111 | ||
a4319a61 AL |
112 | static inline void __iomem * |
113 | mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) | |
fefe7b09 TP |
114 | { |
115 | return mvchip->membase + GPIO_IO_CONF_OFF; | |
116 | } | |
117 | ||
118 | static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) | |
119 | { | |
120 | return mvchip->membase + GPIO_IN_POL_OFF; | |
121 | } | |
122 | ||
a4319a61 AL |
123 | static inline void __iomem * |
124 | mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) | |
fefe7b09 TP |
125 | { |
126 | return mvchip->membase + GPIO_DATA_IN_OFF; | |
127 | } | |
128 | ||
a4319a61 AL |
129 | static inline void __iomem * |
130 | mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) | |
fefe7b09 TP |
131 | { |
132 | int cpu; | |
133 | ||
f4dcd2d9 | 134 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
135 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
136 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
137 | return mvchip->membase + GPIO_EDGE_CAUSE_OFF; | |
138 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
139 | cpu = smp_processor_id(); | |
a4319a61 AL |
140 | return mvchip->percpu_membase + |
141 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); | |
fefe7b09 TP |
142 | default: |
143 | BUG(); | |
144 | } | |
145 | } | |
146 | ||
a4319a61 AL |
147 | static inline void __iomem * |
148 | mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) | |
fefe7b09 TP |
149 | { |
150 | int cpu; | |
151 | ||
f4dcd2d9 | 152 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
153 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
154 | return mvchip->membase + GPIO_EDGE_MASK_OFF; | |
155 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
156 | cpu = smp_processor_id(); | |
157 | return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); | |
158 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
159 | cpu = smp_processor_id(); | |
a4319a61 AL |
160 | return mvchip->percpu_membase + |
161 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); | |
fefe7b09 TP |
162 | default: |
163 | BUG(); | |
164 | } | |
165 | } | |
166 | ||
167 | static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) | |
168 | { | |
169 | int cpu; | |
170 | ||
f4dcd2d9 | 171 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
172 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
173 | return mvchip->membase + GPIO_LEVEL_MASK_OFF; | |
174 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
175 | cpu = smp_processor_id(); | |
176 | return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); | |
177 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
178 | cpu = smp_processor_id(); | |
a4319a61 AL |
179 | return mvchip->percpu_membase + |
180 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); | |
fefe7b09 TP |
181 | default: |
182 | BUG(); | |
183 | } | |
184 | } | |
185 | ||
186 | /* | |
187 | * Functions implementing the gpio_chip methods | |
188 | */ | |
189 | ||
d276de70 | 190 | static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) |
fefe7b09 | 191 | { |
bbe76004 | 192 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
193 | unsigned long flags; |
194 | u32 u; | |
195 | ||
196 | spin_lock_irqsave(&mvchip->lock, flags); | |
197 | u = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
198 | if (value) | |
199 | u |= 1 << pin; | |
200 | else | |
201 | u &= ~(1 << pin); | |
202 | writel_relaxed(u, mvebu_gpioreg_out(mvchip)); | |
203 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
204 | } | |
205 | ||
d276de70 | 206 | static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 207 | { |
bbe76004 | 208 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
209 | u32 u; |
210 | ||
211 | if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { | |
212 | u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ | |
213 | readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
214 | } else { | |
215 | u = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
216 | } | |
217 | ||
218 | return (u >> pin) & 1; | |
219 | } | |
220 | ||
d276de70 RS |
221 | static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, |
222 | int value) | |
e9133760 | 223 | { |
bbe76004 | 224 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
e9133760 JL |
225 | unsigned long flags; |
226 | u32 u; | |
227 | ||
228 | spin_lock_irqsave(&mvchip->lock, flags); | |
229 | u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); | |
230 | if (value) | |
231 | u |= 1 << pin; | |
232 | else | |
233 | u &= ~(1 << pin); | |
234 | writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); | |
235 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
236 | } | |
237 | ||
d276de70 | 238 | static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 239 | { |
bbe76004 | 240 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
241 | unsigned long flags; |
242 | int ret; | |
243 | u32 u; | |
244 | ||
7077f4cc RS |
245 | /* |
246 | * Check with the pinctrl driver whether this pin is usable as | |
247 | * an input GPIO | |
248 | */ | |
fefe7b09 TP |
249 | ret = pinctrl_gpio_direction_input(chip->base + pin); |
250 | if (ret) | |
251 | return ret; | |
252 | ||
253 | spin_lock_irqsave(&mvchip->lock, flags); | |
254 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
255 | u |= 1 << pin; | |
256 | writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); | |
257 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
d276de70 | 262 | static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, |
fefe7b09 TP |
263 | int value) |
264 | { | |
bbe76004 | 265 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
266 | unsigned long flags; |
267 | int ret; | |
268 | u32 u; | |
269 | ||
7077f4cc RS |
270 | /* |
271 | * Check with the pinctrl driver whether this pin is usable as | |
272 | * an output GPIO | |
273 | */ | |
fefe7b09 TP |
274 | ret = pinctrl_gpio_direction_output(chip->base + pin); |
275 | if (ret) | |
276 | return ret; | |
277 | ||
e9133760 | 278 | mvebu_gpio_blink(chip, pin, 0); |
c57d75c0 TP |
279 | mvebu_gpio_set(chip, pin, value); |
280 | ||
fefe7b09 TP |
281 | spin_lock_irqsave(&mvchip->lock, flags); |
282 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
283 | u &= ~(1 << pin); | |
284 | writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); | |
285 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
d276de70 | 290 | static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 291 | { |
bbe76004 | 292 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
163ad364 | 293 | |
fefe7b09 TP |
294 | return irq_create_mapping(mvchip->domain, pin); |
295 | } | |
296 | ||
297 | /* | |
298 | * Functions implementing the irq_chip methods | |
299 | */ | |
300 | static void mvebu_gpio_irq_ack(struct irq_data *d) | |
301 | { | |
302 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
303 | struct mvebu_gpio_chip *mvchip = gc->private; | |
812d4788 | 304 | u32 mask = d->mask; |
fefe7b09 TP |
305 | |
306 | irq_gc_lock(gc); | |
812d4788 | 307 | writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip)); |
fefe7b09 TP |
308 | irq_gc_unlock(gc); |
309 | } | |
310 | ||
311 | static void mvebu_gpio_edge_irq_mask(struct irq_data *d) | |
312 | { | |
313 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
314 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 315 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 316 | u32 mask = d->mask; |
fefe7b09 TP |
317 | |
318 | irq_gc_lock(gc); | |
61819549 GC |
319 | ct->mask_cache_priv &= ~mask; |
320 | ||
321 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); | |
fefe7b09 TP |
322 | irq_gc_unlock(gc); |
323 | } | |
324 | ||
325 | static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) | |
326 | { | |
327 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
328 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 329 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 330 | u32 mask = d->mask; |
fefe7b09 TP |
331 | |
332 | irq_gc_lock(gc); | |
61819549 GC |
333 | ct->mask_cache_priv |= mask; |
334 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); | |
fefe7b09 TP |
335 | irq_gc_unlock(gc); |
336 | } | |
337 | ||
338 | static void mvebu_gpio_level_irq_mask(struct irq_data *d) | |
339 | { | |
340 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
341 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 342 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 343 | u32 mask = d->mask; |
fefe7b09 TP |
344 | |
345 | irq_gc_lock(gc); | |
61819549 GC |
346 | ct->mask_cache_priv &= ~mask; |
347 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); | |
fefe7b09 TP |
348 | irq_gc_unlock(gc); |
349 | } | |
350 | ||
351 | static void mvebu_gpio_level_irq_unmask(struct irq_data *d) | |
352 | { | |
353 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
354 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 355 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 356 | u32 mask = d->mask; |
fefe7b09 TP |
357 | |
358 | irq_gc_lock(gc); | |
61819549 GC |
359 | ct->mask_cache_priv |= mask; |
360 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); | |
fefe7b09 TP |
361 | irq_gc_unlock(gc); |
362 | } | |
363 | ||
364 | /***************************************************************************** | |
365 | * MVEBU GPIO IRQ | |
366 | * | |
367 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same | |
368 | * value of the line or the opposite value. | |
369 | * | |
370 | * Level IRQ handlers: DATA_IN is used directly as cause register. | |
a4319a61 | 371 | * Interrupt are masked by LEVEL_MASK registers. |
fefe7b09 | 372 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. |
a4319a61 | 373 | * Interrupt are masked by EDGE_MASK registers. |
fefe7b09 | 374 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps |
a4319a61 AL |
375 | * the polarity to catch the next line transaction. |
376 | * This is a race condition that might not perfectly | |
377 | * work on some use cases. | |
fefe7b09 TP |
378 | * |
379 | * Every eight GPIO lines are grouped (OR'ed) before going up to main | |
380 | * cause register. | |
381 | * | |
a4319a61 AL |
382 | * EDGE cause mask |
383 | * data-in /--------| |-----| |----\ | |
384 | * -----| |----- ---- to main cause reg | |
385 | * X \----------------| |----/ | |
386 | * polarity LEVEL mask | |
fefe7b09 TP |
387 | * |
388 | ****************************************************************************/ | |
389 | ||
390 | static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
391 | { | |
392 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
393 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
394 | struct mvebu_gpio_chip *mvchip = gc->private; | |
395 | int pin; | |
396 | u32 u; | |
397 | ||
398 | pin = d->hwirq; | |
399 | ||
400 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); | |
a4319a61 | 401 | if (!u) |
fefe7b09 | 402 | return -EINVAL; |
fefe7b09 TP |
403 | |
404 | type &= IRQ_TYPE_SENSE_MASK; | |
405 | if (type == IRQ_TYPE_NONE) | |
406 | return -EINVAL; | |
407 | ||
408 | /* Check if we need to change chip and handler */ | |
409 | if (!(ct->type & type)) | |
410 | if (irq_setup_alt_chip(d, type)) | |
411 | return -EINVAL; | |
412 | ||
413 | /* | |
414 | * Configure interrupt polarity. | |
415 | */ | |
f4dcd2d9 | 416 | switch (type) { |
fefe7b09 TP |
417 | case IRQ_TYPE_EDGE_RISING: |
418 | case IRQ_TYPE_LEVEL_HIGH: | |
419 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
420 | u &= ~(1 << pin); | |
421 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); | |
7cf8c9f7 | 422 | break; |
fefe7b09 TP |
423 | case IRQ_TYPE_EDGE_FALLING: |
424 | case IRQ_TYPE_LEVEL_LOW: | |
425 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
426 | u |= 1 << pin; | |
427 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); | |
7cf8c9f7 | 428 | break; |
fefe7b09 TP |
429 | case IRQ_TYPE_EDGE_BOTH: { |
430 | u32 v; | |
431 | ||
432 | v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ | |
433 | readl_relaxed(mvebu_gpioreg_data_in(mvchip)); | |
434 | ||
435 | /* | |
436 | * set initial polarity based on current input level | |
437 | */ | |
438 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
439 | if (v & (1 << pin)) | |
440 | u |= 1 << pin; /* falling */ | |
441 | else | |
442 | u &= ~(1 << pin); /* rising */ | |
443 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); | |
7cf8c9f7 | 444 | break; |
fefe7b09 TP |
445 | } |
446 | } | |
447 | return 0; | |
448 | } | |
449 | ||
bd0b9ac4 | 450 | static void mvebu_gpio_irq_handler(struct irq_desc *desc) |
fefe7b09 | 451 | { |
476f8b4c | 452 | struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); |
01ca59f1 | 453 | struct irq_chip *chip = irq_desc_get_chip(desc); |
fefe7b09 TP |
454 | u32 cause, type; |
455 | int i; | |
456 | ||
457 | if (mvchip == NULL) | |
458 | return; | |
459 | ||
01ca59f1 TP |
460 | chained_irq_enter(chip, desc); |
461 | ||
fefe7b09 TP |
462 | cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & |
463 | readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); | |
464 | cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & | |
465 | readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); | |
466 | ||
467 | for (i = 0; i < mvchip->chip.ngpio; i++) { | |
468 | int irq; | |
469 | ||
812d4788 | 470 | irq = irq_find_mapping(mvchip->domain, i); |
fefe7b09 TP |
471 | |
472 | if (!(cause & (1 << i))) | |
473 | continue; | |
474 | ||
fb90c22a | 475 | type = irq_get_trigger_type(irq); |
fefe7b09 TP |
476 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
477 | /* Swap polarity (race with GPIO line) */ | |
478 | u32 polarity; | |
479 | ||
480 | polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
481 | polarity ^= 1 << i; | |
482 | writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); | |
483 | } | |
01ca59f1 | 484 | |
fefe7b09 TP |
485 | generic_handle_irq(irq); |
486 | } | |
01ca59f1 TP |
487 | |
488 | chained_irq_exit(chip, desc); | |
fefe7b09 TP |
489 | } |
490 | ||
a4ba5e1b SG |
491 | #ifdef CONFIG_DEBUG_FS |
492 | #include <linux/seq_file.h> | |
493 | ||
494 | static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
495 | { | |
bbe76004 | 496 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
a4ba5e1b SG |
497 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; |
498 | int i; | |
499 | ||
500 | out = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
501 | io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
502 | blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); | |
503 | in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
504 | data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); | |
505 | cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); | |
506 | edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); | |
507 | lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); | |
508 | ||
509 | for (i = 0; i < chip->ngpio; i++) { | |
510 | const char *label; | |
511 | u32 msk; | |
512 | bool is_out; | |
513 | ||
514 | label = gpiochip_is_requested(chip, i); | |
515 | if (!label) | |
516 | continue; | |
517 | ||
518 | msk = 1 << i; | |
519 | is_out = !(io_conf & msk); | |
520 | ||
521 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); | |
522 | ||
523 | if (is_out) { | |
524 | seq_printf(s, " out %s %s\n", | |
525 | out & msk ? "hi" : "lo", | |
526 | blink & msk ? "(blink )" : ""); | |
527 | continue; | |
528 | } | |
529 | ||
530 | seq_printf(s, " in %s (act %s) - IRQ", | |
531 | (data_in ^ in_pol) & msk ? "hi" : "lo", | |
532 | in_pol & msk ? "lo" : "hi"); | |
533 | if (!((edg_msk | lvl_msk) & msk)) { | |
a4319a61 | 534 | seq_puts(s, " disabled\n"); |
a4ba5e1b SG |
535 | continue; |
536 | } | |
537 | if (edg_msk & msk) | |
a4319a61 | 538 | seq_puts(s, " edge "); |
a4ba5e1b | 539 | if (lvl_msk & msk) |
a4319a61 | 540 | seq_puts(s, " level"); |
a4ba5e1b SG |
541 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); |
542 | } | |
543 | } | |
544 | #else | |
545 | #define mvebu_gpio_dbg_show NULL | |
546 | #endif | |
547 | ||
271b17b6 | 548 | static const struct of_device_id mvebu_gpio_of_match[] = { |
fefe7b09 TP |
549 | { |
550 | .compatible = "marvell,orion-gpio", | |
a4319a61 | 551 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
fefe7b09 TP |
552 | }, |
553 | { | |
554 | .compatible = "marvell,mv78200-gpio", | |
a4319a61 | 555 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, |
fefe7b09 TP |
556 | }, |
557 | { | |
558 | .compatible = "marvell,armadaxp-gpio", | |
a4319a61 | 559 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, |
fefe7b09 TP |
560 | }, |
561 | { | |
562 | /* sentinel */ | |
563 | }, | |
564 | }; | |
fefe7b09 | 565 | |
b5b7b487 TP |
566 | static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) |
567 | { | |
568 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
569 | int i; | |
570 | ||
571 | mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); | |
572 | mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); | |
573 | mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); | |
574 | mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); | |
575 | ||
576 | switch (mvchip->soc_variant) { | |
577 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
578 | mvchip->edge_mask_regs[0] = | |
579 | readl(mvchip->membase + GPIO_EDGE_MASK_OFF); | |
580 | mvchip->level_mask_regs[0] = | |
581 | readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
582 | break; | |
583 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
584 | for (i = 0; i < 2; i++) { | |
585 | mvchip->edge_mask_regs[i] = | |
586 | readl(mvchip->membase + | |
587 | GPIO_EDGE_MASK_MV78200_OFF(i)); | |
588 | mvchip->level_mask_regs[i] = | |
589 | readl(mvchip->membase + | |
590 | GPIO_LEVEL_MASK_MV78200_OFF(i)); | |
591 | } | |
592 | break; | |
593 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
594 | for (i = 0; i < 4; i++) { | |
595 | mvchip->edge_mask_regs[i] = | |
596 | readl(mvchip->membase + | |
597 | GPIO_EDGE_MASK_ARMADAXP_OFF(i)); | |
598 | mvchip->level_mask_regs[i] = | |
599 | readl(mvchip->membase + | |
600 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); | |
601 | } | |
602 | break; | |
603 | default: | |
604 | BUG(); | |
605 | } | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int mvebu_gpio_resume(struct platform_device *pdev) | |
611 | { | |
612 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
613 | int i; | |
614 | ||
615 | writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); | |
616 | writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); | |
617 | writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); | |
618 | writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); | |
619 | ||
620 | switch (mvchip->soc_variant) { | |
621 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
622 | writel(mvchip->edge_mask_regs[0], | |
623 | mvchip->membase + GPIO_EDGE_MASK_OFF); | |
624 | writel(mvchip->level_mask_regs[0], | |
625 | mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
626 | break; | |
627 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
628 | for (i = 0; i < 2; i++) { | |
629 | writel(mvchip->edge_mask_regs[i], | |
630 | mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); | |
631 | writel(mvchip->level_mask_regs[i], | |
632 | mvchip->membase + | |
633 | GPIO_LEVEL_MASK_MV78200_OFF(i)); | |
634 | } | |
635 | break; | |
636 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
637 | for (i = 0; i < 4; i++) { | |
638 | writel(mvchip->edge_mask_regs[i], | |
639 | mvchip->membase + | |
640 | GPIO_EDGE_MASK_ARMADAXP_OFF(i)); | |
641 | writel(mvchip->level_mask_regs[i], | |
642 | mvchip->membase + | |
643 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); | |
644 | } | |
645 | break; | |
646 | default: | |
647 | BUG(); | |
648 | } | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
3836309d | 653 | static int mvebu_gpio_probe(struct platform_device *pdev) |
fefe7b09 TP |
654 | { |
655 | struct mvebu_gpio_chip *mvchip; | |
656 | const struct of_device_id *match; | |
657 | struct device_node *np = pdev->dev.of_node; | |
658 | struct resource *res; | |
659 | struct irq_chip_generic *gc; | |
660 | struct irq_chip_type *ct; | |
de88747f | 661 | struct clk *clk; |
fefe7b09 | 662 | unsigned int ngpios; |
812d4788 | 663 | bool have_irqs; |
fefe7b09 TP |
664 | int soc_variant; |
665 | int i, cpu, id; | |
f1d2d081 | 666 | int err; |
fefe7b09 TP |
667 | |
668 | match = of_match_device(mvebu_gpio_of_match, &pdev->dev); | |
669 | if (match) | |
f0d50460 | 670 | soc_variant = (unsigned long) match->data; |
fefe7b09 TP |
671 | else |
672 | soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; | |
673 | ||
812d4788 JG |
674 | /* Some gpio controllers do not provide irq support */ |
675 | have_irqs = of_irq_count(np) != 0; | |
676 | ||
a4319a61 AL |
677 | mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), |
678 | GFP_KERNEL); | |
6c8365f6 | 679 | if (!mvchip) |
fefe7b09 | 680 | return -ENOMEM; |
fefe7b09 | 681 | |
b5b7b487 TP |
682 | platform_set_drvdata(pdev, mvchip); |
683 | ||
fefe7b09 TP |
684 | if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { |
685 | dev_err(&pdev->dev, "Missing ngpios OF property\n"); | |
686 | return -ENODEV; | |
687 | } | |
688 | ||
689 | id = of_alias_get_id(pdev->dev.of_node, "gpio"); | |
690 | if (id < 0) { | |
691 | dev_err(&pdev->dev, "Couldn't get OF id\n"); | |
692 | return id; | |
693 | } | |
694 | ||
de88747f AL |
695 | clk = devm_clk_get(&pdev->dev, NULL); |
696 | /* Not all SoCs require a clock.*/ | |
697 | if (!IS_ERR(clk)) | |
698 | clk_prepare_enable(clk); | |
699 | ||
fefe7b09 TP |
700 | mvchip->soc_variant = soc_variant; |
701 | mvchip->chip.label = dev_name(&pdev->dev); | |
58383c78 | 702 | mvchip->chip.parent = &pdev->dev; |
203f0daa JG |
703 | mvchip->chip.request = gpiochip_generic_request; |
704 | mvchip->chip.free = gpiochip_generic_free; | |
fefe7b09 TP |
705 | mvchip->chip.direction_input = mvebu_gpio_direction_input; |
706 | mvchip->chip.get = mvebu_gpio_get; | |
707 | mvchip->chip.direction_output = mvebu_gpio_direction_output; | |
708 | mvchip->chip.set = mvebu_gpio_set; | |
812d4788 JG |
709 | if (have_irqs) |
710 | mvchip->chip.to_irq = mvebu_gpio_to_irq; | |
fefe7b09 TP |
711 | mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; |
712 | mvchip->chip.ngpio = ngpios; | |
9fb1f39e | 713 | mvchip->chip.can_sleep = false; |
fefe7b09 | 714 | mvchip->chip.of_node = np; |
a4ba5e1b | 715 | mvchip->chip.dbg_show = mvebu_gpio_dbg_show; |
fefe7b09 TP |
716 | |
717 | spin_lock_init(&mvchip->lock); | |
08a67a58 | 718 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
641d0342 | 719 | mvchip->membase = devm_ioremap_resource(&pdev->dev, res); |
422d26b6 | 720 | if (IS_ERR(mvchip->membase)) |
641d0342 | 721 | return PTR_ERR(mvchip->membase); |
fefe7b09 | 722 | |
7077f4cc RS |
723 | /* |
724 | * The Armada XP has a second range of registers for the | |
725 | * per-CPU registers | |
726 | */ | |
fefe7b09 TP |
727 | if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { |
728 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
641d0342 TR |
729 | mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, |
730 | res); | |
f4dcd2d9 | 731 | if (IS_ERR(mvchip->percpu_membase)) |
641d0342 | 732 | return PTR_ERR(mvchip->percpu_membase); |
fefe7b09 TP |
733 | } |
734 | ||
735 | /* | |
736 | * Mask and clear GPIO interrupts. | |
737 | */ | |
f4dcd2d9 | 738 | switch (soc_variant) { |
fefe7b09 TP |
739 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
740 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
741 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); | |
742 | writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
743 | break; | |
744 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
745 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
746 | for (cpu = 0; cpu < 2; cpu++) { | |
747 | writel_relaxed(0, mvchip->membase + | |
748 | GPIO_EDGE_MASK_MV78200_OFF(cpu)); | |
749 | writel_relaxed(0, mvchip->membase + | |
750 | GPIO_LEVEL_MASK_MV78200_OFF(cpu)); | |
751 | } | |
752 | break; | |
753 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
754 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
755 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); | |
756 | writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
757 | for (cpu = 0; cpu < 4; cpu++) { | |
758 | writel_relaxed(0, mvchip->percpu_membase + | |
759 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); | |
760 | writel_relaxed(0, mvchip->percpu_membase + | |
761 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); | |
762 | writel_relaxed(0, mvchip->percpu_membase + | |
763 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); | |
764 | } | |
765 | break; | |
766 | default: | |
767 | BUG(); | |
768 | } | |
769 | ||
00b9ab4a | 770 | devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); |
fefe7b09 TP |
771 | |
772 | /* Some gpio controllers do not provide irq support */ | |
812d4788 | 773 | if (!have_irqs) |
fefe7b09 TP |
774 | return 0; |
775 | ||
812d4788 JG |
776 | mvchip->domain = |
777 | irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); | |
778 | if (!mvchip->domain) { | |
779 | dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", | |
780 | mvchip->chip.label); | |
781 | return -ENODEV; | |
fefe7b09 TP |
782 | } |
783 | ||
812d4788 JG |
784 | err = irq_alloc_domain_generic_chips( |
785 | mvchip->domain, ngpios, 2, np->name, handle_level_irq, | |
786 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); | |
787 | if (err) { | |
788 | dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", | |
789 | mvchip->chip.label); | |
790 | goto err_domain; | |
fefe7b09 TP |
791 | } |
792 | ||
899c37ed RS |
793 | /* |
794 | * NOTE: The common accessors cannot be used because of the percpu | |
812d4788 JG |
795 | * access to the mask registers |
796 | */ | |
797 | gc = irq_get_domain_generic_chip(mvchip->domain, 0); | |
fefe7b09 TP |
798 | gc->private = mvchip; |
799 | ct = &gc->chip_types[0]; | |
800 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
801 | ct->chip.irq_mask = mvebu_gpio_level_irq_mask; | |
802 | ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; | |
803 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
804 | ct->chip.name = mvchip->chip.label; | |
805 | ||
806 | ct = &gc->chip_types[1]; | |
807 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
808 | ct->chip.irq_ack = mvebu_gpio_irq_ack; | |
809 | ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; | |
810 | ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; | |
811 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
812 | ct->handler = handle_edge_irq; | |
813 | ct->chip.name = mvchip->chip.label; | |
814 | ||
899c37ed RS |
815 | /* |
816 | * Setup the interrupt handlers. Each chip can have up to 4 | |
812d4788 JG |
817 | * interrupt handlers, with each handler dealing with 8 GPIO |
818 | * pins. | |
819 | */ | |
820 | for (i = 0; i < 4; i++) { | |
821 | int irq = platform_get_irq(pdev, i); | |
fefe7b09 | 822 | |
812d4788 JG |
823 | if (irq < 0) |
824 | continue; | |
825 | irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, | |
826 | mvchip); | |
fefe7b09 TP |
827 | } |
828 | ||
829 | return 0; | |
f1d2d081 | 830 | |
812d4788 JG |
831 | err_domain: |
832 | irq_domain_remove(mvchip->domain); | |
f1d2d081 | 833 | |
f1d2d081 | 834 | return err; |
fefe7b09 TP |
835 | } |
836 | ||
837 | static struct platform_driver mvebu_gpio_driver = { | |
838 | .driver = { | |
a4319a61 | 839 | .name = "mvebu-gpio", |
fefe7b09 TP |
840 | .of_match_table = mvebu_gpio_of_match, |
841 | }, | |
842 | .probe = mvebu_gpio_probe, | |
b5b7b487 TP |
843 | .suspend = mvebu_gpio_suspend, |
844 | .resume = mvebu_gpio_resume, | |
fefe7b09 | 845 | }; |
ed329f3a | 846 | builtin_platform_driver(mvebu_gpio_driver); |