[linux-2.6-block.git] / drivers / gpio / gpio-mt7621.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 */

#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>

#define MTK_BANK_CNT	3
#define MTK_BANK_WIDTH	32

#define GPIO_BANK_STRIDE	0x04
#define GPIO_REG_CTRL		0x00
#define GPIO_REG_POL		0x10
#define GPIO_REG_DATA		0x20
#define GPIO_REG_DSET		0x30
#define GPIO_REG_DCLR		0x40
#define GPIO_REG_REDGE		0x50
#define GPIO_REG_FEDGE		0x60
#define GPIO_REG_HLVL		0x70
#define GPIO_REG_LLVL		0x80
#define GPIO_REG_STAT		0x90
#define GPIO_REG_EDGE		0xA0

struct mtk_gc {
	struct irq_chip irq_chip;
	struct gpio_chip chip;
	spinlock_t lock;
	int bank;
	u32 rising;
	u32 falling;
	u32 hlevel;
	u32 llevel;
};

/**
 * struct mtk - state container for
 * data of the platform driver. It is 3
 * separate gpio-chip each one with its
 * own irq_chip.
 * @dev: device instance
 * @base: memory base address
 * @gpio_irq: irq number from the device tree
 * @gc_map: array of the gpio chips
 */
struct mtk {
	struct device *dev;
	void __iomem *base;
	int gpio_irq;
	struct mtk_gc gc_map[MTK_BANK_CNT];
};

static inline struct mtk_gc *
to_mediatek_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct mtk_gc, chip);
}

static inline void
mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
{
	struct gpio_chip *gc = &rg->chip;
	struct mtk *mtk = gpiochip_get_data(gc);

	offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
	gc->write_reg(mtk->base + offset, val);
}

static inline u32
mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
{
	struct gpio_chip *gc = &rg->chip;
	struct mtk *mtk = gpiochip_get_data(gc);

	offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
	return gc->read_reg(mtk->base + offset);
}

static irqreturn_t
mediatek_gpio_irq_handler(int irq, void *data)
{
	struct gpio_chip *gc = data;
	struct mtk_gc *rg = to_mediatek_gpio(gc);
	irqreturn_t ret = IRQ_NONE;
	unsigned long pending;
	int bit;

	pending = mtk_gpio_r32(rg, GPIO_REG_STAT);

	for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
		u32 map = irq_find_mapping(gc->irq.domain, bit);

		generic_handle_irq(map);
		mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
		ret |= IRQ_HANDLED;
	}

	return ret;
}

static void
mediatek_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct mtk_gc *rg = to_mediatek_gpio(gc);
	int pin = d->hwirq;
	unsigned long flags;
	u32 rise, fall, high, low;

	spin_lock_irqsave(&rg->lock, flags);
	rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
	fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
	high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
	low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
	mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
	mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
	mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
	mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
	spin_unlock_irqrestore(&rg->lock, flags);
}

static void
mediatek_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct mtk_gc *rg = to_mediatek_gpio(gc);
	int pin = d->hwirq;
	unsigned long flags;
	u32 rise, fall, high, low;

	spin_lock_irqsave(&rg->lock, flags);
	rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
	fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
	high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
	low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
	mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
	mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
	mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
	mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
	spin_unlock_irqrestore(&rg->lock, flags);
}

static int
mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct mtk_gc *rg = to_mediatek_gpio(gc);
	int pin = d->hwirq;
	u32 mask = BIT(pin);

	if (type == IRQ_TYPE_PROBE) {
		if ((rg->rising | rg->falling |
		     rg->hlevel | rg->llevel) & mask)
			return 0;

		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	rg->rising &= ~mask;
	rg->falling &= ~mask;
	rg->hlevel &= ~mask;
	rg->llevel &= ~mask;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_BOTH:
		rg->rising |= mask;
		rg->falling |= mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		rg->rising |= mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		rg->falling |= mask;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		rg->hlevel |= mask;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		rg->llevel |= mask;
		break;
	}

	return 0;
}

static int
mediatek_gpio_xlate(struct gpio_chip *chip,
		    const struct of_phandle_args *spec, u32 *flags)
{
	int gpio = spec->args[0];
	struct mtk_gc *rg = to_mediatek_gpio(chip);

	if (rg->bank != gpio / MTK_BANK_WIDTH)
		return -EINVAL;

	if (flags)
		*flags = spec->args[1];

	return gpio % MTK_BANK_WIDTH;
}

static int
mediatek_gpio_bank_probe(struct device *dev,
			 struct device_node *node, int bank)
{
	struct mtk *mtk = dev_get_drvdata(dev);
	struct mtk_gc *rg;
	void __iomem *dat, *set, *ctrl, *diro;
	int ret;

	rg = &mtk->gc_map[bank];
	memset(rg, 0, sizeof(*rg));

	spin_lock_init(&rg->lock);
	rg->chip.of_node = node;
	rg->bank = bank;

	dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
	set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
	ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
	diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);

	ret = bgpio_init(&rg->chip, dev, 4,
			 dat, set, ctrl, diro, NULL, 0);
	if (ret) {
		dev_err(dev, "bgpio_init() failed\n");
		return ret;
	}

	rg->chip.of_gpio_n_cells = 2;
	rg->chip.of_xlate = mediatek_gpio_xlate;
	rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
					dev_name(dev), bank);
	if (!rg->chip.label)
		return -ENOMEM;

	ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
	if (ret < 0) {
		dev_err(dev, "Could not register gpio %d, ret=%d\n",
			rg->chip.ngpio, ret);
		return ret;
	}

	rg->irq_chip.name = dev_name(dev);
	rg->irq_chip.parent_device = dev;
	rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
	rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
	rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
	rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;

	if (mtk->gpio_irq) {
		/*
		 * Manually request the irq here instead of passing
		 * a flow-handler to gpiochip_set_chained_irqchip,
		 * because the irq is shared.
		 */
		ret = devm_request_irq(dev, mtk->gpio_irq,
				       mediatek_gpio_irq_handler, IRQF_SHARED,
				       rg->chip.label, &rg->chip);

		if (ret) {
			dev_err(dev, "Error requesting IRQ %d: %d\n",
				mtk->gpio_irq, ret);
			return ret;
		}

		ret = gpiochip_irqchip_add(&rg->chip, &rg->irq_chip,
					   0, handle_simple_irq, IRQ_TYPE_NONE);
		if (ret) {
			dev_err(dev, "failed to add gpiochip_irqchip\n");
			return ret;
		}

		gpiochip_set_chained_irqchip(&rg->chip, &rg->irq_chip,
					     mtk->gpio_irq, NULL);
	}

	/* set polarity to low for all gpios */
	mtk_gpio_w32(rg, GPIO_REG_POL, 0);

	dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);

	return 0;
}

static int
mediatek_gpio_probe(struct platform_device *pdev)
{
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct mtk *mtk;
	int i;
	int ret;

	mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
	if (!mtk)
		return -ENOMEM;

	mtk->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(mtk->base))
		return PTR_ERR(mtk->base);

	mtk->gpio_irq = irq_of_parse_and_map(np, 0);
	mtk->dev = dev;
	platform_set_drvdata(pdev, mtk);

	for (i = 0; i < MTK_BANK_CNT; i++) {
		ret = mediatek_gpio_bank_probe(dev, np, i);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct of_device_id mediatek_gpio_match[] = {
	{ .compatible = "mediatek,mt7621-gpio" },
	{},
};
MODULE_DEVICE_TABLE(of, mediatek_gpio_match);

static struct platform_driver mediatek_gpio_driver = {
	.probe = mediatek_gpio_probe,
	.driver = {
		.name = "mt7621_gpio",
		.of_match_table = mediatek_gpio_match,
	},
};

builtin_platform_driver(mediatek_gpio_driver);
Commit	Line	Data
4ba9c3af SP	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	4	* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
	5	*/
	6
	7	#include <linux/err.h>
	8	#include <linux/gpio/driver.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/io.h>
	11	#include <linux/module.h>
	12	#include <linux/of_irq.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/spinlock.h>
	15
	16	#define MTK_BANK_CNT 3
	17	#define MTK_BANK_WIDTH 32
	18
	19	#define GPIO_BANK_STRIDE 0x04
	20	#define GPIO_REG_CTRL 0x00
	21	#define GPIO_REG_POL 0x10
	22	#define GPIO_REG_DATA 0x20
	23	#define GPIO_REG_DSET 0x30
	24	#define GPIO_REG_DCLR 0x40
	25	#define GPIO_REG_REDGE 0x50
	26	#define GPIO_REG_FEDGE 0x60
	27	#define GPIO_REG_HLVL 0x70
	28	#define GPIO_REG_LLVL 0x80
	29	#define GPIO_REG_STAT 0x90
	30	#define GPIO_REG_EDGE 0xA0
	31
	32	struct mtk_gc {
fa84667b	33	struct irq_chip irq_chip;
4ba9c3af SP	34	struct gpio_chip chip;
	35	spinlock_t lock;
	36	int bank;
	37	u32 rising;
	38	u32 falling;
	39	u32 hlevel;
	40	u32 llevel;
	41	};
	42
	43	/**
8512486b	44	* struct mtk - state container for
4ba9c3af SP	45	* data of the platform driver. It is 3
	46	* separate gpio-chip each one with its
	47	* own irq_chip.
	48	* @dev: device instance
8512486b	49	* @base: memory base address
4ba9c3af SP	50	* @gpio_irq: irq number from the device tree
	51	* @gc_map: array of the gpio chips
	52	*/
8512486b	53	struct mtk {
4ba9c3af	54	struct device *dev;
8512486b	55	void __iomem *base;
4ba9c3af SP	56	int gpio_irq;
	57	struct mtk_gc gc_map[MTK_BANK_CNT];
	58	};
	59
	60	static inline struct mtk_gc *
	61	to_mediatek_gpio(struct gpio_chip *chip)
	62	{
	63	return container_of(chip, struct mtk_gc, chip);
	64	}
	65
	66	static inline void
	67	mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
	68	{
	69	struct gpio_chip *gc = &rg->chip;
8512486b	70	struct mtk *mtk = gpiochip_get_data(gc);
4ba9c3af SP	71
4ba9c3af SP	72	offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
8512486b	73	gc->write_reg(mtk->base + offset, val);
4ba9c3af SP	74	}
	75
	76	static inline u32
	77	mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
	78	{
	79	struct gpio_chip *gc = &rg->chip;
8512486b	80	struct mtk *mtk = gpiochip_get_data(gc);
4ba9c3af SP	81
4ba9c3af SP	82	offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
8512486b	83	return gc->read_reg(mtk->base + offset);
4ba9c3af SP	84	}
	85
	86	static irqreturn_t
	87	mediatek_gpio_irq_handler(int irq, void *data)
	88	{
	89	struct gpio_chip *gc = data;
	90	struct mtk_gc *rg = to_mediatek_gpio(gc);
	91	irqreturn_t ret = IRQ_NONE;
	92	unsigned long pending;
	93	int bit;
	94
	95	pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
	96
	97	for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
	98	u32 map = irq_find_mapping(gc->irq.domain, bit);
	99
	100	generic_handle_irq(map);
	101	mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
	102	ret \|= IRQ_HANDLED;
	103	}
	104
	105	return ret;
	106	}
	107
	108	static void
	109	mediatek_gpio_irq_unmask(struct irq_data *d)
	110	{
	111	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	112	struct mtk_gc *rg = to_mediatek_gpio(gc);
	113	int pin = d->hwirq;
	114	unsigned long flags;
	115	u32 rise, fall, high, low;
	116
	117	spin_lock_irqsave(&rg->lock, flags);
	118	rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
	119	fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
	120	high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
	121	low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
	122	mtk_gpio_w32(rg, GPIO_REG_REDGE, rise \| (BIT(pin) & rg->rising));
	123	mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall \| (BIT(pin) & rg->falling));
	124	mtk_gpio_w32(rg, GPIO_REG_HLVL, high \| (BIT(pin) & rg->hlevel));
	125	mtk_gpio_w32(rg, GPIO_REG_LLVL, low \| (BIT(pin) & rg->llevel));
	126	spin_unlock_irqrestore(&rg->lock, flags);
	127	}
	128
	129	static void
	130	mediatek_gpio_irq_mask(struct irq_data *d)
	131	{
	132	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	133	struct mtk_gc *rg = to_mediatek_gpio(gc);
	134	int pin = d->hwirq;
	135	unsigned long flags;
	136	u32 rise, fall, high, low;
	137
	138	spin_lock_irqsave(&rg->lock, flags);
	139	rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
	140	fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
	141	high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
	142	low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
	143	mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
	144	mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
	145	mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
	146	mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
	147	spin_unlock_irqrestore(&rg->lock, flags);
148	}
149
150	static int
151	mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
152	{
153	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
154	struct mtk_gc *rg = to_mediatek_gpio(gc);
155	int pin = d->hwirq;
156	u32 mask = BIT(pin);
157
158	if (type == IRQ_TYPE_PROBE) {
159	if ((rg->rising \| rg->falling \|
160	rg->hlevel \| rg->llevel) & mask)
161	return 0;
162
163	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
164	}
165
166	rg->rising &= ~mask;
167	rg->falling &= ~mask;
168	rg->hlevel &= ~mask;
169	rg->llevel &= ~mask;
170
171	switch (type & IRQ_TYPE_SENSE_MASK) {
172	case IRQ_TYPE_EDGE_BOTH:
173	rg->rising \|= mask;
174	rg->falling \|= mask;
175	break;
176	case IRQ_TYPE_EDGE_RISING:
177	rg->rising \|= mask;
178	break;
179	case IRQ_TYPE_EDGE_FALLING:
180	rg->falling \|= mask;
181	break;
182	case IRQ_TYPE_LEVEL_HIGH:
183	rg->hlevel \|= mask;
184	break;
185	case IRQ_TYPE_LEVEL_LOW:
186	rg->llevel \|= mask;
187	break;
188	}
189
190	return 0;
191	}
192
4ba9c3af SP	193	static int
	194	mediatek_gpio_xlate(struct gpio_chip *chip,
	195	const struct of_phandle_args spec, u32 flags)
	196	{
	197	int gpio = spec->args[0];
	198	struct mtk_gc *rg = to_mediatek_gpio(chip);
	199
	200	if (rg->bank != gpio / MTK_BANK_WIDTH)
	201	return -EINVAL;
	202
	203	if (flags)
	204	*flags = spec->args[1];
	205
	206	return gpio % MTK_BANK_WIDTH;
	207	}
	208
	209	static int
8512486b	210	mediatek_gpio_bank_probe(struct device *dev,
4ba9c3af SP	211	struct device_node *node, int bank)
4ba9c3af SP	212	{
8512486b	213	struct mtk *mtk = dev_get_drvdata(dev);
4ba9c3af SP	214	struct mtk_gc *rg;
	215	void __iomem dat, set, ctrl, diro;
	216	int ret;
	217
8512486b	218	rg = &mtk->gc_map[bank];
4ba9c3af SP	219	memset(rg, 0, sizeof(*rg));
	220
	221	spin_lock_init(&rg->lock);
	222	rg->chip.of_node = node;
	223	rg->bank = bank;
	224
8512486b LW	225	dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
	226	set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
	227	ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
	228	diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
4ba9c3af	229
8512486b	230	ret = bgpio_init(&rg->chip, dev, 4,
4ba9c3af SP	231	dat, set, ctrl, diro, NULL, 0);
4ba9c3af SP	232	if (ret) {
8512486b	233	dev_err(dev, "bgpio_init() failed\n");
4ba9c3af SP	234	return ret;
	235	}
	236
	237	rg->chip.of_gpio_n_cells = 2;
	238	rg->chip.of_xlate = mediatek_gpio_xlate;
8512486b LW	239	rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
8512486b LW	240	dev_name(dev), bank);
59d646c7 NMG	241	if (!rg->chip.label)
59d646c7 NMG	242	return -ENOMEM;
4ba9c3af	243
8512486b	244	ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
4ba9c3af	245	if (ret < 0) {
8512486b	246	dev_err(dev, "Could not register gpio %d, ret=%d\n",
4ba9c3af SP	247	rg->chip.ngpio, ret);
	248	return ret;
	249	}
	250
fa84667b RD	251	rg->irq_chip.name = dev_name(dev);
	252	rg->irq_chip.parent_device = dev;
	253	rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
	254	rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
	255	rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
	256	rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
	257
8512486b	258	if (mtk->gpio_irq) {
4ba9c3af SP	259	/*
	260	* Manually request the irq here instead of passing
	261	* a flow-handler to gpiochip_set_chained_irqchip,
	262	* because the irq is shared.
	263	*/
8512486b	264	ret = devm_request_irq(dev, mtk->gpio_irq,
4ba9c3af SP	265	mediatek_gpio_irq_handler, IRQF_SHARED,
	266	rg->chip.label, &rg->chip);
	267
	268	if (ret) {
8512486b LW	269	dev_err(dev, "Error requesting IRQ %d: %d\n",
8512486b LW	270	mtk->gpio_irq, ret);
4ba9c3af SP	271	return ret;
	272	}
	273
fa84667b	274	ret = gpiochip_irqchip_add(&rg->chip, &rg->irq_chip,
4ba9c3af SP	275	0, handle_simple_irq, IRQ_TYPE_NONE);
4ba9c3af SP	276	if (ret) {
8512486b	277	dev_err(dev, "failed to add gpiochip_irqchip\n");
4ba9c3af SP	278	return ret;
	279	}
	280
fa84667b	281	gpiochip_set_chained_irqchip(&rg->chip, &rg->irq_chip,
8512486b	282	mtk->gpio_irq, NULL);
4ba9c3af SP	283	}
	284
	285	/* set polarity to low for all gpios */
	286	mtk_gpio_w32(rg, GPIO_REG_POL, 0);
	287
8512486b	288	dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
4ba9c3af SP	289
	290	return 0;
	291	}
	292
	293	static int
	294	mediatek_gpio_probe(struct platform_device *pdev)
	295	{
4ba9c3af	296	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8512486b LW	297	struct device *dev = &pdev->dev;
	298	struct device_node *np = dev->of_node;
	299	struct mtk *mtk;
4ba9c3af	300	int i;
a109c2db	301	int ret;
4ba9c3af	302
8512486b LW	303	mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
8512486b LW	304	if (!mtk)
4ba9c3af SP	305	return -ENOMEM;
4ba9c3af SP	306
8512486b LW	307	mtk->base = devm_ioremap_resource(dev, res);
	308	if (IS_ERR(mtk->base))
	309	return PTR_ERR(mtk->base);
4ba9c3af	310
8512486b LW	311	mtk->gpio_irq = irq_of_parse_and_map(np, 0);
	312	mtk->dev = dev;
	313	platform_set_drvdata(pdev, mtk);
4ba9c3af	314
a109c2db NMG	315	for (i = 0; i < MTK_BANK_CNT; i++) {
	316	ret = mediatek_gpio_bank_probe(dev, np, i);
	317	if (ret)
	318	return ret;
	319	}
4ba9c3af SP	320
	321	return 0;
	322	}
	323
	324	static const struct of_device_id mediatek_gpio_match[] = {
	325	{ .compatible = "mediatek,mt7621-gpio" },
	326	{},
	327	};
	328	MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
	329
	330	static struct platform_driver mediatek_gpio_driver = {
	331	.probe = mediatek_gpio_probe,
	332	.driver = {
	333	.name = "mt7621_gpio",
	334	.of_match_table = mediatek_gpio_match,
	335	},
	336	};
	337
	338	builtin_platform_driver(mediatek_gpio_driver);