[linux-block.git] / drivers / gpio / gpio-mpc8xxx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
 *
 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2016 Freescale Semiconductor Inc.
 */

#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>

#define MPC8XXX_GPIO_PINS	32

#define GPIO_DIR		0x00
#define GPIO_ODR		0x04
#define GPIO_DAT		0x08
#define GPIO_IER		0x0c
#define GPIO_IMR		0x10
#define GPIO_ICR		0x14
#define GPIO_ICR2		0x18
#define GPIO_IBE		0x18

struct mpc8xxx_gpio_chip {
	struct gpio_chip	gc;
	void __iomem *regs;
	raw_spinlock_t lock;

	int (*direction_output)(struct gpio_chip *chip,
				unsigned offset, int value);

	struct irq_domain *irq;
	int irqn;
};

/*
 * This hardware has a big endian bit assignment such that GPIO line 0 is
 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
 * This inline helper give the right bitmask for a certain line.
 */
static inline u32 mpc_pin2mask(unsigned int offset)
{
	return BIT(31 - offset);
}

/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 * defined as output cannot be determined by reading GPDAT register,
 * so we use shadow data register instead. The status of input pins
 * is determined by reading GPDAT register.
 */
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	u32 val;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	u32 out_mask, out_shadow;

	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
	out_shadow = gc->bgpio_data & out_mask;

	return !!((val | out_shadow) & mpc_pin2mask(gpio));
}

static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
				unsigned int gpio, int val)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	/* GPIO 28..31 are input only on MPC5121 */
	if (gpio >= 28)
		return -EINVAL;

	return mpc8xxx_gc->direction_output(gc, gpio, val);
}

static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
				unsigned int gpio, int val)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	/* GPIO 0..3 are input only on MPC5125 */
	if (gpio <= 3)
		return -EINVAL;

	return mpc8xxx_gc->direction_output(gc, gpio, val);
}

static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);

	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
		return irq_create_mapping(mpc8xxx_gc->irq, offset);
	else
		return -ENXIO;
}

static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long mask;
	int i;

	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
		& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
	for_each_set_bit(i, &mask, 32)
		generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);

	return IRQ_HANDLED;
}

static void mpc8xxx_irq_unmask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
		| mpc_pin2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_mask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
		& ~mpc_pin2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_ack(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
		      mpc_pin2mask(irqd_to_hwirq(d)));
}

static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
			| mpc_pin2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
			& ~mpc_pin2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long gpio = irqd_to_hwirq(d);
	void __iomem *reg;
	unsigned int shift;
	unsigned long flags;

	if (gpio < 16) {
		reg = mpc8xxx_gc->regs + GPIO_ICR;
		shift = (15 - gpio) * 2;
	} else {
		reg = mpc8xxx_gc->regs + GPIO_ICR2;
		shift = (15 - (gpio % 16)) * 2;
	}

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
			| (2 << shift));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_LEVEL_HIGH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
			| (1 << shift));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip mpc8xxx_irq_chip = {
	.name		= "mpc8xxx-gpio",
	.irq_unmask	= mpc8xxx_irq_unmask,
	.irq_mask	= mpc8xxx_irq_mask,
	.irq_ack	= mpc8xxx_irq_ack,
	/* this might get overwritten in mpc8xxx_probe() */
	.irq_set_type	= mpc8xxx_irq_set_type,
};

static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);

	return 0;
}

static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
	.map	= mpc8xxx_gpio_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

struct mpc8xxx_gpio_devtype {
	int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
	int (*gpio_get)(struct gpio_chip *, unsigned int);
	int (*irq_set_type)(struct irq_data *, unsigned int);
};

static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	.gpio_dir_out = mpc5121_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	.gpio_dir_out = mpc5125_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	.gpio_get = mpc8572_gpio_get,
};

static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
	.irq_set_type = mpc8xxx_irq_set_type,
};

static const struct of_device_id mpc8xxx_gpio_ids[] = {
	{ .compatible = "fsl,mpc8349-gpio", },
	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
	{ .compatible = "fsl,mpc8610-gpio", },
	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
	{ .compatible = "fsl,pq3-gpio",     },
	{ .compatible = "fsl,ls1028a-gpio", },
	{ .compatible = "fsl,ls1088a-gpio", },
	{ .compatible = "fsl,qoriq-gpio",   },
	{}
};

static int mpc8xxx_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
	struct gpio_chip	*gc;
	const struct mpc8xxx_gpio_devtype *devtype = NULL;
	struct fwnode_handle *fwnode;
	int ret;

	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	if (!mpc8xxx_gc)
		return -ENOMEM;

	platform_set_drvdata(pdev, mpc8xxx_gc);

	raw_spin_lock_init(&mpc8xxx_gc->lock);

	mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mpc8xxx_gc->regs))
		return PTR_ERR(mpc8xxx_gc->regs);

	gc = &mpc8xxx_gc->gc;
	gc->parent = &pdev->dev;

	if (device_property_read_bool(&pdev->dev, "little-endian")) {
		ret = bgpio_init(gc, &pdev->dev, 4,
				 mpc8xxx_gc->regs + GPIO_DAT,
				 NULL, NULL,
				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
				 BGPIOF_BIG_ENDIAN);
		if (ret)
			return ret;
		dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
	} else {
		ret = bgpio_init(gc, &pdev->dev, 4,
				 mpc8xxx_gc->regs + GPIO_DAT,
				 NULL, NULL,
				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
				 BGPIOF_BIG_ENDIAN
				 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
		if (ret)
			return ret;
		dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
	}

	mpc8xxx_gc->direction_output = gc->direction_output;

	devtype = device_get_match_data(&pdev->dev);
	if (!devtype)
		devtype = &mpc8xxx_gpio_devtype_default;

	/*
	 * It's assumed that only a single type of gpio controller is available
	 * on the current machine, so overwriting global data is fine.
	 */
	if (devtype->irq_set_type)
		mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;

	if (devtype->gpio_dir_out)
		gc->direction_output = devtype->gpio_dir_out;
	if (devtype->gpio_get)
		gc->get = devtype->gpio_get;

	gc->to_irq = mpc8xxx_gpio_to_irq;

	/*
	 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
	 * the input enable of each individual GPIO port.  When an individual
	 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
	 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
	 * the port value to the GPIO Data Register.
	 */
	fwnode = dev_fwnode(&pdev->dev);
	if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
	    of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
	    of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
	    is_acpi_node(fwnode))
		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);

	ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
	if (ret) {
		dev_err(&pdev->dev,
			"GPIO chip registration failed with status %d\n", ret);
		return ret;
	}

	mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
	if (mpc8xxx_gc->irqn < 0)
		return mpc8xxx_gc->irqn;

	mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
						   MPC8XXX_GPIO_PINS,
						   &mpc8xxx_gpio_irq_ops,
						   mpc8xxx_gc);

	if (!mpc8xxx_gc->irq)
		return 0;

	/* ack and mask all irqs */
	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);

	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
			       mpc8xxx_gpio_irq_cascade,
			       IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
			       mpc8xxx_gc);
	if (ret) {
		dev_err(&pdev->dev,
			"failed to devm_request_irq(%d), ret = %d\n",
			mpc8xxx_gc->irqn, ret);
		goto err;
	}

	return 0;
err:
	irq_domain_remove(mpc8xxx_gc->irq);
	return ret;
}

static int mpc8xxx_remove(struct platform_device *pdev)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);

	if (mpc8xxx_gc->irq) {
		irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
		irq_domain_remove(mpc8xxx_gc->irq);
	}

	return 0;
}

#ifdef CONFIG_ACPI
static const struct acpi_device_id gpio_acpi_ids[] = {
	{"NXP0031",},
	{ }
};
MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
#endif

static struct platform_driver mpc8xxx_plat_driver = {
	.probe		= mpc8xxx_probe,
	.remove		= mpc8xxx_remove,
	.driver		= {
		.name = "gpio-mpc8xxx",
		.of_match_table	= mpc8xxx_gpio_ids,
		.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
	},
};

static int __init mpc8xxx_init(void)
{
	return platform_driver_register(&mpc8xxx_plat_driver);
}

arch_initcall(mpc8xxx_init);
Commit	Line	Data
3bb16560	1	// SPDX-License-Identifier: GPL-2.0-only
1e16dfc1	2	/*
42178e2a	3	* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
1e16dfc1 PK	4	*
1e16dfc1 PK	5	* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
42178e2a	6	* Copyright (C) 2016 Freescale Semiconductor Inc.
1e16dfc1 PK	7	*/
1e16dfc1 PK	8
76c47d14	9	#include <linux/acpi.h>
1e16dfc1 PK	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/spinlock.h>
	13	#include <linux/io.h>
	14	#include <linux/of.h>
	15	#include <linux/of_gpio.h>
42178e2a	16	#include <linux/of_address.h>
5af50730	17	#include <linux/of_irq.h>
98686d9a	18	#include <linux/of_platform.h>
76c47d14 RW	19	#include <linux/property.h>
76c47d14 RW	20	#include <linux/mod_devicetable.h>
5a0e3ad6	21	#include <linux/slab.h>
345e5c8a	22	#include <linux/irq.h>
42178e2a	23	#include <linux/gpio/driver.h>
b3222f71	24	#include <linux/bitops.h>
698b8eea	25	#include <linux/interrupt.h>
1e16dfc1 PK	26
	27	#define MPC8XXX_GPIO_PINS 32
	28
	29	#define GPIO_DIR 0x00
	30	#define GPIO_ODR 0x04
	31	#define GPIO_DAT 0x08
	32	#define GPIO_IER 0x0c
	33	#define GPIO_IMR 0x10
	34	#define GPIO_ICR 0x14
e39d5ef6	35	#define GPIO_ICR2 0x18
bd4bd337	36	#define GPIO_IBE 0x18
1e16dfc1 PK	37
1e16dfc1 PK	38	struct mpc8xxx_gpio_chip {
42178e2a LG	39	struct gpio_chip gc;
42178e2a LG	40	void __iomem *regs;
50593613	41	raw_spinlock_t lock;
1e16dfc1	42
42178e2a LG	43	int (direction_output)(struct gpio_chip chip,
	44	unsigned offset, int value);
	45
bae1d8f1	46	struct irq_domain *irq;
9f51ce0b	47	int irqn;
1e16dfc1 PK	48	};
1e16dfc1 PK	49
b3222f71 LW	50	/*
	51	* This hardware has a big endian bit assignment such that GPIO line 0 is
	52	* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
	53	* This inline helper give the right bitmask for a certain line.
	54	*/
	55	static inline u32 mpc_pin2mask(unsigned int offset)
	56	{
	57	return BIT(31 - offset);
	58	}
	59
c1a676df FR	60	/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
	61	* defined as output cannot be determined by reading GPDAT register,
	62	* so we use shadow data register instead. The status of input pins
	63	* is determined by reading GPDAT register.
	64	*/
	65	static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	66	{
	67	u32 val;
709d71a1	68	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1aeef303	69	u32 out_mask, out_shadow;
c1a676df	70
cd0d3f58 AL	71	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
cd0d3f58 AL	72	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
42178e2a	73	out_shadow = gc->bgpio_data & out_mask;
1aeef303	74
b3222f71	75	return !!((val \| out_shadow) & mpc_pin2mask(gpio));
c1a676df FR	76	}
c1a676df FR	77
42178e2a LG	78	static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
42178e2a LG	79	unsigned int gpio, int val)
1e16dfc1	80	{
709d71a1	81	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
28538df0 WS	82	/* GPIO 28..31 are input only on MPC5121 */
	83	if (gpio >= 28)
	84	return -EINVAL;
	85
42178e2a	86	return mpc8xxx_gc->direction_output(gc, gpio, val);
28538df0 WS	87	}
28538df0 WS	88
42178e2a LG	89	static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
42178e2a LG	90	unsigned int gpio, int val)
0ba69e08	91	{
42178e2a	92	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0ba69e08 UKK	93	/* GPIO 0..3 are input only on MPC5125 */
	94	if (gpio <= 3)
	95	return -EINVAL;
	96
42178e2a	97	return mpc8xxx_gc->direction_output(gc, gpio, val);
0ba69e08 UKK	98	}
0ba69e08 UKK	99
345e5c8a PK	100	static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
345e5c8a PK	101	{
709d71a1	102	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
345e5c8a PK	103
	104	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
	105	return irq_create_mapping(mpc8xxx_gc->irq, offset);
	106	else
	107	return -ENXIO;
	108	}
	109
698b8eea	110	static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
345e5c8a	111	{
698b8eea	112	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
cd0d3f58	113	struct gpio_chip *gc = &mpc8xxx_gc->gc;
698b8eea SH	114	unsigned long mask;
698b8eea SH	115	int i;
345e5c8a	116
cd0d3f58 AL	117	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
cd0d3f58 AL	118	& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
698b8eea	119	for_each_set_bit(i, &mask, 32)
dbd1c54f	120	generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
698b8eea SH	121
698b8eea SH	122	return IRQ_HANDLED;
345e5c8a PK	123	}
345e5c8a PK	124
94347cb3	125	static void mpc8xxx_irq_unmask(struct irq_data *d)
345e5c8a	126	{
94347cb3	127	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	128	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	129	unsigned long flags;
345e5c8a PK	130
50593613	131	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	132
cd0d3f58 AL	133	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
cd0d3f58 AL	134	gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
b3222f71	135	\| mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a	136
50593613	137	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	138	}
345e5c8a PK	139
94347cb3	140	static void mpc8xxx_irq_mask(struct irq_data *d)
345e5c8a	141	{
94347cb3	142	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	143	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	144	unsigned long flags;
345e5c8a PK	145
50593613	146	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	147
cd0d3f58 AL	148	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
cd0d3f58 AL	149	gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
b3222f71	150	& ~mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a	151
50593613	152	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	153	}
345e5c8a PK	154
94347cb3	155	static void mpc8xxx_irq_ack(struct irq_data *d)
345e5c8a	156	{
94347cb3	157	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	158	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a	159
cd0d3f58	160	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
b3222f71	161	mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a PK	162	}
345e5c8a PK	163
94347cb3	164	static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
345e5c8a	165	{
94347cb3	166	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	167	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	168	unsigned long flags;
	169
	170	switch (flow_type) {
	171	case IRQ_TYPE_EDGE_FALLING:
279c12df	172	case IRQ_TYPE_LEVEL_LOW:
50593613	173	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 AL	174	gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
cd0d3f58 AL	175	gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
b3222f71	176	\| mpc_pin2mask(irqd_to_hwirq(d)));
50593613	177	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	178	break;
	179
	180	case IRQ_TYPE_EDGE_BOTH:
50593613	181	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 AL	182	gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
cd0d3f58 AL	183	gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
b3222f71	184	& ~mpc_pin2mask(irqd_to_hwirq(d)));
50593613	185	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	186	break;
	187
	188	default:
	189	return -EINVAL;
	190	}
	191
	192	return 0;
	193	}
	194
94347cb3	195	static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
e39d5ef6	196	{
94347cb3	197	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
cd0d3f58	198	struct gpio_chip *gc = &mpc8xxx_gc->gc;
476eb491	199	unsigned long gpio = irqd_to_hwirq(d);
e39d5ef6 AG	200	void __iomem *reg;
	201	unsigned int shift;
	202	unsigned long flags;
	203
	204	if (gpio < 16) {
42178e2a	205	reg = mpc8xxx_gc->regs + GPIO_ICR;
e39d5ef6 AG	206	shift = (15 - gpio) * 2;
e39d5ef6 AG	207	} else {
42178e2a	208	reg = mpc8xxx_gc->regs + GPIO_ICR2;
e39d5ef6 AG	209	shift = (15 - (gpio % 16)) * 2;
	210	}
	211
	212	switch (flow_type) {
	213	case IRQ_TYPE_EDGE_FALLING:
	214	case IRQ_TYPE_LEVEL_LOW:
50593613	215	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	216	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a	217	\| (2 << shift));
50593613	218	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	219	break;
	220
	221	case IRQ_TYPE_EDGE_RISING:
	222	case IRQ_TYPE_LEVEL_HIGH:
50593613	223	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	224	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a	225	\| (1 << shift));
50593613	226	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	227	break;
	228
	229	case IRQ_TYPE_EDGE_BOTH:
50593613	230	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	231	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
50593613	232	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	233	break;
	234
	235	default:
	236	return -EINVAL;
	237	}
	238
	239	return 0;
	240	}
	241
345e5c8a PK	242	static struct irq_chip mpc8xxx_irq_chip = {
345e5c8a PK	243	.name = "mpc8xxx-gpio",
94347cb3 LB	244	.irq_unmask = mpc8xxx_irq_unmask,
	245	.irq_mask = mpc8xxx_irq_mask,
	246	.irq_ack = mpc8xxx_irq_ack,
82e39b0d	247	/* this might get overwritten in mpc8xxx_probe() */
94347cb3	248	.irq_set_type = mpc8xxx_irq_set_type,
345e5c8a PK	249	};
345e5c8a PK	250
5ba17ae9 LW	251	static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
5ba17ae9 LW	252	irq_hw_number_t hwirq)
345e5c8a	253	{
5ba17ae9	254	irq_set_chip_data(irq, h->host_data);
d71cf15b	255	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
345e5c8a PK	256
	257	return 0;
	258	}
	259
0b354dc4	260	static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
345e5c8a	261	.map = mpc8xxx_gpio_irq_map,
ff8c3ab8	262	.xlate = irq_domain_xlate_twocell,
345e5c8a PK	263	};
345e5c8a PK	264
82e39b0d UKK	265	struct mpc8xxx_gpio_devtype {
	266	int (gpio_dir_out)(struct gpio_chip , unsigned int, int);
	267	int (gpio_get)(struct gpio_chip , unsigned int);
	268	int (irq_set_type)(struct irq_data , unsigned int);
	269	};
	270
	271	static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	272	.gpio_dir_out = mpc5121_gpio_dir_out,
	273	.irq_set_type = mpc512x_irq_set_type,
	274	};
	275
0ba69e08 UKK	276	static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	277	.gpio_dir_out = mpc5125_gpio_dir_out,
	278	.irq_set_type = mpc512x_irq_set_type,
	279	};
	280
82e39b0d UKK	281	static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	282	.gpio_get = mpc8572_gpio_get,
	283	};
	284
	285	static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
82e39b0d UKK	286	.irq_set_type = mpc8xxx_irq_set_type,
	287	};
	288
4183afef	289	static const struct of_device_id mpc8xxx_gpio_ids[] = {
e39d5ef6	290	{ .compatible = "fsl,mpc8349-gpio", },
82e39b0d	291	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
e39d5ef6	292	{ .compatible = "fsl,mpc8610-gpio", },
82e39b0d	293	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
0ba69e08	294	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
15a5148c	295	{ .compatible = "fsl,pq3-gpio", },
3795d7cc MW	296	{ .compatible = "fsl,ls1028a-gpio", },
3795d7cc MW	297	{ .compatible = "fsl,ls1088a-gpio", },
d1dcfbbb	298	{ .compatible = "fsl,qoriq-gpio", },
e39d5ef6 AG	299	{}
	300	};
	301
98686d9a	302	static int mpc8xxx_probe(struct platform_device *pdev)
1e16dfc1	303	{
98686d9a	304	struct device_node *np = pdev->dev.of_node;
1e16dfc1	305	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
42178e2a	306	struct gpio_chip *gc;
76c47d14 RW	307	const struct mpc8xxx_gpio_devtype *devtype = NULL;
76c47d14 RW	308	struct fwnode_handle *fwnode;
1e16dfc1 PK	309	int ret;
1e16dfc1 PK	310
98686d9a RRD	311	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	312	if (!mpc8xxx_gc)
	313	return -ENOMEM;
1e16dfc1	314
257e1075 RRD	315	platform_set_drvdata(pdev, mpc8xxx_gc);
257e1075 RRD	316
50593613	317	raw_spin_lock_init(&mpc8xxx_gc->lock);
1e16dfc1	318
76c47d14 RW	319	mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
	320	if (IS_ERR(mpc8xxx_gc->regs))
	321	return PTR_ERR(mpc8xxx_gc->regs);
42178e2a LG	322
42178e2a LG	323	gc = &mpc8xxx_gc->gc;
322f6a31	324	gc->parent = &pdev->dev;
42178e2a	325
76c47d14	326	if (device_property_read_bool(&pdev->dev, "little-endian")) {
42178e2a LG	327	ret = bgpio_init(gc, &pdev->dev, 4,
	328	mpc8xxx_gc->regs + GPIO_DAT,
	329	NULL, NULL,
	330	mpc8xxx_gc->regs + GPIO_DIR, NULL,
	331	BGPIOF_BIG_ENDIAN);
	332	if (ret)
7d658893	333	return ret;
42178e2a LG	334	dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
	335	} else {
	336	ret = bgpio_init(gc, &pdev->dev, 4,
	337	mpc8xxx_gc->regs + GPIO_DAT,
	338	NULL, NULL,
	339	mpc8xxx_gc->regs + GPIO_DIR, NULL,
	340	BGPIOF_BIG_ENDIAN
	341	\| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	342	if (ret)
7d658893	343	return ret;
42178e2a LG	344	dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
42178e2a LG	345	}
1e16dfc1	346
fa4007ca	347	mpc8xxx_gc->direction_output = gc->direction_output;
82e39b0d	348
76c47d14	349	devtype = device_get_match_data(&pdev->dev);
82e39b0d UKK	350	if (!devtype)
	351	devtype = &mpc8xxx_gpio_devtype_default;
	352
	353	/*
	354	* It's assumed that only a single type of gpio controller is available
	355	* on the current machine, so overwriting global data is fine.
	356	*/
4e50573f VO	357	if (devtype->irq_set_type)
4e50573f VO	358	mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
82e39b0d	359
adf32eaa AL	360	if (devtype->gpio_dir_out)
	361	gc->direction_output = devtype->gpio_dir_out;
	362	if (devtype->gpio_get)
	363	gc->get = devtype->gpio_get;
	364
345e5c8a	365	gc->to_irq = mpc8xxx_gpio_to_irq;
1e16dfc1	366
3795d7cc MW	367	/*
	368	* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
	369	* the input enable of each individual GPIO port. When an individual
	370	* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
	371	* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
	372	* the port value to the GPIO Data Register.
	373	*/
76c47d14	374	fwnode = dev_fwnode(&pdev->dev);
3795d7cc MW	375	if (of_device_is_compatible(np, "fsl,qoriq-gpio") \|\|
3795d7cc MW	376	of_device_is_compatible(np, "fsl,ls1028a-gpio") \|\|
76c47d14 RW	377	of_device_is_compatible(np, "fsl,ls1088a-gpio") \|\|
76c47d14 RW	378	is_acpi_node(fwnode))
787b64a4 RK	379	gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
787b64a4 RK	380
889a1b3f	381	ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
42178e2a	382	if (ret) {
76c47d14 RW	383	dev_err(&pdev->dev,
76c47d14 RW	384	"GPIO chip registration failed with status %d\n", ret);
7d658893	385	return ret;
42178e2a	386	}
1e16dfc1	387
76c47d14	388	mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
0b39536c ML	389	if (mpc8xxx_gc->irqn < 0)
0b39536c ML	390	return mpc8xxx_gc->irqn;
345e5c8a	391
76c47d14 RW	392	mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
	393	MPC8XXX_GPIO_PINS,
	394	&mpc8xxx_gpio_irq_ops,
	395	mpc8xxx_gc);
	396
345e5c8a	397	if (!mpc8xxx_gc->irq)
98686d9a	398	return 0;
345e5c8a	399
345e5c8a	400	/* ack and mask all irqs */
cd0d3f58 AL	401	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
cd0d3f58 AL	402	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
345e5c8a	403
698b8eea SH	404	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
698b8eea SH	405	mpc8xxx_gpio_irq_cascade,
ec7099fd	406	IRQF_NO_THREAD \| IRQF_SHARED, "gpio-cascade",
698b8eea SH	407	mpc8xxx_gc);
698b8eea SH	408	if (ret) {
76c47d14 RW	409	dev_err(&pdev->dev,
	410	"failed to devm_request_irq(%d), ret = %d\n",
	411	mpc8xxx_gc->irqn, ret);
698b8eea SH	412	goto err;
	413	}
	414
257e1075	415	return 0;
42178e2a	416	err:
7d658893	417	irq_domain_remove(mpc8xxx_gc->irq);
42178e2a	418	return ret;
257e1075 RRD	419	}
	420
	421	static int mpc8xxx_remove(struct platform_device *pdev)
	422	{
	423	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
	424
	425	if (mpc8xxx_gc->irq) {
05379818	426	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
257e1075 RRD	427	irq_domain_remove(mpc8xxx_gc->irq);
	428	}
	429
98686d9a	430	return 0;
1e16dfc1 PK	431	}
1e16dfc1 PK	432
76c47d14 RW	433	#ifdef CONFIG_ACPI
	434	static const struct acpi_device_id gpio_acpi_ids[] = {
	435	{"NXP0031",},
	436	{ }
	437	};
	438	MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
	439	#endif
	440
98686d9a RRD	441	static struct platform_driver mpc8xxx_plat_driver = {
98686d9a RRD	442	.probe = mpc8xxx_probe,
257e1075	443	.remove = mpc8xxx_remove,
98686d9a RRD	444	.driver = {
	445	.name = "gpio-mpc8xxx",
	446	.of_match_table = mpc8xxx_gpio_ids,
76c47d14	447	.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
98686d9a RRD	448	},
98686d9a RRD	449	};
1e16dfc1	450
98686d9a RRD	451	static int __init mpc8xxx_init(void)
	452	{
	453	return platform_driver_register(&mpc8xxx_plat_driver);
1e16dfc1	454	}
98686d9a RRD	455
98686d9a RRD	456	arch_initcall(mpc8xxx_init);