Commit | Line | Data |
---|---|---|
aeec56e3 | 1 | /* |
c103de24 | 2 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
3 | * |
4 | * Copyright 2008 MontaVista Software, Inc. | |
5 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... | |
13 | * ...`` ```````.. | |
14 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
15 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
16 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
17 | * ````````` | |
18 | ___ | |
19 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
20 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
21 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
22 | `....trivial..'~`.```.``` | |
23 | * ``````` | |
24 | * .```````~~~~`..`.``.``. | |
25 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
26 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
27 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
28 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
29 | * ``.`.``...``` ```.. output pins are also supported.` | |
30 | * ^^ `````.`````````.,``~``~``~~`````` | |
31 | * . ^^ | |
32 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
33 | * .. The expectation is that in at least some cases . ,-~~~-, | |
34 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
35 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
36 | * ..````````......``````````` \o_ | |
37 | * | | |
38 | * ^^ / \ | |
39 | * | |
40 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
41 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
42 | * . the number of GPIOs is determined by the width of ~ | |
43 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
44 | * `.......````.``` | |
45 | */ | |
46 | ||
47 | #include <linux/init.h> | |
280df6b3 | 48 | #include <linux/err.h> |
aeec56e3 AV |
49 | #include <linux/bug.h> |
50 | #include <linux/kernel.h> | |
51 | #include <linux/module.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/compiler.h> | |
54 | #include <linux/types.h> | |
55 | #include <linux/errno.h> | |
56 | #include <linux/log2.h> | |
57 | #include <linux/ioport.h> | |
58 | #include <linux/io.h> | |
0f4630f3 | 59 | #include <linux/gpio/driver.h> |
aeec56e3 | 60 | #include <linux/slab.h> |
4b63739e | 61 | #include <linux/bitops.h> |
aeec56e3 AV |
62 | #include <linux/platform_device.h> |
63 | #include <linux/mod_devicetable.h> | |
e698613a ÁFR |
64 | #include <linux/of.h> |
65 | #include <linux/of_device.h> | |
aeec56e3 | 66 | |
8467afec | 67 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 68 | { |
fd996235 | 69 | writeb(data, reg); |
aeec56e3 AV |
70 | } |
71 | ||
8467afec | 72 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 73 | { |
fd996235 | 74 | return readb(reg); |
8467afec JI |
75 | } |
76 | ||
77 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
78 | { | |
fd996235 | 79 | writew(data, reg); |
8467afec JI |
80 | } |
81 | ||
82 | static unsigned long bgpio_read16(void __iomem *reg) | |
83 | { | |
fd996235 | 84 | return readw(reg); |
8467afec JI |
85 | } |
86 | ||
87 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
88 | { | |
fd996235 | 89 | writel(data, reg); |
8467afec JI |
90 | } |
91 | ||
92 | static unsigned long bgpio_read32(void __iomem *reg) | |
93 | { | |
fd996235 | 94 | return readl(reg); |
8467afec JI |
95 | } |
96 | ||
aeec56e3 | 97 | #if BITS_PER_LONG >= 64 |
8467afec JI |
98 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
99 | { | |
fd996235 | 100 | writeq(data, reg); |
8467afec JI |
101 | } |
102 | ||
103 | static unsigned long bgpio_read64(void __iomem *reg) | |
104 | { | |
fd996235 | 105 | return readq(reg); |
aeec56e3 | 106 | } |
8467afec | 107 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 | 108 | |
2b78f1e1 AL |
109 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
110 | { | |
111 | iowrite16be(data, reg); | |
112 | } | |
113 | ||
114 | static unsigned long bgpio_read16be(void __iomem *reg) | |
115 | { | |
116 | return ioread16be(reg); | |
117 | } | |
118 | ||
119 | static void bgpio_write32be(void __iomem *reg, unsigned long data) | |
120 | { | |
121 | iowrite32be(data, reg); | |
122 | } | |
123 | ||
124 | static unsigned long bgpio_read32be(void __iomem *reg) | |
125 | { | |
126 | return ioread32be(reg); | |
127 | } | |
128 | ||
0f4630f3 | 129 | static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin) |
aeec56e3 | 130 | { |
4b63739e | 131 | return BIT(pin); |
8467afec JI |
132 | } |
133 | ||
0f4630f3 | 134 | static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc, |
8467afec JI |
135 | unsigned int pin) |
136 | { | |
0f4630f3 | 137 | return BIT(gc->bgpio_bits - 1 - pin); |
aeec56e3 AV |
138 | } |
139 | ||
b19e7f51 VZ |
140 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
141 | { | |
0f4630f3 | 142 | unsigned long pinmask = gc->pin2mask(gc, gpio); |
b19e7f51 | 143 | |
0f4630f3 LW |
144 | if (gc->bgpio_dir & pinmask) |
145 | return !!(gc->read_reg(gc->reg_set) & pinmask); | |
b19e7f51 | 146 | else |
0f4630f3 | 147 | return !!(gc->read_reg(gc->reg_dat) & pinmask); |
b19e7f51 VZ |
148 | } |
149 | ||
aeec56e3 AV |
150 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
151 | { | |
0f4630f3 | 152 | return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio)); |
aeec56e3 AV |
153 | } |
154 | ||
91492a44 RV |
155 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
156 | { | |
157 | } | |
158 | ||
aeec56e3 AV |
159 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
160 | { | |
0f4630f3 | 161 | unsigned long mask = gc->pin2mask(gc, gpio); |
aeec56e3 AV |
162 | unsigned long flags; |
163 | ||
0f4630f3 | 164 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
aeec56e3 AV |
165 | |
166 | if (val) | |
0f4630f3 | 167 | gc->bgpio_data |= mask; |
aeec56e3 | 168 | else |
0f4630f3 | 169 | gc->bgpio_data &= ~mask; |
aeec56e3 | 170 | |
0f4630f3 | 171 | gc->write_reg(gc->reg_dat, gc->bgpio_data); |
aeec56e3 | 172 | |
0f4630f3 | 173 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
aeec56e3 AV |
174 | } |
175 | ||
e027d6f9 JI |
176 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
177 | int val) | |
178 | { | |
0f4630f3 | 179 | unsigned long mask = gc->pin2mask(gc, gpio); |
e027d6f9 JI |
180 | |
181 | if (val) | |
0f4630f3 | 182 | gc->write_reg(gc->reg_set, mask); |
e027d6f9 | 183 | else |
0f4630f3 | 184 | gc->write_reg(gc->reg_clr, mask); |
e027d6f9 JI |
185 | } |
186 | ||
dd86a0cc JI |
187 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
188 | { | |
0f4630f3 | 189 | unsigned long mask = gc->pin2mask(gc, gpio); |
dd86a0cc JI |
190 | unsigned long flags; |
191 | ||
0f4630f3 | 192 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
dd86a0cc JI |
193 | |
194 | if (val) | |
0f4630f3 | 195 | gc->bgpio_data |= mask; |
dd86a0cc | 196 | else |
0f4630f3 | 197 | gc->bgpio_data &= ~mask; |
dd86a0cc | 198 | |
0f4630f3 | 199 | gc->write_reg(gc->reg_set, gc->bgpio_data); |
dd86a0cc | 200 | |
0f4630f3 | 201 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
dd86a0cc JI |
202 | } |
203 | ||
0f4630f3 | 204 | static void bgpio_multiple_get_masks(struct gpio_chip *gc, |
73c4ceda RI |
205 | unsigned long *mask, unsigned long *bits, |
206 | unsigned long *set_mask, | |
207 | unsigned long *clear_mask) | |
208 | { | |
209 | int i; | |
210 | ||
211 | *set_mask = 0; | |
212 | *clear_mask = 0; | |
213 | ||
0f4630f3 | 214 | for (i = 0; i < gc->bgpio_bits; i++) { |
73c4ceda RI |
215 | if (*mask == 0) |
216 | break; | |
217 | if (__test_and_clear_bit(i, mask)) { | |
218 | if (test_bit(i, bits)) | |
0f4630f3 | 219 | *set_mask |= gc->pin2mask(gc, i); |
73c4ceda | 220 | else |
0f4630f3 | 221 | *clear_mask |= gc->pin2mask(gc, i); |
73c4ceda RI |
222 | } |
223 | } | |
224 | } | |
225 | ||
0f4630f3 | 226 | static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, |
73c4ceda RI |
227 | unsigned long *mask, |
228 | unsigned long *bits, | |
229 | void __iomem *reg) | |
230 | { | |
231 | unsigned long flags; | |
232 | unsigned long set_mask, clear_mask; | |
233 | ||
0f4630f3 | 234 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
73c4ceda | 235 | |
0f4630f3 | 236 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda | 237 | |
0f4630f3 LW |
238 | gc->bgpio_data |= set_mask; |
239 | gc->bgpio_data &= ~clear_mask; | |
73c4ceda | 240 | |
0f4630f3 | 241 | gc->write_reg(reg, gc->bgpio_data); |
73c4ceda | 242 | |
0f4630f3 | 243 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
73c4ceda RI |
244 | } |
245 | ||
246 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
247 | unsigned long *bits) | |
248 | { | |
0f4630f3 | 249 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); |
73c4ceda RI |
250 | } |
251 | ||
252 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, | |
253 | unsigned long *bits) | |
254 | { | |
0f4630f3 | 255 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); |
73c4ceda RI |
256 | } |
257 | ||
258 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, | |
259 | unsigned long *mask, | |
260 | unsigned long *bits) | |
261 | { | |
73c4ceda RI |
262 | unsigned long set_mask, clear_mask; |
263 | ||
0f4630f3 | 264 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda RI |
265 | |
266 | if (set_mask) | |
0f4630f3 | 267 | gc->write_reg(gc->reg_set, set_mask); |
73c4ceda | 268 | if (clear_mask) |
0f4630f3 | 269 | gc->write_reg(gc->reg_clr, clear_mask); |
73c4ceda RI |
270 | } |
271 | ||
31029116 JI |
272 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
273 | { | |
274 | return 0; | |
275 | } | |
276 | ||
91492a44 RV |
277 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
278 | int val) | |
279 | { | |
280 | return -EINVAL; | |
281 | } | |
282 | ||
31029116 JI |
283 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
284 | int val) | |
285 | { | |
286 | gc->set(gc, gpio, val); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
aeec56e3 AV |
291 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
292 | { | |
31029116 JI |
293 | unsigned long flags; |
294 | ||
0f4630f3 | 295 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 296 | |
0f4630f3 LW |
297 | gc->bgpio_dir &= ~gc->pin2mask(gc, gpio); |
298 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 299 | |
0f4630f3 | 300 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 301 | |
aeec56e3 AV |
302 | return 0; |
303 | } | |
304 | ||
db3b0fcc PZ |
305 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
306 | { | |
0f4630f3 LW |
307 | /* Return 0 if output, 1 of input */ |
308 | return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio)); | |
db3b0fcc PZ |
309 | } |
310 | ||
aeec56e3 AV |
311 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
312 | { | |
31029116 JI |
313 | unsigned long flags; |
314 | ||
315 | gc->set(gc, gpio, val); | |
316 | ||
0f4630f3 | 317 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 318 | |
0f4630f3 LW |
319 | gc->bgpio_dir |= gc->pin2mask(gc, gpio); |
320 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 321 | |
0f4630f3 | 322 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 JI |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
327 | static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) | |
328 | { | |
31029116 JI |
329 | unsigned long flags; |
330 | ||
0f4630f3 | 331 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 332 | |
0f4630f3 LW |
333 | gc->bgpio_dir |= gc->pin2mask(gc, gpio); |
334 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 335 | |
0f4630f3 | 336 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 JI |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
341 | static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) | |
342 | { | |
31029116 JI |
343 | unsigned long flags; |
344 | ||
e027d6f9 JI |
345 | gc->set(gc, gpio, val); |
346 | ||
0f4630f3 | 347 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 348 | |
0f4630f3 LW |
349 | gc->bgpio_dir &= ~gc->pin2mask(gc, gpio); |
350 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 351 | |
0f4630f3 | 352 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 353 | |
aeec56e3 AV |
354 | return 0; |
355 | } | |
356 | ||
db3b0fcc PZ |
357 | static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio) |
358 | { | |
0f4630f3 LW |
359 | /* Return 0 if output, 1 if input */ |
360 | return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio)); | |
db3b0fcc PZ |
361 | } |
362 | ||
280df6b3 | 363 | static int bgpio_setup_accessors(struct device *dev, |
0f4630f3 | 364 | struct gpio_chip *gc, |
2b78f1e1 AL |
365 | bool bit_be, |
366 | bool byte_be) | |
aeec56e3 | 367 | { |
8467afec | 368 | |
0f4630f3 | 369 | switch (gc->bgpio_bits) { |
8467afec | 370 | case 8: |
0f4630f3 LW |
371 | gc->read_reg = bgpio_read8; |
372 | gc->write_reg = bgpio_write8; | |
8467afec JI |
373 | break; |
374 | case 16: | |
2b78f1e1 | 375 | if (byte_be) { |
0f4630f3 LW |
376 | gc->read_reg = bgpio_read16be; |
377 | gc->write_reg = bgpio_write16be; | |
2b78f1e1 | 378 | } else { |
0f4630f3 LW |
379 | gc->read_reg = bgpio_read16; |
380 | gc->write_reg = bgpio_write16; | |
2b78f1e1 | 381 | } |
8467afec JI |
382 | break; |
383 | case 32: | |
2b78f1e1 | 384 | if (byte_be) { |
0f4630f3 LW |
385 | gc->read_reg = bgpio_read32be; |
386 | gc->write_reg = bgpio_write32be; | |
2b78f1e1 | 387 | } else { |
0f4630f3 LW |
388 | gc->read_reg = bgpio_read32; |
389 | gc->write_reg = bgpio_write32; | |
2b78f1e1 | 390 | } |
8467afec JI |
391 | break; |
392 | #if BITS_PER_LONG >= 64 | |
393 | case 64: | |
2b78f1e1 AL |
394 | if (byte_be) { |
395 | dev_err(dev, | |
396 | "64 bit big endian byte order unsupported\n"); | |
397 | return -EINVAL; | |
398 | } else { | |
0f4630f3 LW |
399 | gc->read_reg = bgpio_read64; |
400 | gc->write_reg = bgpio_write64; | |
2b78f1e1 | 401 | } |
8467afec JI |
402 | break; |
403 | #endif /* BITS_PER_LONG >= 64 */ | |
404 | default: | |
0f4630f3 | 405 | dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); |
8467afec JI |
406 | return -EINVAL; |
407 | } | |
408 | ||
0f4630f3 | 409 | gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask; |
8467afec JI |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
e027d6f9 JI |
414 | /* |
415 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 416 | * three supported configurations: |
e027d6f9 | 417 | * |
dd86a0cc | 418 | * - single input/output register resource (named "dat"). |
e027d6f9 | 419 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
420 | * - single output register resource and single input resource ("set" and |
421 | * dat"). | |
e027d6f9 JI |
422 | * |
423 | * For the single output register, this drives a 1 by setting a bit and a zero | |
424 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
425 | * in the set register and clears it by setting a bit in the clear register. | |
426 | * The configuration is detected by which resources are present. | |
31029116 JI |
427 | * |
428 | * For setting the GPIO direction, there are three supported configurations: | |
429 | * | |
430 | * - simple bidirection GPIO that requires no configuration. | |
431 | * - an output direction register (named "dirout") where a 1 bit | |
432 | * indicates the GPIO is an output. | |
433 | * - an input direction register (named "dirin") where a 1 bit indicates | |
434 | * the GPIO is an input. | |
e027d6f9 | 435 | */ |
0f4630f3 | 436 | static int bgpio_setup_io(struct gpio_chip *gc, |
280df6b3 JI |
437 | void __iomem *dat, |
438 | void __iomem *set, | |
b19e7f51 VZ |
439 | void __iomem *clr, |
440 | unsigned long flags) | |
8467afec | 441 | { |
aeec56e3 | 442 | |
0f4630f3 LW |
443 | gc->reg_dat = dat; |
444 | if (!gc->reg_dat) | |
280df6b3 | 445 | return -EINVAL; |
e027d6f9 | 446 | |
280df6b3 | 447 | if (set && clr) { |
0f4630f3 LW |
448 | gc->reg_set = set; |
449 | gc->reg_clr = clr; | |
450 | gc->set = bgpio_set_with_clear; | |
451 | gc->set_multiple = bgpio_set_multiple_with_clear; | |
280df6b3 | 452 | } else if (set && !clr) { |
0f4630f3 LW |
453 | gc->reg_set = set; |
454 | gc->set = bgpio_set_set; | |
455 | gc->set_multiple = bgpio_set_multiple_set; | |
91492a44 | 456 | } else if (flags & BGPIOF_NO_OUTPUT) { |
0f4630f3 LW |
457 | gc->set = bgpio_set_none; |
458 | gc->set_multiple = NULL; | |
e027d6f9 | 459 | } else { |
0f4630f3 LW |
460 | gc->set = bgpio_set; |
461 | gc->set_multiple = bgpio_set_multiple; | |
aeec56e3 AV |
462 | } |
463 | ||
b19e7f51 VZ |
464 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
465 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) | |
0f4630f3 | 466 | gc->get = bgpio_get_set; |
b19e7f51 | 467 | else |
0f4630f3 | 468 | gc->get = bgpio_get; |
dd86a0cc | 469 | |
e027d6f9 JI |
470 | return 0; |
471 | } | |
472 | ||
0f4630f3 | 473 | static int bgpio_setup_direction(struct gpio_chip *gc, |
280df6b3 | 474 | void __iomem *dirout, |
91492a44 RV |
475 | void __iomem *dirin, |
476 | unsigned long flags) | |
31029116 | 477 | { |
280df6b3 | 478 | if (dirout && dirin) { |
31029116 | 479 | return -EINVAL; |
280df6b3 | 480 | } else if (dirout) { |
0f4630f3 LW |
481 | gc->reg_dir = dirout; |
482 | gc->direction_output = bgpio_dir_out; | |
483 | gc->direction_input = bgpio_dir_in; | |
484 | gc->get_direction = bgpio_get_dir; | |
280df6b3 | 485 | } else if (dirin) { |
0f4630f3 LW |
486 | gc->reg_dir = dirin; |
487 | gc->direction_output = bgpio_dir_out_inv; | |
488 | gc->direction_input = bgpio_dir_in_inv; | |
489 | gc->get_direction = bgpio_get_dir_inv; | |
31029116 | 490 | } else { |
91492a44 | 491 | if (flags & BGPIOF_NO_OUTPUT) |
0f4630f3 | 492 | gc->direction_output = bgpio_dir_out_err; |
91492a44 | 493 | else |
0f4630f3 LW |
494 | gc->direction_output = bgpio_simple_dir_out; |
495 | gc->direction_input = bgpio_simple_dir_in; | |
31029116 JI |
496 | } |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
7b42e3db AF |
501 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
502 | { | |
503 | if (gpio_pin < chip->ngpio) | |
504 | return 0; | |
505 | ||
506 | return -EINVAL; | |
507 | } | |
508 | ||
0f4630f3 | 509 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
4f5b0480 RK |
510 | unsigned long sz, void __iomem *dat, void __iomem *set, |
511 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 512 | unsigned long flags) |
e027d6f9 | 513 | { |
e027d6f9 | 514 | int ret; |
e027d6f9 | 515 | |
280df6b3 JI |
516 | if (!is_power_of_2(sz)) |
517 | return -EINVAL; | |
e027d6f9 | 518 | |
0f4630f3 LW |
519 | gc->bgpio_bits = sz * 8; |
520 | if (gc->bgpio_bits > BITS_PER_LONG) | |
280df6b3 JI |
521 | return -EINVAL; |
522 | ||
0f4630f3 LW |
523 | spin_lock_init(&gc->bgpio_lock); |
524 | gc->parent = dev; | |
525 | gc->label = dev_name(dev); | |
526 | gc->base = -1; | |
527 | gc->ngpio = gc->bgpio_bits; | |
528 | gc->request = bgpio_request; | |
280df6b3 | 529 | |
0f4630f3 | 530 | ret = bgpio_setup_io(gc, dat, set, clr, flags); |
e027d6f9 JI |
531 | if (ret) |
532 | return ret; | |
aeec56e3 | 533 | |
0f4630f3 | 534 | ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN, |
2b78f1e1 | 535 | flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
8467afec JI |
536 | if (ret) |
537 | return ret; | |
aeec56e3 | 538 | |
0f4630f3 | 539 | ret = bgpio_setup_direction(gc, dirout, dirin, flags); |
31029116 JI |
540 | if (ret) |
541 | return ret; | |
542 | ||
0f4630f3 LW |
543 | gc->bgpio_data = gc->read_reg(gc->reg_dat); |
544 | if (gc->set == bgpio_set_set && | |
3e11f7b8 | 545 | !(flags & BGPIOF_UNREADABLE_REG_SET)) |
0f4630f3 LW |
546 | gc->bgpio_data = gc->read_reg(gc->reg_set); |
547 | if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) | |
548 | gc->bgpio_dir = gc->read_reg(gc->reg_dir); | |
924e7a9f | 549 | |
280df6b3 JI |
550 | return ret; |
551 | } | |
552 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 553 | |
8f01c9d0 | 554 | #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) |
aeec56e3 | 555 | |
280df6b3 JI |
556 | static void __iomem *bgpio_map(struct platform_device *pdev, |
557 | const char *name, | |
8d240260 | 558 | resource_size_t sane_sz) |
280df6b3 | 559 | { |
280df6b3 | 560 | struct resource *r; |
280df6b3 | 561 | resource_size_t sz; |
280df6b3 JI |
562 | |
563 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
8d240260 | 564 | if (!r) |
b2f68b63 | 565 | return NULL; |
280df6b3 JI |
566 | |
567 | sz = resource_size(r); | |
8d240260 HK |
568 | if (sz != sane_sz) |
569 | return IOMEM_ERR_PTR(-EINVAL); | |
280df6b3 | 570 | |
8d240260 | 571 | return devm_ioremap_resource(&pdev->dev, r); |
aeec56e3 AV |
572 | } |
573 | ||
e698613a ÁFR |
574 | #ifdef CONFIG_OF |
575 | static const struct of_device_id bgpio_of_match[] = { | |
05cc995f | 576 | { .compatible = "brcm,bcm6345-gpio" }, |
c0d30ecf | 577 | { .compatible = "wd,mbl-gpio" }, |
b8c90199 | 578 | { .compatible = "ni,169445-nand-gpio" }, |
e698613a ÁFR |
579 | { } |
580 | }; | |
581 | MODULE_DEVICE_TABLE(of, bgpio_of_match); | |
582 | ||
583 | static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, | |
584 | unsigned long *flags) | |
585 | { | |
586 | struct bgpio_pdata *pdata; | |
587 | ||
588 | if (!of_match_device(bgpio_of_match, &pdev->dev)) | |
589 | return NULL; | |
590 | ||
591 | pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata), | |
592 | GFP_KERNEL); | |
593 | if (!pdata) | |
594 | return ERR_PTR(-ENOMEM); | |
595 | ||
596 | pdata->base = -1; | |
597 | ||
05cc995f CL |
598 | if (of_device_is_big_endian(pdev->dev.of_node)) |
599 | *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; | |
600 | ||
c0d30ecf CL |
601 | if (of_property_read_bool(pdev->dev.of_node, "no-output")) |
602 | *flags |= BGPIOF_NO_OUTPUT; | |
603 | ||
e698613a ÁFR |
604 | return pdata; |
605 | } | |
606 | #else | |
607 | static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, | |
608 | unsigned long *flags) | |
609 | { | |
610 | return NULL; | |
611 | } | |
612 | #endif /* CONFIG_OF */ | |
613 | ||
3836309d | 614 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
615 | { |
616 | struct device *dev = &pdev->dev; | |
617 | struct resource *r; | |
618 | void __iomem *dat; | |
619 | void __iomem *set; | |
620 | void __iomem *clr; | |
621 | void __iomem *dirout; | |
622 | void __iomem *dirin; | |
623 | unsigned long sz; | |
e698613a | 624 | unsigned long flags = 0; |
280df6b3 | 625 | int err; |
0f4630f3 | 626 | struct gpio_chip *gc; |
e698613a ÁFR |
627 | struct bgpio_pdata *pdata; |
628 | ||
629 | pdata = bgpio_parse_dt(pdev, &flags); | |
630 | if (IS_ERR(pdata)) | |
631 | return PTR_ERR(pdata); | |
632 | ||
633 | if (!pdata) { | |
634 | pdata = dev_get_platdata(dev); | |
635 | flags = pdev->id_entry->driver_data; | |
636 | } | |
280df6b3 JI |
637 | |
638 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
639 | if (!r) | |
640 | return -EINVAL; | |
641 | ||
642 | sz = resource_size(r); | |
643 | ||
8d240260 HK |
644 | dat = bgpio_map(pdev, "dat", sz); |
645 | if (IS_ERR(dat)) | |
646 | return PTR_ERR(dat); | |
280df6b3 | 647 | |
8d240260 HK |
648 | set = bgpio_map(pdev, "set", sz); |
649 | if (IS_ERR(set)) | |
650 | return PTR_ERR(set); | |
280df6b3 | 651 | |
8d240260 HK |
652 | clr = bgpio_map(pdev, "clr", sz); |
653 | if (IS_ERR(clr)) | |
654 | return PTR_ERR(clr); | |
280df6b3 | 655 | |
8d240260 HK |
656 | dirout = bgpio_map(pdev, "dirout", sz); |
657 | if (IS_ERR(dirout)) | |
658 | return PTR_ERR(dirout); | |
280df6b3 | 659 | |
8d240260 HK |
660 | dirin = bgpio_map(pdev, "dirin", sz); |
661 | if (IS_ERR(dirin)) | |
662 | return PTR_ERR(dirin); | |
280df6b3 | 663 | |
0f4630f3 LW |
664 | gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); |
665 | if (!gc) | |
280df6b3 JI |
666 | return -ENOMEM; |
667 | ||
0f4630f3 | 668 | err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
669 | if (err) |
670 | return err; | |
671 | ||
672 | if (pdata) { | |
781f6d71 | 673 | if (pdata->label) |
0f4630f3 LW |
674 | gc->label = pdata->label; |
675 | gc->base = pdata->base; | |
280df6b3 | 676 | if (pdata->ngpio > 0) |
0f4630f3 | 677 | gc->ngpio = pdata->ngpio; |
280df6b3 JI |
678 | } |
679 | ||
0f4630f3 | 680 | platform_set_drvdata(pdev, gc); |
280df6b3 | 681 | |
c05f813b | 682 | return devm_gpiochip_add_data(&pdev->dev, gc, NULL); |
aeec56e3 AV |
683 | } |
684 | ||
685 | static const struct platform_device_id bgpio_id_table[] = { | |
19338530 AS |
686 | { |
687 | .name = "basic-mmio-gpio", | |
688 | .driver_data = 0, | |
689 | }, { | |
690 | .name = "basic-mmio-gpio-be", | |
691 | .driver_data = BGPIOF_BIG_ENDIAN, | |
692 | }, | |
693 | { } | |
aeec56e3 AV |
694 | }; |
695 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
696 | ||
697 | static struct platform_driver bgpio_driver = { | |
698 | .driver = { | |
699 | .name = "basic-mmio-gpio", | |
e698613a | 700 | .of_match_table = of_match_ptr(bgpio_of_match), |
aeec56e3 AV |
701 | }, |
702 | .id_table = bgpio_id_table, | |
280df6b3 | 703 | .probe = bgpio_pdev_probe, |
aeec56e3 AV |
704 | }; |
705 | ||
6f61415e | 706 | module_platform_driver(bgpio_driver); |
280df6b3 | 707 | |
c103de24 | 708 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
709 | |
710 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
711 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
712 | MODULE_LICENSE("GPL"); |