Commit | Line | Data |
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dae5f0af | 1 | // SPDX-License-Identifier: GPL-2.0+ |
aeec56e3 | 2 | /* |
c103de24 | 3 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
4 | * |
5 | * Copyright 2008 MontaVista Software, Inc. | |
6 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
7 | * | |
aeec56e3 AV |
8 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... |
9 | * ...`` ```````.. | |
10 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
11 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
12 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
13 | * ````````` | |
14 | ___ | |
15 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
16 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
17 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
18 | `....trivial..'~`.```.``` | |
19 | * ``````` | |
20 | * .```````~~~~`..`.``.``. | |
21 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
22 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
23 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
24 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
25 | * ``.`.``...``` ```.. output pins are also supported.` | |
26 | * ^^ `````.`````````.,``~``~``~~`````` | |
27 | * . ^^ | |
28 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
29 | * .. The expectation is that in at least some cases . ,-~~~-, | |
30 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
31 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
32 | * ..````````......``````````` \o_ | |
33 | * | | |
34 | * ^^ / \ | |
35 | * | |
36 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
37 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
38 | * . the number of GPIOs is determined by the width of ~ | |
39 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
40 | * `.......````.``` | |
41 | */ | |
42 | ||
c9bd27c8 AS |
43 | #include <linux/bitops.h> |
44 | #include <linux/compiler.h> | |
280df6b3 | 45 | #include <linux/err.h> |
c9bd27c8 AS |
46 | #include <linux/init.h> |
47 | #include <linux/io.h> | |
48 | #include <linux/ioport.h> | |
49 | #include <linux/log2.h> | |
50 | #include <linux/mod_devicetable.h> | |
aeec56e3 | 51 | #include <linux/module.h> |
c9bd27c8 AS |
52 | #include <linux/platform_device.h> |
53 | #include <linux/property.h> | |
54 | #include <linux/slab.h> | |
aeec56e3 | 55 | #include <linux/spinlock.h> |
aeec56e3 | 56 | #include <linux/types.h> |
c9bd27c8 | 57 | |
0f4630f3 | 58 | #include <linux/gpio/driver.h> |
aeec56e3 | 59 | |
55b2395e AM |
60 | #include "gpiolib.h" |
61 | ||
8467afec | 62 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 63 | { |
fd996235 | 64 | writeb(data, reg); |
aeec56e3 AV |
65 | } |
66 | ||
8467afec | 67 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 68 | { |
fd996235 | 69 | return readb(reg); |
8467afec JI |
70 | } |
71 | ||
72 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
73 | { | |
fd996235 | 74 | writew(data, reg); |
8467afec JI |
75 | } |
76 | ||
77 | static unsigned long bgpio_read16(void __iomem *reg) | |
78 | { | |
fd996235 | 79 | return readw(reg); |
8467afec JI |
80 | } |
81 | ||
82 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
83 | { | |
fd996235 | 84 | writel(data, reg); |
8467afec JI |
85 | } |
86 | ||
87 | static unsigned long bgpio_read32(void __iomem *reg) | |
88 | { | |
fd996235 | 89 | return readl(reg); |
8467afec JI |
90 | } |
91 | ||
aeec56e3 | 92 | #if BITS_PER_LONG >= 64 |
8467afec JI |
93 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
94 | { | |
fd996235 | 95 | writeq(data, reg); |
8467afec JI |
96 | } |
97 | ||
98 | static unsigned long bgpio_read64(void __iomem *reg) | |
99 | { | |
fd996235 | 100 | return readq(reg); |
aeec56e3 | 101 | } |
8467afec | 102 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 | 103 | |
2b78f1e1 AL |
104 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
105 | { | |
106 | iowrite16be(data, reg); | |
107 | } | |
108 | ||
109 | static unsigned long bgpio_read16be(void __iomem *reg) | |
110 | { | |
111 | return ioread16be(reg); | |
112 | } | |
113 | ||
114 | static void bgpio_write32be(void __iomem *reg, unsigned long data) | |
115 | { | |
116 | iowrite32be(data, reg); | |
117 | } | |
118 | ||
119 | static unsigned long bgpio_read32be(void __iomem *reg) | |
120 | { | |
121 | return ioread32be(reg); | |
122 | } | |
123 | ||
24efd94b | 124 | static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) |
aeec56e3 | 125 | { |
24efd94b LW |
126 | if (gc->be_bits) |
127 | return BIT(gc->bgpio_bits - 1 - line); | |
128 | return BIT(line); | |
aeec56e3 AV |
129 | } |
130 | ||
b19e7f51 VZ |
131 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
132 | { | |
24efd94b | 133 | unsigned long pinmask = bgpio_line2mask(gc, gpio); |
d799a4de | 134 | bool dir = !!(gc->bgpio_dir & pinmask); |
b19e7f51 | 135 | |
d799a4de | 136 | if (dir) |
0f4630f3 | 137 | return !!(gc->read_reg(gc->reg_set) & pinmask); |
b19e7f51 | 138 | else |
0f4630f3 | 139 | return !!(gc->read_reg(gc->reg_dat) & pinmask); |
b19e7f51 VZ |
140 | } |
141 | ||
80057cb4 LW |
142 | /* |
143 | * This assumes that the bits in the GPIO register are in native endianness. | |
144 | * We only assign the function pointer if we have that. | |
145 | */ | |
146 | static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
147 | unsigned long *bits) | |
148 | { | |
149 | unsigned long get_mask = 0; | |
150 | unsigned long set_mask = 0; | |
80057cb4 | 151 | |
07c7b6a5 LW |
152 | /* Make sure we first clear any bits that are zero when we read the register */ |
153 | *bits &= ~*mask; | |
154 | ||
4f2f95e9 JK |
155 | set_mask = *mask & gc->bgpio_dir; |
156 | get_mask = *mask & ~gc->bgpio_dir; | |
80057cb4 LW |
157 | |
158 | if (set_mask) | |
159 | *bits |= gc->read_reg(gc->reg_set) & set_mask; | |
160 | if (get_mask) | |
161 | *bits |= gc->read_reg(gc->reg_dat) & get_mask; | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
aeec56e3 AV |
166 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
167 | { | |
24efd94b | 168 | return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); |
aeec56e3 AV |
169 | } |
170 | ||
80057cb4 LW |
171 | /* |
172 | * This only works if the bits in the GPIO register are in native endianness. | |
80057cb4 LW |
173 | */ |
174 | static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, | |
175 | unsigned long *bits) | |
176 | { | |
07c7b6a5 LW |
177 | /* Make sure we first clear any bits that are zero when we read the register */ |
178 | *bits &= ~*mask; | |
179 | *bits |= gc->read_reg(gc->reg_dat) & *mask; | |
80057cb4 LW |
180 | return 0; |
181 | } | |
182 | ||
183 | /* | |
184 | * With big endian mirrored bit order it becomes more tedious. | |
185 | */ | |
186 | static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, | |
187 | unsigned long *bits) | |
188 | { | |
189 | unsigned long readmask = 0; | |
190 | unsigned long val; | |
191 | int bit; | |
192 | ||
07c7b6a5 LW |
193 | /* Make sure we first clear any bits that are zero when we read the register */ |
194 | *bits &= ~*mask; | |
195 | ||
80057cb4 | 196 | /* Create a mirrored mask */ |
761b5c30 | 197 | for_each_set_bit(bit, mask, gc->ngpio) |
80057cb4 LW |
198 | readmask |= bgpio_line2mask(gc, bit); |
199 | ||
200 | /* Read the register */ | |
201 | val = gc->read_reg(gc->reg_dat) & readmask; | |
202 | ||
203 | /* | |
204 | * Mirror the result into the "bits" result, this will give line 0 | |
205 | * in bit 0 ... line 31 in bit 31 for a 32bit register. | |
206 | */ | |
761b5c30 | 207 | for_each_set_bit(bit, &val, gc->ngpio) |
80057cb4 LW |
208 | *bits |= bgpio_line2mask(gc, bit); |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
91492a44 RV |
213 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
214 | { | |
215 | } | |
216 | ||
aeec56e3 AV |
217 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
218 | { | |
24efd94b | 219 | unsigned long mask = bgpio_line2mask(gc, gpio); |
aeec56e3 AV |
220 | unsigned long flags; |
221 | ||
3c938cc5 | 222 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
aeec56e3 AV |
223 | |
224 | if (val) | |
0f4630f3 | 225 | gc->bgpio_data |= mask; |
aeec56e3 | 226 | else |
0f4630f3 | 227 | gc->bgpio_data &= ~mask; |
aeec56e3 | 228 | |
0f4630f3 | 229 | gc->write_reg(gc->reg_dat, gc->bgpio_data); |
aeec56e3 | 230 | |
3c938cc5 | 231 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
aeec56e3 AV |
232 | } |
233 | ||
e027d6f9 JI |
234 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
235 | int val) | |
236 | { | |
24efd94b | 237 | unsigned long mask = bgpio_line2mask(gc, gpio); |
e027d6f9 JI |
238 | |
239 | if (val) | |
0f4630f3 | 240 | gc->write_reg(gc->reg_set, mask); |
e027d6f9 | 241 | else |
0f4630f3 | 242 | gc->write_reg(gc->reg_clr, mask); |
e027d6f9 JI |
243 | } |
244 | ||
dd86a0cc JI |
245 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
246 | { | |
24efd94b | 247 | unsigned long mask = bgpio_line2mask(gc, gpio); |
dd86a0cc JI |
248 | unsigned long flags; |
249 | ||
3c938cc5 | 250 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
dd86a0cc JI |
251 | |
252 | if (val) | |
0f4630f3 | 253 | gc->bgpio_data |= mask; |
dd86a0cc | 254 | else |
0f4630f3 | 255 | gc->bgpio_data &= ~mask; |
dd86a0cc | 256 | |
0f4630f3 | 257 | gc->write_reg(gc->reg_set, gc->bgpio_data); |
dd86a0cc | 258 | |
3c938cc5 | 259 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
dd86a0cc JI |
260 | } |
261 | ||
0f4630f3 | 262 | static void bgpio_multiple_get_masks(struct gpio_chip *gc, |
73c4ceda RI |
263 | unsigned long *mask, unsigned long *bits, |
264 | unsigned long *set_mask, | |
265 | unsigned long *clear_mask) | |
266 | { | |
267 | int i; | |
268 | ||
269 | *set_mask = 0; | |
270 | *clear_mask = 0; | |
271 | ||
761b5c30 AS |
272 | for_each_set_bit(i, mask, gc->bgpio_bits) { |
273 | if (test_bit(i, bits)) | |
274 | *set_mask |= bgpio_line2mask(gc, i); | |
275 | else | |
276 | *clear_mask |= bgpio_line2mask(gc, i); | |
73c4ceda RI |
277 | } |
278 | } | |
279 | ||
0f4630f3 | 280 | static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, |
73c4ceda RI |
281 | unsigned long *mask, |
282 | unsigned long *bits, | |
283 | void __iomem *reg) | |
284 | { | |
285 | unsigned long flags; | |
286 | unsigned long set_mask, clear_mask; | |
287 | ||
3c938cc5 | 288 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
73c4ceda | 289 | |
0f4630f3 | 290 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda | 291 | |
0f4630f3 LW |
292 | gc->bgpio_data |= set_mask; |
293 | gc->bgpio_data &= ~clear_mask; | |
73c4ceda | 294 | |
0f4630f3 | 295 | gc->write_reg(reg, gc->bgpio_data); |
73c4ceda | 296 | |
3c938cc5 | 297 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
73c4ceda RI |
298 | } |
299 | ||
300 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
301 | unsigned long *bits) | |
302 | { | |
0f4630f3 | 303 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); |
73c4ceda RI |
304 | } |
305 | ||
306 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, | |
307 | unsigned long *bits) | |
308 | { | |
0f4630f3 | 309 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); |
73c4ceda RI |
310 | } |
311 | ||
312 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, | |
313 | unsigned long *mask, | |
314 | unsigned long *bits) | |
315 | { | |
73c4ceda RI |
316 | unsigned long set_mask, clear_mask; |
317 | ||
0f4630f3 | 318 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda RI |
319 | |
320 | if (set_mask) | |
0f4630f3 | 321 | gc->write_reg(gc->reg_set, set_mask); |
73c4ceda | 322 | if (clear_mask) |
0f4630f3 | 323 | gc->write_reg(gc->reg_clr, clear_mask); |
73c4ceda RI |
324 | } |
325 | ||
31029116 JI |
326 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
327 | { | |
328 | return 0; | |
329 | } | |
330 | ||
91492a44 RV |
331 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
332 | int val) | |
333 | { | |
334 | return -EINVAL; | |
335 | } | |
336 | ||
31029116 JI |
337 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
338 | int val) | |
339 | { | |
340 | gc->set(gc, gpio, val); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
aeec56e3 AV |
345 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
346 | { | |
31029116 JI |
347 | unsigned long flags; |
348 | ||
3c938cc5 | 349 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 350 | |
f69e00bd LW |
351 | gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); |
352 | ||
353 | if (gc->reg_dir_in) | |
354 | gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); | |
355 | if (gc->reg_dir_out) | |
356 | gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); | |
31029116 | 357 | |
3c938cc5 | 358 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 359 | |
aeec56e3 AV |
360 | return 0; |
361 | } | |
362 | ||
db3b0fcc PZ |
363 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
364 | { | |
f69e00bd | 365 | /* Return 0 if output, 1 if input */ |
e42615ec MV |
366 | if (gc->bgpio_dir_unreadable) { |
367 | if (gc->bgpio_dir & bgpio_line2mask(gc, gpio)) | |
368 | return GPIO_LINE_DIRECTION_OUT; | |
369 | return GPIO_LINE_DIRECTION_IN; | |
370 | } | |
371 | ||
372 | if (gc->reg_dir_out) { | |
373 | if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) | |
374 | return GPIO_LINE_DIRECTION_OUT; | |
375 | return GPIO_LINE_DIRECTION_IN; | |
376 | } | |
377 | ||
f69e00bd | 378 | if (gc->reg_dir_in) |
e42615ec MV |
379 | if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) |
380 | return GPIO_LINE_DIRECTION_OUT; | |
f69e00bd | 381 | |
e42615ec | 382 | return GPIO_LINE_DIRECTION_IN; |
db3b0fcc PZ |
383 | } |
384 | ||
d19d2de6 | 385 | static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
aeec56e3 | 386 | { |
31029116 JI |
387 | unsigned long flags; |
388 | ||
3c938cc5 | 389 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 390 | |
f69e00bd LW |
391 | gc->bgpio_dir |= bgpio_line2mask(gc, gpio); |
392 | ||
393 | if (gc->reg_dir_in) | |
394 | gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); | |
395 | if (gc->reg_dir_out) | |
396 | gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); | |
31029116 | 397 | |
3c938cc5 | 398 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
d19d2de6 | 399 | } |
31029116 | 400 | |
d19d2de6 CG |
401 | static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, |
402 | int val) | |
403 | { | |
404 | bgpio_dir_out(gc, gpio, val); | |
405 | gc->set(gc, gpio, val); | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, | |
410 | int val) | |
411 | { | |
412 | gc->set(gc, gpio, val); | |
413 | bgpio_dir_out(gc, gpio, val); | |
aeec56e3 AV |
414 | return 0; |
415 | } | |
416 | ||
280df6b3 | 417 | static int bgpio_setup_accessors(struct device *dev, |
0f4630f3 | 418 | struct gpio_chip *gc, |
2b78f1e1 | 419 | bool byte_be) |
aeec56e3 | 420 | { |
8467afec | 421 | |
0f4630f3 | 422 | switch (gc->bgpio_bits) { |
8467afec | 423 | case 8: |
0f4630f3 LW |
424 | gc->read_reg = bgpio_read8; |
425 | gc->write_reg = bgpio_write8; | |
8467afec JI |
426 | break; |
427 | case 16: | |
2b78f1e1 | 428 | if (byte_be) { |
0f4630f3 LW |
429 | gc->read_reg = bgpio_read16be; |
430 | gc->write_reg = bgpio_write16be; | |
2b78f1e1 | 431 | } else { |
0f4630f3 LW |
432 | gc->read_reg = bgpio_read16; |
433 | gc->write_reg = bgpio_write16; | |
2b78f1e1 | 434 | } |
8467afec JI |
435 | break; |
436 | case 32: | |
2b78f1e1 | 437 | if (byte_be) { |
0f4630f3 LW |
438 | gc->read_reg = bgpio_read32be; |
439 | gc->write_reg = bgpio_write32be; | |
2b78f1e1 | 440 | } else { |
0f4630f3 LW |
441 | gc->read_reg = bgpio_read32; |
442 | gc->write_reg = bgpio_write32; | |
2b78f1e1 | 443 | } |
8467afec JI |
444 | break; |
445 | #if BITS_PER_LONG >= 64 | |
446 | case 64: | |
2b78f1e1 AL |
447 | if (byte_be) { |
448 | dev_err(dev, | |
449 | "64 bit big endian byte order unsupported\n"); | |
450 | return -EINVAL; | |
451 | } else { | |
0f4630f3 LW |
452 | gc->read_reg = bgpio_read64; |
453 | gc->write_reg = bgpio_write64; | |
2b78f1e1 | 454 | } |
8467afec JI |
455 | break; |
456 | #endif /* BITS_PER_LONG >= 64 */ | |
457 | default: | |
0f4630f3 | 458 | dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); |
8467afec JI |
459 | return -EINVAL; |
460 | } | |
461 | ||
8467afec JI |
462 | return 0; |
463 | } | |
464 | ||
e027d6f9 JI |
465 | /* |
466 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 467 | * three supported configurations: |
e027d6f9 | 468 | * |
dd86a0cc | 469 | * - single input/output register resource (named "dat"). |
e027d6f9 | 470 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
471 | * - single output register resource and single input resource ("set" and |
472 | * dat"). | |
e027d6f9 JI |
473 | * |
474 | * For the single output register, this drives a 1 by setting a bit and a zero | |
475 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
476 | * in the set register and clears it by setting a bit in the clear register. | |
477 | * The configuration is detected by which resources are present. | |
31029116 JI |
478 | * |
479 | * For setting the GPIO direction, there are three supported configurations: | |
480 | * | |
481 | * - simple bidirection GPIO that requires no configuration. | |
482 | * - an output direction register (named "dirout") where a 1 bit | |
483 | * indicates the GPIO is an output. | |
484 | * - an input direction register (named "dirin") where a 1 bit indicates | |
485 | * the GPIO is an input. | |
e027d6f9 | 486 | */ |
0f4630f3 | 487 | static int bgpio_setup_io(struct gpio_chip *gc, |
280df6b3 JI |
488 | void __iomem *dat, |
489 | void __iomem *set, | |
b19e7f51 VZ |
490 | void __iomem *clr, |
491 | unsigned long flags) | |
8467afec | 492 | { |
aeec56e3 | 493 | |
0f4630f3 LW |
494 | gc->reg_dat = dat; |
495 | if (!gc->reg_dat) | |
280df6b3 | 496 | return -EINVAL; |
e027d6f9 | 497 | |
280df6b3 | 498 | if (set && clr) { |
0f4630f3 LW |
499 | gc->reg_set = set; |
500 | gc->reg_clr = clr; | |
501 | gc->set = bgpio_set_with_clear; | |
502 | gc->set_multiple = bgpio_set_multiple_with_clear; | |
280df6b3 | 503 | } else if (set && !clr) { |
0f4630f3 LW |
504 | gc->reg_set = set; |
505 | gc->set = bgpio_set_set; | |
506 | gc->set_multiple = bgpio_set_multiple_set; | |
91492a44 | 507 | } else if (flags & BGPIOF_NO_OUTPUT) { |
0f4630f3 LW |
508 | gc->set = bgpio_set_none; |
509 | gc->set_multiple = NULL; | |
e027d6f9 | 510 | } else { |
0f4630f3 LW |
511 | gc->set = bgpio_set; |
512 | gc->set_multiple = bgpio_set_multiple; | |
aeec56e3 AV |
513 | } |
514 | ||
b19e7f51 | 515 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
80057cb4 | 516 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) { |
0f4630f3 | 517 | gc->get = bgpio_get_set; |
80057cb4 LW |
518 | if (!gc->be_bits) |
519 | gc->get_multiple = bgpio_get_set_multiple; | |
520 | /* | |
521 | * We deliberately avoid assigning the ->get_multiple() call | |
522 | * for big endian mirrored registers which are ALSO reflecting | |
523 | * their value in the set register when used as output. It is | |
524 | * simply too much complexity, let the GPIO core fall back to | |
525 | * reading each line individually in that fringe case. | |
526 | */ | |
527 | } else { | |
0f4630f3 | 528 | gc->get = bgpio_get; |
80057cb4 LW |
529 | if (gc->be_bits) |
530 | gc->get_multiple = bgpio_get_multiple_be; | |
531 | else | |
532 | gc->get_multiple = bgpio_get_multiple; | |
533 | } | |
dd86a0cc | 534 | |
e027d6f9 JI |
535 | return 0; |
536 | } | |
537 | ||
0f4630f3 | 538 | static int bgpio_setup_direction(struct gpio_chip *gc, |
280df6b3 | 539 | void __iomem *dirout, |
91492a44 RV |
540 | void __iomem *dirin, |
541 | unsigned long flags) | |
31029116 | 542 | { |
f69e00bd LW |
543 | if (dirout || dirin) { |
544 | gc->reg_dir_out = dirout; | |
545 | gc->reg_dir_in = dirin; | |
d19d2de6 CG |
546 | if (flags & BGPIOF_NO_SET_ON_INPUT) |
547 | gc->direction_output = bgpio_dir_out_dir_first; | |
548 | else | |
549 | gc->direction_output = bgpio_dir_out_val_first; | |
d799a4de LW |
550 | gc->direction_input = bgpio_dir_in; |
551 | gc->get_direction = bgpio_get_dir; | |
31029116 | 552 | } else { |
91492a44 | 553 | if (flags & BGPIOF_NO_OUTPUT) |
0f4630f3 | 554 | gc->direction_output = bgpio_dir_out_err; |
91492a44 | 555 | else |
0f4630f3 LW |
556 | gc->direction_output = bgpio_simple_dir_out; |
557 | gc->direction_input = bgpio_simple_dir_in; | |
31029116 JI |
558 | } |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
7b42e3db AF |
563 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
564 | { | |
565 | if (gpio_pin < chip->ngpio) | |
566 | return 0; | |
567 | ||
568 | return -EINVAL; | |
569 | } | |
570 | ||
d799a4de LW |
571 | /** |
572 | * bgpio_init() - Initialize generic GPIO accessor functions | |
573 | * @gc: the GPIO chip to set up | |
574 | * @dev: the parent device of the new GPIO chip (compulsory) | |
575 | * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 | |
576 | * @dat: MMIO address for the register to READ the value of the GPIO lines, it | |
577 | * is expected that a 1 in the corresponding bit in this register means the | |
578 | * line is asserted | |
579 | * @set: MMIO address for the register to SET the value of the GPIO lines, it is | |
580 | * expected that we write the line with 1 in this register to drive the GPIO line | |
581 | * high. | |
582 | * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is | |
583 | * expected that we write the line with 1 in this register to drive the GPIO line | |
584 | * low. It is allowed to leave this address as NULL, in that case the SET register | |
585 | * will be assumed to also clear the GPIO lines, by actively writing the line | |
586 | * with 0. | |
587 | * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed | |
588 | * that setting a line to 1 in this register will turn that line into an | |
589 | * output line. Conversely, setting the line to 0 will turn that line into | |
f69e00bd | 590 | * an input. |
d799a4de LW |
591 | * @dirin: MMIO address for the register to set this line as INPUT. It is assumed |
592 | * that setting a line to 1 in this register will turn that line into an | |
593 | * input line. Conversely, setting the line to 0 will turn that line into | |
f69e00bd | 594 | * an output. |
d799a4de LW |
595 | * @flags: Different flags that will affect the behaviour of the device, such as |
596 | * endianness etc. | |
597 | */ | |
0f4630f3 | 598 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
4f5b0480 RK |
599 | unsigned long sz, void __iomem *dat, void __iomem *set, |
600 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 601 | unsigned long flags) |
e027d6f9 | 602 | { |
e027d6f9 | 603 | int ret; |
e027d6f9 | 604 | |
280df6b3 JI |
605 | if (!is_power_of_2(sz)) |
606 | return -EINVAL; | |
e027d6f9 | 607 | |
0f4630f3 LW |
608 | gc->bgpio_bits = sz * 8; |
609 | if (gc->bgpio_bits > BITS_PER_LONG) | |
280df6b3 JI |
610 | return -EINVAL; |
611 | ||
3c938cc5 | 612 | raw_spin_lock_init(&gc->bgpio_lock); |
0f4630f3 LW |
613 | gc->parent = dev; |
614 | gc->label = dev_name(dev); | |
615 | gc->base = -1; | |
0f4630f3 | 616 | gc->request = bgpio_request; |
80057cb4 | 617 | gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); |
280df6b3 | 618 | |
55b2395e AM |
619 | ret = gpiochip_get_ngpios(gc, dev); |
620 | if (ret) | |
621 | gc->ngpio = gc->bgpio_bits; | |
622 | else | |
623 | gc->bgpio_bits = roundup_pow_of_two(round_up(gc->ngpio, 8)); | |
624 | ||
0f4630f3 | 625 | ret = bgpio_setup_io(gc, dat, set, clr, flags); |
e027d6f9 JI |
626 | if (ret) |
627 | return ret; | |
aeec56e3 | 628 | |
24efd94b | 629 | ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
8467afec JI |
630 | if (ret) |
631 | return ret; | |
aeec56e3 | 632 | |
0f4630f3 | 633 | ret = bgpio_setup_direction(gc, dirout, dirin, flags); |
31029116 JI |
634 | if (ret) |
635 | return ret; | |
636 | ||
0f4630f3 LW |
637 | gc->bgpio_data = gc->read_reg(gc->reg_dat); |
638 | if (gc->set == bgpio_set_set && | |
3e11f7b8 | 639 | !(flags & BGPIOF_UNREADABLE_REG_SET)) |
0f4630f3 | 640 | gc->bgpio_data = gc->read_reg(gc->reg_set); |
f69e00bd LW |
641 | |
642 | if (flags & BGPIOF_UNREADABLE_REG_DIR) | |
643 | gc->bgpio_dir_unreadable = true; | |
644 | ||
645 | /* | |
646 | * Inspect hardware to find initial direction setting. | |
647 | */ | |
648 | if ((gc->reg_dir_out || gc->reg_dir_in) && | |
649 | !(flags & BGPIOF_UNREADABLE_REG_DIR)) { | |
650 | if (gc->reg_dir_out) | |
651 | gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); | |
652 | else if (gc->reg_dir_in) | |
653 | gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); | |
654 | /* | |
655 | * If we have two direction registers, synchronise | |
656 | * input setting to output setting, the library | |
657 | * can not handle a line being input and output at | |
658 | * the same time. | |
659 | */ | |
660 | if (gc->reg_dir_out && gc->reg_dir_in) | |
661 | gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); | |
662 | } | |
924e7a9f | 663 | |
280df6b3 JI |
664 | return ret; |
665 | } | |
666 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 667 | |
8f01c9d0 | 668 | #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) |
aeec56e3 | 669 | |
280df6b3 JI |
670 | static void __iomem *bgpio_map(struct platform_device *pdev, |
671 | const char *name, | |
8d240260 | 672 | resource_size_t sane_sz) |
280df6b3 | 673 | { |
280df6b3 | 674 | struct resource *r; |
280df6b3 | 675 | resource_size_t sz; |
280df6b3 JI |
676 | |
677 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
8d240260 | 678 | if (!r) |
b2f68b63 | 679 | return NULL; |
280df6b3 JI |
680 | |
681 | sz = resource_size(r); | |
8d240260 HK |
682 | if (sz != sane_sz) |
683 | return IOMEM_ERR_PTR(-EINVAL); | |
280df6b3 | 684 | |
8d240260 | 685 | return devm_ioremap_resource(&pdev->dev, r); |
aeec56e3 AV |
686 | } |
687 | ||
e698613a | 688 | static const struct of_device_id bgpio_of_match[] = { |
05cc995f | 689 | { .compatible = "brcm,bcm6345-gpio" }, |
c0d30ecf | 690 | { .compatible = "wd,mbl-gpio" }, |
b8c90199 | 691 | { .compatible = "ni,169445-nand-gpio" }, |
e698613a ÁFR |
692 | { } |
693 | }; | |
694 | MODULE_DEVICE_TABLE(of, bgpio_of_match); | |
695 | ||
001cf2de | 696 | static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags) |
e698613a ÁFR |
697 | { |
698 | struct bgpio_pdata *pdata; | |
699 | ||
001cf2de | 700 | if (!dev_fwnode(dev)) |
e698613a ÁFR |
701 | return NULL; |
702 | ||
001cf2de | 703 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
e698613a ÁFR |
704 | if (!pdata) |
705 | return ERR_PTR(-ENOMEM); | |
706 | ||
707 | pdata->base = -1; | |
708 | ||
001cf2de | 709 | if (device_is_big_endian(dev)) |
05cc995f CL |
710 | *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; |
711 | ||
001cf2de | 712 | if (device_property_read_bool(dev, "no-output")) |
c0d30ecf CL |
713 | *flags |= BGPIOF_NO_OUTPUT; |
714 | ||
e698613a ÁFR |
715 | return pdata; |
716 | } | |
e698613a | 717 | |
3836309d | 718 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
719 | { |
720 | struct device *dev = &pdev->dev; | |
721 | struct resource *r; | |
722 | void __iomem *dat; | |
723 | void __iomem *set; | |
724 | void __iomem *clr; | |
725 | void __iomem *dirout; | |
726 | void __iomem *dirin; | |
727 | unsigned long sz; | |
e698613a | 728 | unsigned long flags = 0; |
280df6b3 | 729 | int err; |
0f4630f3 | 730 | struct gpio_chip *gc; |
e698613a ÁFR |
731 | struct bgpio_pdata *pdata; |
732 | ||
001cf2de | 733 | pdata = bgpio_parse_fw(dev, &flags); |
e698613a ÁFR |
734 | if (IS_ERR(pdata)) |
735 | return PTR_ERR(pdata); | |
736 | ||
737 | if (!pdata) { | |
738 | pdata = dev_get_platdata(dev); | |
739 | flags = pdev->id_entry->driver_data; | |
740 | } | |
280df6b3 JI |
741 | |
742 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
743 | if (!r) | |
744 | return -EINVAL; | |
745 | ||
746 | sz = resource_size(r); | |
747 | ||
8d240260 HK |
748 | dat = bgpio_map(pdev, "dat", sz); |
749 | if (IS_ERR(dat)) | |
750 | return PTR_ERR(dat); | |
280df6b3 | 751 | |
8d240260 HK |
752 | set = bgpio_map(pdev, "set", sz); |
753 | if (IS_ERR(set)) | |
754 | return PTR_ERR(set); | |
280df6b3 | 755 | |
8d240260 HK |
756 | clr = bgpio_map(pdev, "clr", sz); |
757 | if (IS_ERR(clr)) | |
758 | return PTR_ERR(clr); | |
280df6b3 | 759 | |
8d240260 HK |
760 | dirout = bgpio_map(pdev, "dirout", sz); |
761 | if (IS_ERR(dirout)) | |
762 | return PTR_ERR(dirout); | |
280df6b3 | 763 | |
8d240260 HK |
764 | dirin = bgpio_map(pdev, "dirin", sz); |
765 | if (IS_ERR(dirin)) | |
766 | return PTR_ERR(dirin); | |
280df6b3 | 767 | |
0f4630f3 LW |
768 | gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); |
769 | if (!gc) | |
280df6b3 JI |
770 | return -ENOMEM; |
771 | ||
0f4630f3 | 772 | err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
773 | if (err) |
774 | return err; | |
775 | ||
776 | if (pdata) { | |
781f6d71 | 777 | if (pdata->label) |
0f4630f3 LW |
778 | gc->label = pdata->label; |
779 | gc->base = pdata->base; | |
280df6b3 | 780 | if (pdata->ngpio > 0) |
0f4630f3 | 781 | gc->ngpio = pdata->ngpio; |
280df6b3 JI |
782 | } |
783 | ||
0f4630f3 | 784 | platform_set_drvdata(pdev, gc); |
280df6b3 | 785 | |
c05f813b | 786 | return devm_gpiochip_add_data(&pdev->dev, gc, NULL); |
aeec56e3 AV |
787 | } |
788 | ||
789 | static const struct platform_device_id bgpio_id_table[] = { | |
19338530 AS |
790 | { |
791 | .name = "basic-mmio-gpio", | |
792 | .driver_data = 0, | |
793 | }, { | |
794 | .name = "basic-mmio-gpio-be", | |
795 | .driver_data = BGPIOF_BIG_ENDIAN, | |
796 | }, | |
797 | { } | |
aeec56e3 AV |
798 | }; |
799 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
800 | ||
801 | static struct platform_driver bgpio_driver = { | |
802 | .driver = { | |
803 | .name = "basic-mmio-gpio", | |
001cf2de | 804 | .of_match_table = bgpio_of_match, |
aeec56e3 AV |
805 | }, |
806 | .id_table = bgpio_id_table, | |
280df6b3 | 807 | .probe = bgpio_pdev_probe, |
aeec56e3 AV |
808 | }; |
809 | ||
6f61415e | 810 | module_platform_driver(bgpio_driver); |
280df6b3 | 811 | |
c103de24 | 812 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
813 | |
814 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
815 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
816 | MODULE_LICENSE("GPL"); |