Commit | Line | Data |
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dae5f0af | 1 | // SPDX-License-Identifier: GPL-2.0+ |
aeec56e3 | 2 | /* |
c103de24 | 3 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
4 | * |
5 | * Copyright 2008 MontaVista Software, Inc. | |
6 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
7 | * | |
aeec56e3 AV |
8 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... |
9 | * ...`` ```````.. | |
10 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
11 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
12 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
13 | * ````````` | |
14 | ___ | |
15 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
16 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
17 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
18 | `....trivial..'~`.```.``` | |
19 | * ``````` | |
20 | * .```````~~~~`..`.``.``. | |
21 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
22 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
23 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
24 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
25 | * ``.`.``...``` ```.. output pins are also supported.` | |
26 | * ^^ `````.`````````.,``~``~``~~`````` | |
27 | * . ^^ | |
28 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
29 | * .. The expectation is that in at least some cases . ,-~~~-, | |
30 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
31 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
32 | * ..````````......``````````` \o_ | |
33 | * | | |
34 | * ^^ / \ | |
35 | * | |
36 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
37 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
38 | * . the number of GPIOs is determined by the width of ~ | |
39 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
40 | * `.......````.``` | |
41 | */ | |
42 | ||
43 | #include <linux/init.h> | |
280df6b3 | 44 | #include <linux/err.h> |
aeec56e3 AV |
45 | #include <linux/bug.h> |
46 | #include <linux/kernel.h> | |
47 | #include <linux/module.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/compiler.h> | |
50 | #include <linux/types.h> | |
51 | #include <linux/errno.h> | |
52 | #include <linux/log2.h> | |
53 | #include <linux/ioport.h> | |
54 | #include <linux/io.h> | |
0f4630f3 | 55 | #include <linux/gpio/driver.h> |
aeec56e3 | 56 | #include <linux/slab.h> |
4b63739e | 57 | #include <linux/bitops.h> |
aeec56e3 AV |
58 | #include <linux/platform_device.h> |
59 | #include <linux/mod_devicetable.h> | |
e698613a ÁFR |
60 | #include <linux/of.h> |
61 | #include <linux/of_device.h> | |
aeec56e3 | 62 | |
8467afec | 63 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 64 | { |
fd996235 | 65 | writeb(data, reg); |
aeec56e3 AV |
66 | } |
67 | ||
8467afec | 68 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 69 | { |
fd996235 | 70 | return readb(reg); |
8467afec JI |
71 | } |
72 | ||
73 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
74 | { | |
fd996235 | 75 | writew(data, reg); |
8467afec JI |
76 | } |
77 | ||
78 | static unsigned long bgpio_read16(void __iomem *reg) | |
79 | { | |
fd996235 | 80 | return readw(reg); |
8467afec JI |
81 | } |
82 | ||
83 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
84 | { | |
fd996235 | 85 | writel(data, reg); |
8467afec JI |
86 | } |
87 | ||
88 | static unsigned long bgpio_read32(void __iomem *reg) | |
89 | { | |
fd996235 | 90 | return readl(reg); |
8467afec JI |
91 | } |
92 | ||
aeec56e3 | 93 | #if BITS_PER_LONG >= 64 |
8467afec JI |
94 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
95 | { | |
fd996235 | 96 | writeq(data, reg); |
8467afec JI |
97 | } |
98 | ||
99 | static unsigned long bgpio_read64(void __iomem *reg) | |
100 | { | |
fd996235 | 101 | return readq(reg); |
aeec56e3 | 102 | } |
8467afec | 103 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 | 104 | |
2b78f1e1 AL |
105 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
106 | { | |
107 | iowrite16be(data, reg); | |
108 | } | |
109 | ||
110 | static unsigned long bgpio_read16be(void __iomem *reg) | |
111 | { | |
112 | return ioread16be(reg); | |
113 | } | |
114 | ||
115 | static void bgpio_write32be(void __iomem *reg, unsigned long data) | |
116 | { | |
117 | iowrite32be(data, reg); | |
118 | } | |
119 | ||
120 | static unsigned long bgpio_read32be(void __iomem *reg) | |
121 | { | |
122 | return ioread32be(reg); | |
123 | } | |
124 | ||
24efd94b | 125 | static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) |
aeec56e3 | 126 | { |
24efd94b LW |
127 | if (gc->be_bits) |
128 | return BIT(gc->bgpio_bits - 1 - line); | |
129 | return BIT(line); | |
aeec56e3 AV |
130 | } |
131 | ||
b19e7f51 VZ |
132 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
133 | { | |
24efd94b | 134 | unsigned long pinmask = bgpio_line2mask(gc, gpio); |
d799a4de | 135 | bool dir = !!(gc->bgpio_dir & pinmask); |
b19e7f51 | 136 | |
d799a4de | 137 | if (dir) |
0f4630f3 | 138 | return !!(gc->read_reg(gc->reg_set) & pinmask); |
b19e7f51 | 139 | else |
0f4630f3 | 140 | return !!(gc->read_reg(gc->reg_dat) & pinmask); |
b19e7f51 VZ |
141 | } |
142 | ||
80057cb4 LW |
143 | /* |
144 | * This assumes that the bits in the GPIO register are in native endianness. | |
145 | * We only assign the function pointer if we have that. | |
146 | */ | |
147 | static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
148 | unsigned long *bits) | |
149 | { | |
150 | unsigned long get_mask = 0; | |
151 | unsigned long set_mask = 0; | |
80057cb4 | 152 | |
07c7b6a5 LW |
153 | /* Make sure we first clear any bits that are zero when we read the register */ |
154 | *bits &= ~*mask; | |
155 | ||
4f2f95e9 JK |
156 | set_mask = *mask & gc->bgpio_dir; |
157 | get_mask = *mask & ~gc->bgpio_dir; | |
80057cb4 LW |
158 | |
159 | if (set_mask) | |
160 | *bits |= gc->read_reg(gc->reg_set) & set_mask; | |
161 | if (get_mask) | |
162 | *bits |= gc->read_reg(gc->reg_dat) & get_mask; | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
aeec56e3 AV |
167 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
168 | { | |
24efd94b | 169 | return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); |
aeec56e3 AV |
170 | } |
171 | ||
80057cb4 LW |
172 | /* |
173 | * This only works if the bits in the GPIO register are in native endianness. | |
80057cb4 LW |
174 | */ |
175 | static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, | |
176 | unsigned long *bits) | |
177 | { | |
07c7b6a5 LW |
178 | /* Make sure we first clear any bits that are zero when we read the register */ |
179 | *bits &= ~*mask; | |
180 | *bits |= gc->read_reg(gc->reg_dat) & *mask; | |
80057cb4 LW |
181 | return 0; |
182 | } | |
183 | ||
184 | /* | |
185 | * With big endian mirrored bit order it becomes more tedious. | |
186 | */ | |
187 | static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, | |
188 | unsigned long *bits) | |
189 | { | |
190 | unsigned long readmask = 0; | |
191 | unsigned long val; | |
192 | int bit; | |
193 | ||
07c7b6a5 LW |
194 | /* Make sure we first clear any bits that are zero when we read the register */ |
195 | *bits &= ~*mask; | |
196 | ||
80057cb4 | 197 | /* Create a mirrored mask */ |
07c7b6a5 LW |
198 | bit = -1; |
199 | while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio) | |
80057cb4 LW |
200 | readmask |= bgpio_line2mask(gc, bit); |
201 | ||
202 | /* Read the register */ | |
203 | val = gc->read_reg(gc->reg_dat) & readmask; | |
204 | ||
205 | /* | |
206 | * Mirror the result into the "bits" result, this will give line 0 | |
207 | * in bit 0 ... line 31 in bit 31 for a 32bit register. | |
208 | */ | |
07c7b6a5 LW |
209 | bit = -1; |
210 | while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio) | |
80057cb4 LW |
211 | *bits |= bgpio_line2mask(gc, bit); |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
91492a44 RV |
216 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
217 | { | |
218 | } | |
219 | ||
aeec56e3 AV |
220 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
221 | { | |
24efd94b | 222 | unsigned long mask = bgpio_line2mask(gc, gpio); |
aeec56e3 AV |
223 | unsigned long flags; |
224 | ||
0f4630f3 | 225 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
aeec56e3 AV |
226 | |
227 | if (val) | |
0f4630f3 | 228 | gc->bgpio_data |= mask; |
aeec56e3 | 229 | else |
0f4630f3 | 230 | gc->bgpio_data &= ~mask; |
aeec56e3 | 231 | |
0f4630f3 | 232 | gc->write_reg(gc->reg_dat, gc->bgpio_data); |
aeec56e3 | 233 | |
0f4630f3 | 234 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
aeec56e3 AV |
235 | } |
236 | ||
e027d6f9 JI |
237 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
238 | int val) | |
239 | { | |
24efd94b | 240 | unsigned long mask = bgpio_line2mask(gc, gpio); |
e027d6f9 JI |
241 | |
242 | if (val) | |
0f4630f3 | 243 | gc->write_reg(gc->reg_set, mask); |
e027d6f9 | 244 | else |
0f4630f3 | 245 | gc->write_reg(gc->reg_clr, mask); |
e027d6f9 JI |
246 | } |
247 | ||
dd86a0cc JI |
248 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
249 | { | |
24efd94b | 250 | unsigned long mask = bgpio_line2mask(gc, gpio); |
dd86a0cc JI |
251 | unsigned long flags; |
252 | ||
0f4630f3 | 253 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
dd86a0cc JI |
254 | |
255 | if (val) | |
0f4630f3 | 256 | gc->bgpio_data |= mask; |
dd86a0cc | 257 | else |
0f4630f3 | 258 | gc->bgpio_data &= ~mask; |
dd86a0cc | 259 | |
0f4630f3 | 260 | gc->write_reg(gc->reg_set, gc->bgpio_data); |
dd86a0cc | 261 | |
0f4630f3 | 262 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
dd86a0cc JI |
263 | } |
264 | ||
0f4630f3 | 265 | static void bgpio_multiple_get_masks(struct gpio_chip *gc, |
73c4ceda RI |
266 | unsigned long *mask, unsigned long *bits, |
267 | unsigned long *set_mask, | |
268 | unsigned long *clear_mask) | |
269 | { | |
270 | int i; | |
271 | ||
272 | *set_mask = 0; | |
273 | *clear_mask = 0; | |
274 | ||
0f4630f3 | 275 | for (i = 0; i < gc->bgpio_bits; i++) { |
73c4ceda RI |
276 | if (*mask == 0) |
277 | break; | |
278 | if (__test_and_clear_bit(i, mask)) { | |
279 | if (test_bit(i, bits)) | |
24efd94b | 280 | *set_mask |= bgpio_line2mask(gc, i); |
73c4ceda | 281 | else |
24efd94b | 282 | *clear_mask |= bgpio_line2mask(gc, i); |
73c4ceda RI |
283 | } |
284 | } | |
285 | } | |
286 | ||
0f4630f3 | 287 | static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, |
73c4ceda RI |
288 | unsigned long *mask, |
289 | unsigned long *bits, | |
290 | void __iomem *reg) | |
291 | { | |
292 | unsigned long flags; | |
293 | unsigned long set_mask, clear_mask; | |
294 | ||
0f4630f3 | 295 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
73c4ceda | 296 | |
0f4630f3 | 297 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda | 298 | |
0f4630f3 LW |
299 | gc->bgpio_data |= set_mask; |
300 | gc->bgpio_data &= ~clear_mask; | |
73c4ceda | 301 | |
0f4630f3 | 302 | gc->write_reg(reg, gc->bgpio_data); |
73c4ceda | 303 | |
0f4630f3 | 304 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
73c4ceda RI |
305 | } |
306 | ||
307 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
308 | unsigned long *bits) | |
309 | { | |
0f4630f3 | 310 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); |
73c4ceda RI |
311 | } |
312 | ||
313 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, | |
314 | unsigned long *bits) | |
315 | { | |
0f4630f3 | 316 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); |
73c4ceda RI |
317 | } |
318 | ||
319 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, | |
320 | unsigned long *mask, | |
321 | unsigned long *bits) | |
322 | { | |
73c4ceda RI |
323 | unsigned long set_mask, clear_mask; |
324 | ||
0f4630f3 | 325 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda RI |
326 | |
327 | if (set_mask) | |
0f4630f3 | 328 | gc->write_reg(gc->reg_set, set_mask); |
73c4ceda | 329 | if (clear_mask) |
0f4630f3 | 330 | gc->write_reg(gc->reg_clr, clear_mask); |
73c4ceda RI |
331 | } |
332 | ||
31029116 JI |
333 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
334 | { | |
335 | return 0; | |
336 | } | |
337 | ||
91492a44 RV |
338 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
339 | int val) | |
340 | { | |
341 | return -EINVAL; | |
342 | } | |
343 | ||
31029116 JI |
344 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
345 | int val) | |
346 | { | |
347 | gc->set(gc, gpio, val); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
aeec56e3 AV |
352 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
353 | { | |
31029116 JI |
354 | unsigned long flags; |
355 | ||
0f4630f3 | 356 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 357 | |
f69e00bd LW |
358 | gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); |
359 | ||
360 | if (gc->reg_dir_in) | |
361 | gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); | |
362 | if (gc->reg_dir_out) | |
363 | gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); | |
31029116 | 364 | |
0f4630f3 | 365 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 366 | |
aeec56e3 AV |
367 | return 0; |
368 | } | |
369 | ||
db3b0fcc PZ |
370 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
371 | { | |
f69e00bd LW |
372 | /* Return 0 if output, 1 if input */ |
373 | if (gc->bgpio_dir_unreadable) | |
374 | return !(gc->bgpio_dir & bgpio_line2mask(gc, gpio)); | |
375 | if (gc->reg_dir_out) | |
376 | return !(gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)); | |
377 | if (gc->reg_dir_in) | |
378 | return !!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)); | |
379 | ||
380 | /* This should not happen */ | |
381 | return 1; | |
db3b0fcc PZ |
382 | } |
383 | ||
aeec56e3 AV |
384 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
385 | { | |
31029116 JI |
386 | unsigned long flags; |
387 | ||
388 | gc->set(gc, gpio, val); | |
389 | ||
0f4630f3 | 390 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 391 | |
f69e00bd LW |
392 | gc->bgpio_dir |= bgpio_line2mask(gc, gpio); |
393 | ||
394 | if (gc->reg_dir_in) | |
395 | gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); | |
396 | if (gc->reg_dir_out) | |
397 | gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); | |
31029116 | 398 | |
0f4630f3 | 399 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 400 | |
aeec56e3 AV |
401 | return 0; |
402 | } | |
403 | ||
280df6b3 | 404 | static int bgpio_setup_accessors(struct device *dev, |
0f4630f3 | 405 | struct gpio_chip *gc, |
2b78f1e1 | 406 | bool byte_be) |
aeec56e3 | 407 | { |
8467afec | 408 | |
0f4630f3 | 409 | switch (gc->bgpio_bits) { |
8467afec | 410 | case 8: |
0f4630f3 LW |
411 | gc->read_reg = bgpio_read8; |
412 | gc->write_reg = bgpio_write8; | |
8467afec JI |
413 | break; |
414 | case 16: | |
2b78f1e1 | 415 | if (byte_be) { |
0f4630f3 LW |
416 | gc->read_reg = bgpio_read16be; |
417 | gc->write_reg = bgpio_write16be; | |
2b78f1e1 | 418 | } else { |
0f4630f3 LW |
419 | gc->read_reg = bgpio_read16; |
420 | gc->write_reg = bgpio_write16; | |
2b78f1e1 | 421 | } |
8467afec JI |
422 | break; |
423 | case 32: | |
2b78f1e1 | 424 | if (byte_be) { |
0f4630f3 LW |
425 | gc->read_reg = bgpio_read32be; |
426 | gc->write_reg = bgpio_write32be; | |
2b78f1e1 | 427 | } else { |
0f4630f3 LW |
428 | gc->read_reg = bgpio_read32; |
429 | gc->write_reg = bgpio_write32; | |
2b78f1e1 | 430 | } |
8467afec JI |
431 | break; |
432 | #if BITS_PER_LONG >= 64 | |
433 | case 64: | |
2b78f1e1 AL |
434 | if (byte_be) { |
435 | dev_err(dev, | |
436 | "64 bit big endian byte order unsupported\n"); | |
437 | return -EINVAL; | |
438 | } else { | |
0f4630f3 LW |
439 | gc->read_reg = bgpio_read64; |
440 | gc->write_reg = bgpio_write64; | |
2b78f1e1 | 441 | } |
8467afec JI |
442 | break; |
443 | #endif /* BITS_PER_LONG >= 64 */ | |
444 | default: | |
0f4630f3 | 445 | dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); |
8467afec JI |
446 | return -EINVAL; |
447 | } | |
448 | ||
8467afec JI |
449 | return 0; |
450 | } | |
451 | ||
e027d6f9 JI |
452 | /* |
453 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 454 | * three supported configurations: |
e027d6f9 | 455 | * |
dd86a0cc | 456 | * - single input/output register resource (named "dat"). |
e027d6f9 | 457 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
458 | * - single output register resource and single input resource ("set" and |
459 | * dat"). | |
e027d6f9 JI |
460 | * |
461 | * For the single output register, this drives a 1 by setting a bit and a zero | |
462 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
463 | * in the set register and clears it by setting a bit in the clear register. | |
464 | * The configuration is detected by which resources are present. | |
31029116 JI |
465 | * |
466 | * For setting the GPIO direction, there are three supported configurations: | |
467 | * | |
468 | * - simple bidirection GPIO that requires no configuration. | |
469 | * - an output direction register (named "dirout") where a 1 bit | |
470 | * indicates the GPIO is an output. | |
471 | * - an input direction register (named "dirin") where a 1 bit indicates | |
472 | * the GPIO is an input. | |
e027d6f9 | 473 | */ |
0f4630f3 | 474 | static int bgpio_setup_io(struct gpio_chip *gc, |
280df6b3 JI |
475 | void __iomem *dat, |
476 | void __iomem *set, | |
b19e7f51 VZ |
477 | void __iomem *clr, |
478 | unsigned long flags) | |
8467afec | 479 | { |
aeec56e3 | 480 | |
0f4630f3 LW |
481 | gc->reg_dat = dat; |
482 | if (!gc->reg_dat) | |
280df6b3 | 483 | return -EINVAL; |
e027d6f9 | 484 | |
280df6b3 | 485 | if (set && clr) { |
0f4630f3 LW |
486 | gc->reg_set = set; |
487 | gc->reg_clr = clr; | |
488 | gc->set = bgpio_set_with_clear; | |
489 | gc->set_multiple = bgpio_set_multiple_with_clear; | |
280df6b3 | 490 | } else if (set && !clr) { |
0f4630f3 LW |
491 | gc->reg_set = set; |
492 | gc->set = bgpio_set_set; | |
493 | gc->set_multiple = bgpio_set_multiple_set; | |
91492a44 | 494 | } else if (flags & BGPIOF_NO_OUTPUT) { |
0f4630f3 LW |
495 | gc->set = bgpio_set_none; |
496 | gc->set_multiple = NULL; | |
e027d6f9 | 497 | } else { |
0f4630f3 LW |
498 | gc->set = bgpio_set; |
499 | gc->set_multiple = bgpio_set_multiple; | |
aeec56e3 AV |
500 | } |
501 | ||
b19e7f51 | 502 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
80057cb4 | 503 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) { |
0f4630f3 | 504 | gc->get = bgpio_get_set; |
80057cb4 LW |
505 | if (!gc->be_bits) |
506 | gc->get_multiple = bgpio_get_set_multiple; | |
507 | /* | |
508 | * We deliberately avoid assigning the ->get_multiple() call | |
509 | * for big endian mirrored registers which are ALSO reflecting | |
510 | * their value in the set register when used as output. It is | |
511 | * simply too much complexity, let the GPIO core fall back to | |
512 | * reading each line individually in that fringe case. | |
513 | */ | |
514 | } else { | |
0f4630f3 | 515 | gc->get = bgpio_get; |
80057cb4 LW |
516 | if (gc->be_bits) |
517 | gc->get_multiple = bgpio_get_multiple_be; | |
518 | else | |
519 | gc->get_multiple = bgpio_get_multiple; | |
520 | } | |
dd86a0cc | 521 | |
e027d6f9 JI |
522 | return 0; |
523 | } | |
524 | ||
0f4630f3 | 525 | static int bgpio_setup_direction(struct gpio_chip *gc, |
280df6b3 | 526 | void __iomem *dirout, |
91492a44 RV |
527 | void __iomem *dirin, |
528 | unsigned long flags) | |
31029116 | 529 | { |
f69e00bd LW |
530 | if (dirout || dirin) { |
531 | gc->reg_dir_out = dirout; | |
532 | gc->reg_dir_in = dirin; | |
d799a4de LW |
533 | gc->direction_output = bgpio_dir_out; |
534 | gc->direction_input = bgpio_dir_in; | |
535 | gc->get_direction = bgpio_get_dir; | |
31029116 | 536 | } else { |
91492a44 | 537 | if (flags & BGPIOF_NO_OUTPUT) |
0f4630f3 | 538 | gc->direction_output = bgpio_dir_out_err; |
91492a44 | 539 | else |
0f4630f3 LW |
540 | gc->direction_output = bgpio_simple_dir_out; |
541 | gc->direction_input = bgpio_simple_dir_in; | |
31029116 JI |
542 | } |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
7b42e3db AF |
547 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
548 | { | |
549 | if (gpio_pin < chip->ngpio) | |
550 | return 0; | |
551 | ||
552 | return -EINVAL; | |
553 | } | |
554 | ||
d799a4de LW |
555 | /** |
556 | * bgpio_init() - Initialize generic GPIO accessor functions | |
557 | * @gc: the GPIO chip to set up | |
558 | * @dev: the parent device of the new GPIO chip (compulsory) | |
559 | * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 | |
560 | * @dat: MMIO address for the register to READ the value of the GPIO lines, it | |
561 | * is expected that a 1 in the corresponding bit in this register means the | |
562 | * line is asserted | |
563 | * @set: MMIO address for the register to SET the value of the GPIO lines, it is | |
564 | * expected that we write the line with 1 in this register to drive the GPIO line | |
565 | * high. | |
566 | * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is | |
567 | * expected that we write the line with 1 in this register to drive the GPIO line | |
568 | * low. It is allowed to leave this address as NULL, in that case the SET register | |
569 | * will be assumed to also clear the GPIO lines, by actively writing the line | |
570 | * with 0. | |
571 | * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed | |
572 | * that setting a line to 1 in this register will turn that line into an | |
573 | * output line. Conversely, setting the line to 0 will turn that line into | |
f69e00bd | 574 | * an input. |
d799a4de LW |
575 | * @dirin: MMIO address for the register to set this line as INPUT. It is assumed |
576 | * that setting a line to 1 in this register will turn that line into an | |
577 | * input line. Conversely, setting the line to 0 will turn that line into | |
f69e00bd | 578 | * an output. |
d799a4de LW |
579 | * @flags: Different flags that will affect the behaviour of the device, such as |
580 | * endianness etc. | |
581 | */ | |
0f4630f3 | 582 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
4f5b0480 RK |
583 | unsigned long sz, void __iomem *dat, void __iomem *set, |
584 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 585 | unsigned long flags) |
e027d6f9 | 586 | { |
e027d6f9 | 587 | int ret; |
e027d6f9 | 588 | |
280df6b3 JI |
589 | if (!is_power_of_2(sz)) |
590 | return -EINVAL; | |
e027d6f9 | 591 | |
0f4630f3 LW |
592 | gc->bgpio_bits = sz * 8; |
593 | if (gc->bgpio_bits > BITS_PER_LONG) | |
280df6b3 JI |
594 | return -EINVAL; |
595 | ||
0f4630f3 LW |
596 | spin_lock_init(&gc->bgpio_lock); |
597 | gc->parent = dev; | |
598 | gc->label = dev_name(dev); | |
599 | gc->base = -1; | |
600 | gc->ngpio = gc->bgpio_bits; | |
601 | gc->request = bgpio_request; | |
80057cb4 | 602 | gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); |
280df6b3 | 603 | |
0f4630f3 | 604 | ret = bgpio_setup_io(gc, dat, set, clr, flags); |
e027d6f9 JI |
605 | if (ret) |
606 | return ret; | |
aeec56e3 | 607 | |
24efd94b | 608 | ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
8467afec JI |
609 | if (ret) |
610 | return ret; | |
aeec56e3 | 611 | |
0f4630f3 | 612 | ret = bgpio_setup_direction(gc, dirout, dirin, flags); |
31029116 JI |
613 | if (ret) |
614 | return ret; | |
615 | ||
0f4630f3 LW |
616 | gc->bgpio_data = gc->read_reg(gc->reg_dat); |
617 | if (gc->set == bgpio_set_set && | |
3e11f7b8 | 618 | !(flags & BGPIOF_UNREADABLE_REG_SET)) |
0f4630f3 | 619 | gc->bgpio_data = gc->read_reg(gc->reg_set); |
f69e00bd LW |
620 | |
621 | if (flags & BGPIOF_UNREADABLE_REG_DIR) | |
622 | gc->bgpio_dir_unreadable = true; | |
623 | ||
624 | /* | |
625 | * Inspect hardware to find initial direction setting. | |
626 | */ | |
627 | if ((gc->reg_dir_out || gc->reg_dir_in) && | |
628 | !(flags & BGPIOF_UNREADABLE_REG_DIR)) { | |
629 | if (gc->reg_dir_out) | |
630 | gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); | |
631 | else if (gc->reg_dir_in) | |
632 | gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); | |
633 | /* | |
634 | * If we have two direction registers, synchronise | |
635 | * input setting to output setting, the library | |
636 | * can not handle a line being input and output at | |
637 | * the same time. | |
638 | */ | |
639 | if (gc->reg_dir_out && gc->reg_dir_in) | |
640 | gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); | |
641 | } | |
924e7a9f | 642 | |
280df6b3 JI |
643 | return ret; |
644 | } | |
645 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 646 | |
8f01c9d0 | 647 | #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) |
aeec56e3 | 648 | |
280df6b3 JI |
649 | static void __iomem *bgpio_map(struct platform_device *pdev, |
650 | const char *name, | |
8d240260 | 651 | resource_size_t sane_sz) |
280df6b3 | 652 | { |
280df6b3 | 653 | struct resource *r; |
280df6b3 | 654 | resource_size_t sz; |
280df6b3 JI |
655 | |
656 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
8d240260 | 657 | if (!r) |
b2f68b63 | 658 | return NULL; |
280df6b3 JI |
659 | |
660 | sz = resource_size(r); | |
8d240260 HK |
661 | if (sz != sane_sz) |
662 | return IOMEM_ERR_PTR(-EINVAL); | |
280df6b3 | 663 | |
8d240260 | 664 | return devm_ioremap_resource(&pdev->dev, r); |
aeec56e3 AV |
665 | } |
666 | ||
e698613a ÁFR |
667 | #ifdef CONFIG_OF |
668 | static const struct of_device_id bgpio_of_match[] = { | |
05cc995f | 669 | { .compatible = "brcm,bcm6345-gpio" }, |
c0d30ecf | 670 | { .compatible = "wd,mbl-gpio" }, |
b8c90199 | 671 | { .compatible = "ni,169445-nand-gpio" }, |
e698613a ÁFR |
672 | { } |
673 | }; | |
674 | MODULE_DEVICE_TABLE(of, bgpio_of_match); | |
675 | ||
676 | static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, | |
677 | unsigned long *flags) | |
678 | { | |
679 | struct bgpio_pdata *pdata; | |
680 | ||
681 | if (!of_match_device(bgpio_of_match, &pdev->dev)) | |
682 | return NULL; | |
683 | ||
684 | pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata), | |
685 | GFP_KERNEL); | |
686 | if (!pdata) | |
687 | return ERR_PTR(-ENOMEM); | |
688 | ||
689 | pdata->base = -1; | |
690 | ||
05cc995f CL |
691 | if (of_device_is_big_endian(pdev->dev.of_node)) |
692 | *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; | |
693 | ||
c0d30ecf CL |
694 | if (of_property_read_bool(pdev->dev.of_node, "no-output")) |
695 | *flags |= BGPIOF_NO_OUTPUT; | |
696 | ||
e698613a ÁFR |
697 | return pdata; |
698 | } | |
699 | #else | |
700 | static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, | |
701 | unsigned long *flags) | |
702 | { | |
703 | return NULL; | |
704 | } | |
705 | #endif /* CONFIG_OF */ | |
706 | ||
3836309d | 707 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
708 | { |
709 | struct device *dev = &pdev->dev; | |
710 | struct resource *r; | |
711 | void __iomem *dat; | |
712 | void __iomem *set; | |
713 | void __iomem *clr; | |
714 | void __iomem *dirout; | |
715 | void __iomem *dirin; | |
716 | unsigned long sz; | |
e698613a | 717 | unsigned long flags = 0; |
280df6b3 | 718 | int err; |
0f4630f3 | 719 | struct gpio_chip *gc; |
e698613a ÁFR |
720 | struct bgpio_pdata *pdata; |
721 | ||
722 | pdata = bgpio_parse_dt(pdev, &flags); | |
723 | if (IS_ERR(pdata)) | |
724 | return PTR_ERR(pdata); | |
725 | ||
726 | if (!pdata) { | |
727 | pdata = dev_get_platdata(dev); | |
728 | flags = pdev->id_entry->driver_data; | |
729 | } | |
280df6b3 JI |
730 | |
731 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
732 | if (!r) | |
733 | return -EINVAL; | |
734 | ||
735 | sz = resource_size(r); | |
736 | ||
8d240260 HK |
737 | dat = bgpio_map(pdev, "dat", sz); |
738 | if (IS_ERR(dat)) | |
739 | return PTR_ERR(dat); | |
280df6b3 | 740 | |
8d240260 HK |
741 | set = bgpio_map(pdev, "set", sz); |
742 | if (IS_ERR(set)) | |
743 | return PTR_ERR(set); | |
280df6b3 | 744 | |
8d240260 HK |
745 | clr = bgpio_map(pdev, "clr", sz); |
746 | if (IS_ERR(clr)) | |
747 | return PTR_ERR(clr); | |
280df6b3 | 748 | |
8d240260 HK |
749 | dirout = bgpio_map(pdev, "dirout", sz); |
750 | if (IS_ERR(dirout)) | |
751 | return PTR_ERR(dirout); | |
280df6b3 | 752 | |
8d240260 HK |
753 | dirin = bgpio_map(pdev, "dirin", sz); |
754 | if (IS_ERR(dirin)) | |
755 | return PTR_ERR(dirin); | |
280df6b3 | 756 | |
0f4630f3 LW |
757 | gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); |
758 | if (!gc) | |
280df6b3 JI |
759 | return -ENOMEM; |
760 | ||
0f4630f3 | 761 | err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
762 | if (err) |
763 | return err; | |
764 | ||
765 | if (pdata) { | |
781f6d71 | 766 | if (pdata->label) |
0f4630f3 LW |
767 | gc->label = pdata->label; |
768 | gc->base = pdata->base; | |
280df6b3 | 769 | if (pdata->ngpio > 0) |
0f4630f3 | 770 | gc->ngpio = pdata->ngpio; |
280df6b3 JI |
771 | } |
772 | ||
0f4630f3 | 773 | platform_set_drvdata(pdev, gc); |
280df6b3 | 774 | |
c05f813b | 775 | return devm_gpiochip_add_data(&pdev->dev, gc, NULL); |
aeec56e3 AV |
776 | } |
777 | ||
778 | static const struct platform_device_id bgpio_id_table[] = { | |
19338530 AS |
779 | { |
780 | .name = "basic-mmio-gpio", | |
781 | .driver_data = 0, | |
782 | }, { | |
783 | .name = "basic-mmio-gpio-be", | |
784 | .driver_data = BGPIOF_BIG_ENDIAN, | |
785 | }, | |
786 | { } | |
aeec56e3 AV |
787 | }; |
788 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
789 | ||
790 | static struct platform_driver bgpio_driver = { | |
791 | .driver = { | |
792 | .name = "basic-mmio-gpio", | |
e698613a | 793 | .of_match_table = of_match_ptr(bgpio_of_match), |
aeec56e3 AV |
794 | }, |
795 | .id_table = bgpio_id_table, | |
280df6b3 | 796 | .probe = bgpio_pdev_probe, |
aeec56e3 AV |
797 | }; |
798 | ||
6f61415e | 799 | module_platform_driver(bgpio_driver); |
280df6b3 | 800 | |
c103de24 | 801 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
802 | |
803 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
804 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
805 | MODULE_LICENSE("GPL"); |