Commit | Line | Data |
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dae5f0af | 1 | // SPDX-License-Identifier: GPL-2.0+ |
aeec56e3 | 2 | /* |
c103de24 | 3 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
4 | * |
5 | * Copyright 2008 MontaVista Software, Inc. | |
6 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
7 | * | |
aeec56e3 AV |
8 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... |
9 | * ...`` ```````.. | |
10 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
11 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
12 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
13 | * ````````` | |
14 | ___ | |
15 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
16 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
17 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
18 | `....trivial..'~`.```.``` | |
19 | * ``````` | |
20 | * .```````~~~~`..`.``.``. | |
21 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
22 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
23 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
24 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
25 | * ``.`.``...``` ```.. output pins are also supported.` | |
26 | * ^^ `````.`````````.,``~``~``~~`````` | |
27 | * . ^^ | |
28 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
29 | * .. The expectation is that in at least some cases . ,-~~~-, | |
30 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
31 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
32 | * ..````````......``````````` \o_ | |
33 | * | | |
34 | * ^^ / \ | |
35 | * | |
36 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
37 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
38 | * . the number of GPIOs is determined by the width of ~ | |
39 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
40 | * `.......````.``` | |
41 | */ | |
42 | ||
43 | #include <linux/init.h> | |
280df6b3 | 44 | #include <linux/err.h> |
aeec56e3 AV |
45 | #include <linux/bug.h> |
46 | #include <linux/kernel.h> | |
47 | #include <linux/module.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/compiler.h> | |
50 | #include <linux/types.h> | |
51 | #include <linux/errno.h> | |
52 | #include <linux/log2.h> | |
53 | #include <linux/ioport.h> | |
54 | #include <linux/io.h> | |
0f4630f3 | 55 | #include <linux/gpio/driver.h> |
aeec56e3 | 56 | #include <linux/slab.h> |
4b63739e | 57 | #include <linux/bitops.h> |
aeec56e3 AV |
58 | #include <linux/platform_device.h> |
59 | #include <linux/mod_devicetable.h> | |
e698613a ÁFR |
60 | #include <linux/of.h> |
61 | #include <linux/of_device.h> | |
aeec56e3 | 62 | |
8467afec | 63 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 64 | { |
fd996235 | 65 | writeb(data, reg); |
aeec56e3 AV |
66 | } |
67 | ||
8467afec | 68 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 69 | { |
fd996235 | 70 | return readb(reg); |
8467afec JI |
71 | } |
72 | ||
73 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
74 | { | |
fd996235 | 75 | writew(data, reg); |
8467afec JI |
76 | } |
77 | ||
78 | static unsigned long bgpio_read16(void __iomem *reg) | |
79 | { | |
fd996235 | 80 | return readw(reg); |
8467afec JI |
81 | } |
82 | ||
83 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
84 | { | |
fd996235 | 85 | writel(data, reg); |
8467afec JI |
86 | } |
87 | ||
88 | static unsigned long bgpio_read32(void __iomem *reg) | |
89 | { | |
fd996235 | 90 | return readl(reg); |
8467afec JI |
91 | } |
92 | ||
aeec56e3 | 93 | #if BITS_PER_LONG >= 64 |
8467afec JI |
94 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
95 | { | |
fd996235 | 96 | writeq(data, reg); |
8467afec JI |
97 | } |
98 | ||
99 | static unsigned long bgpio_read64(void __iomem *reg) | |
100 | { | |
fd996235 | 101 | return readq(reg); |
aeec56e3 | 102 | } |
8467afec | 103 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 | 104 | |
2b78f1e1 AL |
105 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
106 | { | |
107 | iowrite16be(data, reg); | |
108 | } | |
109 | ||
110 | static unsigned long bgpio_read16be(void __iomem *reg) | |
111 | { | |
112 | return ioread16be(reg); | |
113 | } | |
114 | ||
115 | static void bgpio_write32be(void __iomem *reg, unsigned long data) | |
116 | { | |
117 | iowrite32be(data, reg); | |
118 | } | |
119 | ||
120 | static unsigned long bgpio_read32be(void __iomem *reg) | |
121 | { | |
122 | return ioread32be(reg); | |
123 | } | |
124 | ||
24efd94b | 125 | static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) |
aeec56e3 | 126 | { |
24efd94b LW |
127 | if (gc->be_bits) |
128 | return BIT(gc->bgpio_bits - 1 - line); | |
129 | return BIT(line); | |
aeec56e3 AV |
130 | } |
131 | ||
b19e7f51 VZ |
132 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
133 | { | |
24efd94b | 134 | unsigned long pinmask = bgpio_line2mask(gc, gpio); |
d799a4de | 135 | bool dir = !!(gc->bgpio_dir & pinmask); |
b19e7f51 | 136 | |
d799a4de LW |
137 | /* |
138 | * If the direction is OUT we read the value from the SET | |
139 | * register, and if the direction is IN we read the value | |
140 | * from the DAT register. | |
141 | * | |
142 | * If the direction bits are inverted, naturally this gets | |
143 | * inverted too. | |
144 | */ | |
145 | if (gc->bgpio_dir_inverted) | |
146 | dir = !dir; | |
147 | ||
148 | if (dir) | |
0f4630f3 | 149 | return !!(gc->read_reg(gc->reg_set) & pinmask); |
b19e7f51 | 150 | else |
0f4630f3 | 151 | return !!(gc->read_reg(gc->reg_dat) & pinmask); |
b19e7f51 VZ |
152 | } |
153 | ||
80057cb4 LW |
154 | /* |
155 | * This assumes that the bits in the GPIO register are in native endianness. | |
156 | * We only assign the function pointer if we have that. | |
157 | */ | |
158 | static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
159 | unsigned long *bits) | |
160 | { | |
161 | unsigned long get_mask = 0; | |
162 | unsigned long set_mask = 0; | |
80057cb4 | 163 | |
07c7b6a5 LW |
164 | /* Make sure we first clear any bits that are zero when we read the register */ |
165 | *bits &= ~*mask; | |
166 | ||
167 | /* Exploit the fact that we know which directions are set */ | |
d799a4de LW |
168 | if (gc->bgpio_dir_inverted) { |
169 | set_mask = *mask & ~gc->bgpio_dir; | |
170 | get_mask = *mask & gc->bgpio_dir; | |
171 | } else { | |
172 | set_mask = *mask & gc->bgpio_dir; | |
173 | get_mask = *mask & ~gc->bgpio_dir; | |
174 | } | |
80057cb4 LW |
175 | |
176 | if (set_mask) | |
177 | *bits |= gc->read_reg(gc->reg_set) & set_mask; | |
178 | if (get_mask) | |
179 | *bits |= gc->read_reg(gc->reg_dat) & get_mask; | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
aeec56e3 AV |
184 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
185 | { | |
24efd94b | 186 | return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); |
aeec56e3 AV |
187 | } |
188 | ||
80057cb4 LW |
189 | /* |
190 | * This only works if the bits in the GPIO register are in native endianness. | |
80057cb4 LW |
191 | */ |
192 | static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, | |
193 | unsigned long *bits) | |
194 | { | |
07c7b6a5 LW |
195 | /* Make sure we first clear any bits that are zero when we read the register */ |
196 | *bits &= ~*mask; | |
197 | *bits |= gc->read_reg(gc->reg_dat) & *mask; | |
80057cb4 LW |
198 | return 0; |
199 | } | |
200 | ||
201 | /* | |
202 | * With big endian mirrored bit order it becomes more tedious. | |
203 | */ | |
204 | static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, | |
205 | unsigned long *bits) | |
206 | { | |
207 | unsigned long readmask = 0; | |
208 | unsigned long val; | |
209 | int bit; | |
210 | ||
07c7b6a5 LW |
211 | /* Make sure we first clear any bits that are zero when we read the register */ |
212 | *bits &= ~*mask; | |
213 | ||
80057cb4 | 214 | /* Create a mirrored mask */ |
07c7b6a5 LW |
215 | bit = -1; |
216 | while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio) | |
80057cb4 LW |
217 | readmask |= bgpio_line2mask(gc, bit); |
218 | ||
219 | /* Read the register */ | |
220 | val = gc->read_reg(gc->reg_dat) & readmask; | |
221 | ||
222 | /* | |
223 | * Mirror the result into the "bits" result, this will give line 0 | |
224 | * in bit 0 ... line 31 in bit 31 for a 32bit register. | |
225 | */ | |
07c7b6a5 LW |
226 | bit = -1; |
227 | while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio) | |
80057cb4 LW |
228 | *bits |= bgpio_line2mask(gc, bit); |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
91492a44 RV |
233 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
234 | { | |
235 | } | |
236 | ||
aeec56e3 AV |
237 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
238 | { | |
24efd94b | 239 | unsigned long mask = bgpio_line2mask(gc, gpio); |
aeec56e3 AV |
240 | unsigned long flags; |
241 | ||
0f4630f3 | 242 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
aeec56e3 AV |
243 | |
244 | if (val) | |
0f4630f3 | 245 | gc->bgpio_data |= mask; |
aeec56e3 | 246 | else |
0f4630f3 | 247 | gc->bgpio_data &= ~mask; |
aeec56e3 | 248 | |
0f4630f3 | 249 | gc->write_reg(gc->reg_dat, gc->bgpio_data); |
aeec56e3 | 250 | |
0f4630f3 | 251 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
aeec56e3 AV |
252 | } |
253 | ||
e027d6f9 JI |
254 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
255 | int val) | |
256 | { | |
24efd94b | 257 | unsigned long mask = bgpio_line2mask(gc, gpio); |
e027d6f9 JI |
258 | |
259 | if (val) | |
0f4630f3 | 260 | gc->write_reg(gc->reg_set, mask); |
e027d6f9 | 261 | else |
0f4630f3 | 262 | gc->write_reg(gc->reg_clr, mask); |
e027d6f9 JI |
263 | } |
264 | ||
dd86a0cc JI |
265 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
266 | { | |
24efd94b | 267 | unsigned long mask = bgpio_line2mask(gc, gpio); |
dd86a0cc JI |
268 | unsigned long flags; |
269 | ||
0f4630f3 | 270 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
dd86a0cc JI |
271 | |
272 | if (val) | |
0f4630f3 | 273 | gc->bgpio_data |= mask; |
dd86a0cc | 274 | else |
0f4630f3 | 275 | gc->bgpio_data &= ~mask; |
dd86a0cc | 276 | |
0f4630f3 | 277 | gc->write_reg(gc->reg_set, gc->bgpio_data); |
dd86a0cc | 278 | |
0f4630f3 | 279 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
dd86a0cc JI |
280 | } |
281 | ||
0f4630f3 | 282 | static void bgpio_multiple_get_masks(struct gpio_chip *gc, |
73c4ceda RI |
283 | unsigned long *mask, unsigned long *bits, |
284 | unsigned long *set_mask, | |
285 | unsigned long *clear_mask) | |
286 | { | |
287 | int i; | |
288 | ||
289 | *set_mask = 0; | |
290 | *clear_mask = 0; | |
291 | ||
0f4630f3 | 292 | for (i = 0; i < gc->bgpio_bits; i++) { |
73c4ceda RI |
293 | if (*mask == 0) |
294 | break; | |
295 | if (__test_and_clear_bit(i, mask)) { | |
296 | if (test_bit(i, bits)) | |
24efd94b | 297 | *set_mask |= bgpio_line2mask(gc, i); |
73c4ceda | 298 | else |
24efd94b | 299 | *clear_mask |= bgpio_line2mask(gc, i); |
73c4ceda RI |
300 | } |
301 | } | |
302 | } | |
303 | ||
0f4630f3 | 304 | static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, |
73c4ceda RI |
305 | unsigned long *mask, |
306 | unsigned long *bits, | |
307 | void __iomem *reg) | |
308 | { | |
309 | unsigned long flags; | |
310 | unsigned long set_mask, clear_mask; | |
311 | ||
0f4630f3 | 312 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
73c4ceda | 313 | |
0f4630f3 | 314 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda | 315 | |
0f4630f3 LW |
316 | gc->bgpio_data |= set_mask; |
317 | gc->bgpio_data &= ~clear_mask; | |
73c4ceda | 318 | |
0f4630f3 | 319 | gc->write_reg(reg, gc->bgpio_data); |
73c4ceda | 320 | |
0f4630f3 | 321 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
73c4ceda RI |
322 | } |
323 | ||
324 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
325 | unsigned long *bits) | |
326 | { | |
0f4630f3 | 327 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); |
73c4ceda RI |
328 | } |
329 | ||
330 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, | |
331 | unsigned long *bits) | |
332 | { | |
0f4630f3 | 333 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); |
73c4ceda RI |
334 | } |
335 | ||
336 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, | |
337 | unsigned long *mask, | |
338 | unsigned long *bits) | |
339 | { | |
73c4ceda RI |
340 | unsigned long set_mask, clear_mask; |
341 | ||
0f4630f3 | 342 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda RI |
343 | |
344 | if (set_mask) | |
0f4630f3 | 345 | gc->write_reg(gc->reg_set, set_mask); |
73c4ceda | 346 | if (clear_mask) |
0f4630f3 | 347 | gc->write_reg(gc->reg_clr, clear_mask); |
73c4ceda RI |
348 | } |
349 | ||
31029116 JI |
350 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
351 | { | |
352 | return 0; | |
353 | } | |
354 | ||
91492a44 RV |
355 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
356 | int val) | |
357 | { | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
31029116 JI |
361 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
362 | int val) | |
363 | { | |
364 | gc->set(gc, gpio, val); | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
aeec56e3 AV |
369 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
370 | { | |
31029116 JI |
371 | unsigned long flags; |
372 | ||
0f4630f3 | 373 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 374 | |
d799a4de LW |
375 | if (gc->bgpio_dir_inverted) |
376 | gc->bgpio_dir |= bgpio_line2mask(gc, gpio); | |
377 | else | |
378 | gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); | |
0f4630f3 | 379 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); |
31029116 | 380 | |
0f4630f3 | 381 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 382 | |
aeec56e3 AV |
383 | return 0; |
384 | } | |
385 | ||
db3b0fcc PZ |
386 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
387 | { | |
0f4630f3 | 388 | /* Return 0 if output, 1 of input */ |
d799a4de LW |
389 | if (gc->bgpio_dir_inverted) |
390 | return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio)); | |
391 | else | |
392 | return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio)); | |
db3b0fcc PZ |
393 | } |
394 | ||
aeec56e3 AV |
395 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
396 | { | |
31029116 JI |
397 | unsigned long flags; |
398 | ||
399 | gc->set(gc, gpio, val); | |
400 | ||
0f4630f3 | 401 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 402 | |
d799a4de LW |
403 | if (gc->bgpio_dir_inverted) |
404 | gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); | |
405 | else | |
406 | gc->bgpio_dir |= bgpio_line2mask(gc, gpio); | |
0f4630f3 | 407 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); |
31029116 | 408 | |
0f4630f3 | 409 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 410 | |
aeec56e3 AV |
411 | return 0; |
412 | } | |
413 | ||
280df6b3 | 414 | static int bgpio_setup_accessors(struct device *dev, |
0f4630f3 | 415 | struct gpio_chip *gc, |
2b78f1e1 | 416 | bool byte_be) |
aeec56e3 | 417 | { |
8467afec | 418 | |
0f4630f3 | 419 | switch (gc->bgpio_bits) { |
8467afec | 420 | case 8: |
0f4630f3 LW |
421 | gc->read_reg = bgpio_read8; |
422 | gc->write_reg = bgpio_write8; | |
8467afec JI |
423 | break; |
424 | case 16: | |
2b78f1e1 | 425 | if (byte_be) { |
0f4630f3 LW |
426 | gc->read_reg = bgpio_read16be; |
427 | gc->write_reg = bgpio_write16be; | |
2b78f1e1 | 428 | } else { |
0f4630f3 LW |
429 | gc->read_reg = bgpio_read16; |
430 | gc->write_reg = bgpio_write16; | |
2b78f1e1 | 431 | } |
8467afec JI |
432 | break; |
433 | case 32: | |
2b78f1e1 | 434 | if (byte_be) { |
0f4630f3 LW |
435 | gc->read_reg = bgpio_read32be; |
436 | gc->write_reg = bgpio_write32be; | |
2b78f1e1 | 437 | } else { |
0f4630f3 LW |
438 | gc->read_reg = bgpio_read32; |
439 | gc->write_reg = bgpio_write32; | |
2b78f1e1 | 440 | } |
8467afec JI |
441 | break; |
442 | #if BITS_PER_LONG >= 64 | |
443 | case 64: | |
2b78f1e1 AL |
444 | if (byte_be) { |
445 | dev_err(dev, | |
446 | "64 bit big endian byte order unsupported\n"); | |
447 | return -EINVAL; | |
448 | } else { | |
0f4630f3 LW |
449 | gc->read_reg = bgpio_read64; |
450 | gc->write_reg = bgpio_write64; | |
2b78f1e1 | 451 | } |
8467afec JI |
452 | break; |
453 | #endif /* BITS_PER_LONG >= 64 */ | |
454 | default: | |
0f4630f3 | 455 | dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); |
8467afec JI |
456 | return -EINVAL; |
457 | } | |
458 | ||
8467afec JI |
459 | return 0; |
460 | } | |
461 | ||
e027d6f9 JI |
462 | /* |
463 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 464 | * three supported configurations: |
e027d6f9 | 465 | * |
dd86a0cc | 466 | * - single input/output register resource (named "dat"). |
e027d6f9 | 467 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
468 | * - single output register resource and single input resource ("set" and |
469 | * dat"). | |
e027d6f9 JI |
470 | * |
471 | * For the single output register, this drives a 1 by setting a bit and a zero | |
472 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
473 | * in the set register and clears it by setting a bit in the clear register. | |
474 | * The configuration is detected by which resources are present. | |
31029116 JI |
475 | * |
476 | * For setting the GPIO direction, there are three supported configurations: | |
477 | * | |
478 | * - simple bidirection GPIO that requires no configuration. | |
479 | * - an output direction register (named "dirout") where a 1 bit | |
480 | * indicates the GPIO is an output. | |
481 | * - an input direction register (named "dirin") where a 1 bit indicates | |
482 | * the GPIO is an input. | |
e027d6f9 | 483 | */ |
0f4630f3 | 484 | static int bgpio_setup_io(struct gpio_chip *gc, |
280df6b3 JI |
485 | void __iomem *dat, |
486 | void __iomem *set, | |
b19e7f51 VZ |
487 | void __iomem *clr, |
488 | unsigned long flags) | |
8467afec | 489 | { |
aeec56e3 | 490 | |
0f4630f3 LW |
491 | gc->reg_dat = dat; |
492 | if (!gc->reg_dat) | |
280df6b3 | 493 | return -EINVAL; |
e027d6f9 | 494 | |
280df6b3 | 495 | if (set && clr) { |
0f4630f3 LW |
496 | gc->reg_set = set; |
497 | gc->reg_clr = clr; | |
498 | gc->set = bgpio_set_with_clear; | |
499 | gc->set_multiple = bgpio_set_multiple_with_clear; | |
280df6b3 | 500 | } else if (set && !clr) { |
0f4630f3 LW |
501 | gc->reg_set = set; |
502 | gc->set = bgpio_set_set; | |
503 | gc->set_multiple = bgpio_set_multiple_set; | |
91492a44 | 504 | } else if (flags & BGPIOF_NO_OUTPUT) { |
0f4630f3 LW |
505 | gc->set = bgpio_set_none; |
506 | gc->set_multiple = NULL; | |
e027d6f9 | 507 | } else { |
0f4630f3 LW |
508 | gc->set = bgpio_set; |
509 | gc->set_multiple = bgpio_set_multiple; | |
aeec56e3 AV |
510 | } |
511 | ||
b19e7f51 | 512 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
80057cb4 | 513 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) { |
0f4630f3 | 514 | gc->get = bgpio_get_set; |
80057cb4 LW |
515 | if (!gc->be_bits) |
516 | gc->get_multiple = bgpio_get_set_multiple; | |
517 | /* | |
518 | * We deliberately avoid assigning the ->get_multiple() call | |
519 | * for big endian mirrored registers which are ALSO reflecting | |
520 | * their value in the set register when used as output. It is | |
521 | * simply too much complexity, let the GPIO core fall back to | |
522 | * reading each line individually in that fringe case. | |
523 | */ | |
524 | } else { | |
0f4630f3 | 525 | gc->get = bgpio_get; |
80057cb4 LW |
526 | if (gc->be_bits) |
527 | gc->get_multiple = bgpio_get_multiple_be; | |
528 | else | |
529 | gc->get_multiple = bgpio_get_multiple; | |
530 | } | |
dd86a0cc | 531 | |
e027d6f9 JI |
532 | return 0; |
533 | } | |
534 | ||
0f4630f3 | 535 | static int bgpio_setup_direction(struct gpio_chip *gc, |
280df6b3 | 536 | void __iomem *dirout, |
91492a44 RV |
537 | void __iomem *dirin, |
538 | unsigned long flags) | |
31029116 | 539 | { |
280df6b3 | 540 | if (dirout && dirin) { |
31029116 | 541 | return -EINVAL; |
280df6b3 | 542 | } else if (dirout) { |
0f4630f3 LW |
543 | gc->reg_dir = dirout; |
544 | gc->direction_output = bgpio_dir_out; | |
545 | gc->direction_input = bgpio_dir_in; | |
546 | gc->get_direction = bgpio_get_dir; | |
280df6b3 | 547 | } else if (dirin) { |
0f4630f3 | 548 | gc->reg_dir = dirin; |
d799a4de LW |
549 | gc->direction_output = bgpio_dir_out; |
550 | gc->direction_input = bgpio_dir_in; | |
551 | gc->get_direction = bgpio_get_dir; | |
552 | gc->bgpio_dir_inverted = true; | |
31029116 | 553 | } else { |
91492a44 | 554 | if (flags & BGPIOF_NO_OUTPUT) |
0f4630f3 | 555 | gc->direction_output = bgpio_dir_out_err; |
91492a44 | 556 | else |
0f4630f3 LW |
557 | gc->direction_output = bgpio_simple_dir_out; |
558 | gc->direction_input = bgpio_simple_dir_in; | |
31029116 JI |
559 | } |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
7b42e3db AF |
564 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
565 | { | |
566 | if (gpio_pin < chip->ngpio) | |
567 | return 0; | |
568 | ||
569 | return -EINVAL; | |
570 | } | |
571 | ||
d799a4de LW |
572 | /** |
573 | * bgpio_init() - Initialize generic GPIO accessor functions | |
574 | * @gc: the GPIO chip to set up | |
575 | * @dev: the parent device of the new GPIO chip (compulsory) | |
576 | * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 | |
577 | * @dat: MMIO address for the register to READ the value of the GPIO lines, it | |
578 | * is expected that a 1 in the corresponding bit in this register means the | |
579 | * line is asserted | |
580 | * @set: MMIO address for the register to SET the value of the GPIO lines, it is | |
581 | * expected that we write the line with 1 in this register to drive the GPIO line | |
582 | * high. | |
583 | * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is | |
584 | * expected that we write the line with 1 in this register to drive the GPIO line | |
585 | * low. It is allowed to leave this address as NULL, in that case the SET register | |
586 | * will be assumed to also clear the GPIO lines, by actively writing the line | |
587 | * with 0. | |
588 | * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed | |
589 | * that setting a line to 1 in this register will turn that line into an | |
590 | * output line. Conversely, setting the line to 0 will turn that line into | |
591 | * an input. Either this or @dirin can be defined, but never both. | |
592 | * @dirin: MMIO address for the register to set this line as INPUT. It is assumed | |
593 | * that setting a line to 1 in this register will turn that line into an | |
594 | * input line. Conversely, setting the line to 0 will turn that line into | |
595 | * an output. Either this or @dirout can be defined, but never both. | |
596 | * @flags: Different flags that will affect the behaviour of the device, such as | |
597 | * endianness etc. | |
598 | */ | |
0f4630f3 | 599 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
4f5b0480 RK |
600 | unsigned long sz, void __iomem *dat, void __iomem *set, |
601 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 602 | unsigned long flags) |
e027d6f9 | 603 | { |
e027d6f9 | 604 | int ret; |
e027d6f9 | 605 | |
280df6b3 JI |
606 | if (!is_power_of_2(sz)) |
607 | return -EINVAL; | |
e027d6f9 | 608 | |
0f4630f3 LW |
609 | gc->bgpio_bits = sz * 8; |
610 | if (gc->bgpio_bits > BITS_PER_LONG) | |
280df6b3 JI |
611 | return -EINVAL; |
612 | ||
0f4630f3 LW |
613 | spin_lock_init(&gc->bgpio_lock); |
614 | gc->parent = dev; | |
615 | gc->label = dev_name(dev); | |
616 | gc->base = -1; | |
617 | gc->ngpio = gc->bgpio_bits; | |
618 | gc->request = bgpio_request; | |
80057cb4 | 619 | gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); |
280df6b3 | 620 | |
0f4630f3 | 621 | ret = bgpio_setup_io(gc, dat, set, clr, flags); |
e027d6f9 JI |
622 | if (ret) |
623 | return ret; | |
aeec56e3 | 624 | |
24efd94b | 625 | ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
8467afec JI |
626 | if (ret) |
627 | return ret; | |
aeec56e3 | 628 | |
0f4630f3 | 629 | ret = bgpio_setup_direction(gc, dirout, dirin, flags); |
31029116 JI |
630 | if (ret) |
631 | return ret; | |
632 | ||
0f4630f3 LW |
633 | gc->bgpio_data = gc->read_reg(gc->reg_dat); |
634 | if (gc->set == bgpio_set_set && | |
3e11f7b8 | 635 | !(flags & BGPIOF_UNREADABLE_REG_SET)) |
0f4630f3 LW |
636 | gc->bgpio_data = gc->read_reg(gc->reg_set); |
637 | if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) | |
638 | gc->bgpio_dir = gc->read_reg(gc->reg_dir); | |
924e7a9f | 639 | |
280df6b3 JI |
640 | return ret; |
641 | } | |
642 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 643 | |
8f01c9d0 | 644 | #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) |
aeec56e3 | 645 | |
280df6b3 JI |
646 | static void __iomem *bgpio_map(struct platform_device *pdev, |
647 | const char *name, | |
8d240260 | 648 | resource_size_t sane_sz) |
280df6b3 | 649 | { |
280df6b3 | 650 | struct resource *r; |
280df6b3 | 651 | resource_size_t sz; |
280df6b3 JI |
652 | |
653 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
8d240260 | 654 | if (!r) |
b2f68b63 | 655 | return NULL; |
280df6b3 JI |
656 | |
657 | sz = resource_size(r); | |
8d240260 HK |
658 | if (sz != sane_sz) |
659 | return IOMEM_ERR_PTR(-EINVAL); | |
280df6b3 | 660 | |
8d240260 | 661 | return devm_ioremap_resource(&pdev->dev, r); |
aeec56e3 AV |
662 | } |
663 | ||
e698613a ÁFR |
664 | #ifdef CONFIG_OF |
665 | static const struct of_device_id bgpio_of_match[] = { | |
05cc995f | 666 | { .compatible = "brcm,bcm6345-gpio" }, |
c0d30ecf | 667 | { .compatible = "wd,mbl-gpio" }, |
b8c90199 | 668 | { .compatible = "ni,169445-nand-gpio" }, |
e698613a ÁFR |
669 | { } |
670 | }; | |
671 | MODULE_DEVICE_TABLE(of, bgpio_of_match); | |
672 | ||
673 | static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, | |
674 | unsigned long *flags) | |
675 | { | |
676 | struct bgpio_pdata *pdata; | |
677 | ||
678 | if (!of_match_device(bgpio_of_match, &pdev->dev)) | |
679 | return NULL; | |
680 | ||
681 | pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata), | |
682 | GFP_KERNEL); | |
683 | if (!pdata) | |
684 | return ERR_PTR(-ENOMEM); | |
685 | ||
686 | pdata->base = -1; | |
687 | ||
05cc995f CL |
688 | if (of_device_is_big_endian(pdev->dev.of_node)) |
689 | *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; | |
690 | ||
c0d30ecf CL |
691 | if (of_property_read_bool(pdev->dev.of_node, "no-output")) |
692 | *flags |= BGPIOF_NO_OUTPUT; | |
693 | ||
e698613a ÁFR |
694 | return pdata; |
695 | } | |
696 | #else | |
697 | static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, | |
698 | unsigned long *flags) | |
699 | { | |
700 | return NULL; | |
701 | } | |
702 | #endif /* CONFIG_OF */ | |
703 | ||
3836309d | 704 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
705 | { |
706 | struct device *dev = &pdev->dev; | |
707 | struct resource *r; | |
708 | void __iomem *dat; | |
709 | void __iomem *set; | |
710 | void __iomem *clr; | |
711 | void __iomem *dirout; | |
712 | void __iomem *dirin; | |
713 | unsigned long sz; | |
e698613a | 714 | unsigned long flags = 0; |
280df6b3 | 715 | int err; |
0f4630f3 | 716 | struct gpio_chip *gc; |
e698613a ÁFR |
717 | struct bgpio_pdata *pdata; |
718 | ||
719 | pdata = bgpio_parse_dt(pdev, &flags); | |
720 | if (IS_ERR(pdata)) | |
721 | return PTR_ERR(pdata); | |
722 | ||
723 | if (!pdata) { | |
724 | pdata = dev_get_platdata(dev); | |
725 | flags = pdev->id_entry->driver_data; | |
726 | } | |
280df6b3 JI |
727 | |
728 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
729 | if (!r) | |
730 | return -EINVAL; | |
731 | ||
732 | sz = resource_size(r); | |
733 | ||
8d240260 HK |
734 | dat = bgpio_map(pdev, "dat", sz); |
735 | if (IS_ERR(dat)) | |
736 | return PTR_ERR(dat); | |
280df6b3 | 737 | |
8d240260 HK |
738 | set = bgpio_map(pdev, "set", sz); |
739 | if (IS_ERR(set)) | |
740 | return PTR_ERR(set); | |
280df6b3 | 741 | |
8d240260 HK |
742 | clr = bgpio_map(pdev, "clr", sz); |
743 | if (IS_ERR(clr)) | |
744 | return PTR_ERR(clr); | |
280df6b3 | 745 | |
8d240260 HK |
746 | dirout = bgpio_map(pdev, "dirout", sz); |
747 | if (IS_ERR(dirout)) | |
748 | return PTR_ERR(dirout); | |
280df6b3 | 749 | |
8d240260 HK |
750 | dirin = bgpio_map(pdev, "dirin", sz); |
751 | if (IS_ERR(dirin)) | |
752 | return PTR_ERR(dirin); | |
280df6b3 | 753 | |
0f4630f3 LW |
754 | gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); |
755 | if (!gc) | |
280df6b3 JI |
756 | return -ENOMEM; |
757 | ||
0f4630f3 | 758 | err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
759 | if (err) |
760 | return err; | |
761 | ||
762 | if (pdata) { | |
781f6d71 | 763 | if (pdata->label) |
0f4630f3 LW |
764 | gc->label = pdata->label; |
765 | gc->base = pdata->base; | |
280df6b3 | 766 | if (pdata->ngpio > 0) |
0f4630f3 | 767 | gc->ngpio = pdata->ngpio; |
280df6b3 JI |
768 | } |
769 | ||
0f4630f3 | 770 | platform_set_drvdata(pdev, gc); |
280df6b3 | 771 | |
c05f813b | 772 | return devm_gpiochip_add_data(&pdev->dev, gc, NULL); |
aeec56e3 AV |
773 | } |
774 | ||
775 | static const struct platform_device_id bgpio_id_table[] = { | |
19338530 AS |
776 | { |
777 | .name = "basic-mmio-gpio", | |
778 | .driver_data = 0, | |
779 | }, { | |
780 | .name = "basic-mmio-gpio-be", | |
781 | .driver_data = BGPIOF_BIG_ENDIAN, | |
782 | }, | |
783 | { } | |
aeec56e3 AV |
784 | }; |
785 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
786 | ||
787 | static struct platform_driver bgpio_driver = { | |
788 | .driver = { | |
789 | .name = "basic-mmio-gpio", | |
e698613a | 790 | .of_match_table = of_match_ptr(bgpio_of_match), |
aeec56e3 AV |
791 | }, |
792 | .id_table = bgpio_id_table, | |
280df6b3 | 793 | .probe = bgpio_pdev_probe, |
aeec56e3 AV |
794 | }; |
795 | ||
6f61415e | 796 | module_platform_driver(bgpio_driver); |
280df6b3 | 797 | |
c103de24 | 798 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
799 | |
800 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
801 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
802 | MODULE_LICENSE("GPL"); |