gpiolib: Fix comment referring to gpio_*() in gpiod_*()
[linux-2.6-block.git] / drivers / gpio / gpio-mcp23s08.c
CommitLineData
e58b9e27 1/*
4e47f91b
LP
2 * MCP23S08 SPI/I2C GPIO gpio expander driver
3 *
4 * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are
5 * supported.
6 * For the I2C versions of the chips (mcp23008 and mcp23017) generation of
7 * interrupts is also supported.
8 * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is
9 * also capable of generating interrupts, but the linux driver does not
10 * support that yet.
e58b9e27
DB
11 */
12
13#include <linux/kernel.h>
14#include <linux/device.h>
e58b9e27 15#include <linux/mutex.h>
bb207ef1 16#include <linux/module.h>
d120c17f 17#include <linux/gpio.h>
752ad5e8 18#include <linux/i2c.h>
e58b9e27
DB
19#include <linux/spi/spi.h>
20#include <linux/spi/mcp23s08.h>
5a0e3ad6 21#include <linux/slab.h>
0b7bb77f 22#include <asm/byteorder.h>
4e47f91b
LP
23#include <linux/interrupt.h>
24#include <linux/of_irq.h>
97ddb1c8 25#include <linux/of_device.h>
e58b9e27 26
0b7bb77f
PK
27/**
28 * MCP types supported by driver
29 */
30#define MCP_TYPE_S08 0
31#define MCP_TYPE_S17 1
752ad5e8
PK
32#define MCP_TYPE_008 2
33#define MCP_TYPE_017 3
28c5a41e 34#define MCP_TYPE_S18 4
e58b9e27
DB
35
36/* Registers are all 8 bits wide.
37 *
38 * The mcp23s17 has twice as many bits, and can be configured to work
39 * with either 16 bit registers or with two adjacent 8 bit banks.
e58b9e27
DB
40 */
41#define MCP_IODIR 0x00 /* init/reset: all ones */
42#define MCP_IPOL 0x01
43#define MCP_GPINTEN 0x02
44#define MCP_DEFVAL 0x03
45#define MCP_INTCON 0x04
46#define MCP_IOCON 0x05
4e47f91b 47# define IOCON_MIRROR (1 << 6)
e58b9e27
DB
48# define IOCON_SEQOP (1 << 5)
49# define IOCON_HAEN (1 << 3)
50# define IOCON_ODR (1 << 2)
51# define IOCON_INTPOL (1 << 1)
52#define MCP_GPPU 0x06
53#define MCP_INTF 0x07
54#define MCP_INTCAP 0x08
55#define MCP_GPIO 0x09
56#define MCP_OLAT 0x0a
57
0b7bb77f
PK
58struct mcp23s08;
59
60struct mcp23s08_ops {
61 int (*read)(struct mcp23s08 *mcp, unsigned reg);
62 int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val);
63 int (*read_regs)(struct mcp23s08 *mcp, unsigned reg,
64 u16 *vals, unsigned n);
65};
66
e58b9e27 67struct mcp23s08 {
e58b9e27 68 u8 addr;
a4e63554 69 bool irq_active_high;
e58b9e27 70
0b7bb77f 71 u16 cache[11];
4e47f91b
LP
72 u16 irq_rise;
73 u16 irq_fall;
74 int irq;
75 bool irq_controller;
e58b9e27
DB
76 /* lock protects the cached values */
77 struct mutex lock;
4e47f91b
LP
78 struct mutex irq_lock;
79 struct irq_domain *irq_domain;
e58b9e27
DB
80
81 struct gpio_chip chip;
82
0b7bb77f 83 const struct mcp23s08_ops *ops;
d62b98f3 84 void *data; /* ops specific data */
e58b9e27
DB
85};
86
0b7bb77f 87/* A given spi_device can represent up to eight mcp23sxx chips
8f1cc3b1
DB
88 * sharing the same chipselect but using different addresses
89 * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
90 * Driver data holds all the per-chip data.
91 */
92struct mcp23s08_driver_data {
93 unsigned ngpio;
0b7bb77f 94 struct mcp23s08 *mcp[8];
8f1cc3b1
DB
95 struct mcp23s08 chip[];
96};
97
4e47f91b
LP
98/* This lock class tells lockdep that GPIO irqs are in a different
99 * category than their parents, so it won't report false recursion.
100 */
101static struct lock_class_key gpio_lock_class;
102
752ad5e8
PK
103/*----------------------------------------------------------------------*/
104
cbf24fad 105#if IS_ENABLED(CONFIG_I2C)
752ad5e8
PK
106
107static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
108{
109 return i2c_smbus_read_byte_data(mcp->data, reg);
110}
111
112static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
113{
114 return i2c_smbus_write_byte_data(mcp->data, reg, val);
115}
116
117static int
118mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
119{
120 while (n--) {
121 int ret = mcp23008_read(mcp, reg++);
122 if (ret < 0)
123 return ret;
124 *vals++ = ret;
125 }
126
127 return 0;
128}
129
130static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg)
131{
132 return i2c_smbus_read_word_data(mcp->data, reg << 1);
133}
134
135static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
136{
137 return i2c_smbus_write_word_data(mcp->data, reg << 1, val);
138}
139
140static int
141mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
142{
143 while (n--) {
144 int ret = mcp23017_read(mcp, reg++);
145 if (ret < 0)
146 return ret;
147 *vals++ = ret;
148 }
149
150 return 0;
151}
152
153static const struct mcp23s08_ops mcp23008_ops = {
154 .read = mcp23008_read,
155 .write = mcp23008_write,
156 .read_regs = mcp23008_read_regs,
157};
158
159static const struct mcp23s08_ops mcp23017_ops = {
160 .read = mcp23017_read,
161 .write = mcp23017_write,
162 .read_regs = mcp23017_read_regs,
163};
164
165#endif /* CONFIG_I2C */
166
167/*----------------------------------------------------------------------*/
168
d62b98f3
PK
169#ifdef CONFIG_SPI_MASTER
170
e58b9e27
DB
171static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
172{
173 u8 tx[2], rx[1];
174 int status;
175
176 tx[0] = mcp->addr | 0x01;
177 tx[1] = reg;
33bc8411 178 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
e58b9e27
DB
179 return (status < 0) ? status : rx[0];
180}
181
0b7bb77f 182static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
e58b9e27
DB
183{
184 u8 tx[3];
185
186 tx[0] = mcp->addr;
187 tx[1] = reg;
188 tx[2] = val;
33bc8411 189 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
e58b9e27
DB
190}
191
192static int
0b7bb77f 193mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
e58b9e27 194{
0b7bb77f
PK
195 u8 tx[2], *tmp;
196 int status;
e58b9e27 197
33bc8411 198 if ((n + reg) > sizeof(mcp->cache))
e58b9e27
DB
199 return -EINVAL;
200 tx[0] = mcp->addr | 0x01;
201 tx[1] = reg;
0b7bb77f
PK
202
203 tmp = (u8 *)vals;
33bc8411 204 status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n);
0b7bb77f
PK
205 if (status >= 0) {
206 while (n--)
207 vals[n] = tmp[n]; /* expand to 16bit */
208 }
209 return status;
210}
211
212static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
213{
214 u8 tx[2], rx[2];
215 int status;
216
217 tx[0] = mcp->addr | 0x01;
218 tx[1] = reg << 1;
33bc8411 219 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
0b7bb77f
PK
220 return (status < 0) ? status : (rx[0] | (rx[1] << 8));
221}
222
223static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
224{
225 u8 tx[4];
226
227 tx[0] = mcp->addr;
228 tx[1] = reg << 1;
229 tx[2] = val;
230 tx[3] = val >> 8;
33bc8411 231 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
0b7bb77f
PK
232}
233
234static int
235mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
236{
237 u8 tx[2];
238 int status;
239
33bc8411 240 if ((n + reg) > sizeof(mcp->cache))
0b7bb77f
PK
241 return -EINVAL;
242 tx[0] = mcp->addr | 0x01;
243 tx[1] = reg << 1;
244
33bc8411 245 status = spi_write_then_read(mcp->data, tx, sizeof(tx),
0b7bb77f
PK
246 (u8 *)vals, n * 2);
247 if (status >= 0) {
248 while (n--)
249 vals[n] = __le16_to_cpu((__le16)vals[n]);
250 }
251
252 return status;
e58b9e27
DB
253}
254
0b7bb77f
PK
255static const struct mcp23s08_ops mcp23s08_ops = {
256 .read = mcp23s08_read,
257 .write = mcp23s08_write,
258 .read_regs = mcp23s08_read_regs,
259};
260
261static const struct mcp23s08_ops mcp23s17_ops = {
262 .read = mcp23s17_read,
263 .write = mcp23s17_write,
264 .read_regs = mcp23s17_read_regs,
265};
266
d62b98f3 267#endif /* CONFIG_SPI_MASTER */
0b7bb77f 268
e58b9e27
DB
269/*----------------------------------------------------------------------*/
270
271static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
272{
9e03cf0b 273 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
274 int status;
275
276 mutex_lock(&mcp->lock);
277 mcp->cache[MCP_IODIR] |= (1 << offset);
0b7bb77f 278 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
279 mutex_unlock(&mcp->lock);
280 return status;
281}
282
283static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
284{
9e03cf0b 285 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
286 int status;
287
288 mutex_lock(&mcp->lock);
289
290 /* REVISIT reading this clears any IRQ ... */
0b7bb77f 291 status = mcp->ops->read(mcp, MCP_GPIO);
e58b9e27
DB
292 if (status < 0)
293 status = 0;
294 else {
295 mcp->cache[MCP_GPIO] = status;
296 status = !!(status & (1 << offset));
297 }
298 mutex_unlock(&mcp->lock);
299 return status;
300}
301
302static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
303{
0b7bb77f 304 unsigned olat = mcp->cache[MCP_OLAT];
e58b9e27
DB
305
306 if (value)
307 olat |= mask;
308 else
309 olat &= ~mask;
310 mcp->cache[MCP_OLAT] = olat;
0b7bb77f 311 return mcp->ops->write(mcp, MCP_OLAT, olat);
e58b9e27
DB
312}
313
314static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
315{
9e03cf0b 316 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 317 unsigned mask = 1 << offset;
e58b9e27
DB
318
319 mutex_lock(&mcp->lock);
320 __mcp23s08_set(mcp, mask, value);
321 mutex_unlock(&mcp->lock);
322}
323
324static int
325mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
326{
9e03cf0b 327 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 328 unsigned mask = 1 << offset;
e58b9e27
DB
329 int status;
330
331 mutex_lock(&mcp->lock);
332 status = __mcp23s08_set(mcp, mask, value);
333 if (status == 0) {
334 mcp->cache[MCP_IODIR] &= ~mask;
0b7bb77f 335 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
336 }
337 mutex_unlock(&mcp->lock);
338 return status;
339}
340
4e47f91b
LP
341/*----------------------------------------------------------------------*/
342static irqreturn_t mcp23s08_irq(int irq, void *data)
343{
344 struct mcp23s08 *mcp = data;
345 int intcap, intf, i;
346 unsigned int child_irq;
347
348 mutex_lock(&mcp->lock);
349 intf = mcp->ops->read(mcp, MCP_INTF);
350 if (intf < 0) {
351 mutex_unlock(&mcp->lock);
352 return IRQ_HANDLED;
353 }
354
355 mcp->cache[MCP_INTF] = intf;
356
357 intcap = mcp->ops->read(mcp, MCP_INTCAP);
358 if (intcap < 0) {
359 mutex_unlock(&mcp->lock);
360 return IRQ_HANDLED;
361 }
362
363 mcp->cache[MCP_INTCAP] = intcap;
364 mutex_unlock(&mcp->lock);
365
366
367 for (i = 0; i < mcp->chip.ngpio; i++) {
368 if ((BIT(i) & mcp->cache[MCP_INTF]) &&
369 ((BIT(i) & intcap & mcp->irq_rise) ||
370 (mcp->irq_fall & ~intcap & BIT(i)))) {
371 child_irq = irq_find_mapping(mcp->irq_domain, i);
372 handle_nested_irq(child_irq);
373 }
374 }
375
376 return IRQ_HANDLED;
377}
378
379static int mcp23s08_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
380{
9e03cf0b 381 struct mcp23s08 *mcp = gpiochip_get_data(chip);
4e47f91b
LP
382
383 return irq_find_mapping(mcp->irq_domain, offset);
384}
385
386static void mcp23s08_irq_mask(struct irq_data *data)
387{
388 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
389 unsigned int pos = data->hwirq;
390
391 mcp->cache[MCP_GPINTEN] &= ~BIT(pos);
392}
393
394static void mcp23s08_irq_unmask(struct irq_data *data)
395{
396 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
397 unsigned int pos = data->hwirq;
398
399 mcp->cache[MCP_GPINTEN] |= BIT(pos);
400}
401
402static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
403{
404 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
405 unsigned int pos = data->hwirq;
406 int status = 0;
407
408 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
409 mcp->cache[MCP_INTCON] &= ~BIT(pos);
410 mcp->irq_rise |= BIT(pos);
411 mcp->irq_fall |= BIT(pos);
412 } else if (type & IRQ_TYPE_EDGE_RISING) {
413 mcp->cache[MCP_INTCON] &= ~BIT(pos);
414 mcp->irq_rise |= BIT(pos);
415 mcp->irq_fall &= ~BIT(pos);
416 } else if (type & IRQ_TYPE_EDGE_FALLING) {
417 mcp->cache[MCP_INTCON] &= ~BIT(pos);
418 mcp->irq_rise &= ~BIT(pos);
419 mcp->irq_fall |= BIT(pos);
420 } else
421 return -EINVAL;
422
423 return status;
424}
425
426static void mcp23s08_irq_bus_lock(struct irq_data *data)
427{
428 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
429
430 mutex_lock(&mcp->irq_lock);
431}
432
433static void mcp23s08_irq_bus_unlock(struct irq_data *data)
434{
435 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
436
437 mutex_lock(&mcp->lock);
438 mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]);
439 mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]);
440 mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]);
441 mutex_unlock(&mcp->lock);
442 mutex_unlock(&mcp->irq_lock);
443}
444
57ef0428 445static int mcp23s08_irq_reqres(struct irq_data *data)
4e47f91b
LP
446{
447 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
448
e3a2e878 449 if (gpiochip_lock_as_irq(&mcp->chip, data->hwirq)) {
58383c78 450 dev_err(mcp->chip.parent,
4e47f91b
LP
451 "unable to lock HW IRQ %lu for IRQ usage\n",
452 data->hwirq);
57ef0428
LW
453 return -EINVAL;
454 }
4e47f91b 455
4e47f91b
LP
456 return 0;
457}
458
57ef0428 459static void mcp23s08_irq_relres(struct irq_data *data)
4e47f91b
LP
460{
461 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
462
e3a2e878 463 gpiochip_unlock_as_irq(&mcp->chip, data->hwirq);
4e47f91b
LP
464}
465
466static struct irq_chip mcp23s08_irq_chip = {
467 .name = "gpio-mcp23xxx",
468 .irq_mask = mcp23s08_irq_mask,
469 .irq_unmask = mcp23s08_irq_unmask,
470 .irq_set_type = mcp23s08_irq_set_type,
471 .irq_bus_lock = mcp23s08_irq_bus_lock,
472 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
57ef0428
LW
473 .irq_request_resources = mcp23s08_irq_reqres,
474 .irq_release_resources = mcp23s08_irq_relres,
4e47f91b
LP
475};
476
477static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
478{
479 struct gpio_chip *chip = &mcp->chip;
480 int err, irq, j;
a4e63554 481 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
4e47f91b
LP
482
483 mutex_init(&mcp->irq_lock);
484
58383c78
LW
485 mcp->irq_domain = irq_domain_add_linear(chip->parent->of_node,
486 chip->ngpio,
4e47f91b
LP
487 &irq_domain_simple_ops, mcp);
488 if (!mcp->irq_domain)
489 return -ENODEV;
490
a4e63554
AS
491 if (mcp->irq_active_high)
492 irqflags |= IRQF_TRIGGER_HIGH;
493 else
494 irqflags |= IRQF_TRIGGER_LOW;
495
58383c78
LW
496 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
497 mcp23s08_irq,
498 irqflags, dev_name(chip->parent), mcp);
4e47f91b 499 if (err != 0) {
58383c78 500 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
4e47f91b
LP
501 mcp->irq, err);
502 return err;
503 }
504
505 chip->to_irq = mcp23s08_gpio_to_irq;
506
507 for (j = 0; j < mcp->chip.ngpio; j++) {
508 irq = irq_create_mapping(mcp->irq_domain, j);
509 irq_set_lockdep_class(irq, &gpio_lock_class);
510 irq_set_chip_data(irq, mcp);
511 irq_set_chip(irq, &mcp23s08_irq_chip);
512 irq_set_nested_thread(irq, true);
4e47f91b 513 irq_set_noprobe(irq);
4e47f91b
LP
514 }
515 return 0;
516}
517
518static void mcp23s08_irq_teardown(struct mcp23s08 *mcp)
519{
520 unsigned int irq, i;
521
4e47f91b
LP
522 for (i = 0; i < mcp->chip.ngpio; i++) {
523 irq = irq_find_mapping(mcp->irq_domain, i);
524 if (irq > 0)
525 irq_dispose_mapping(irq);
526 }
527
528 irq_domain_remove(mcp->irq_domain);
529}
530
e58b9e27
DB
531/*----------------------------------------------------------------------*/
532
533#ifdef CONFIG_DEBUG_FS
534
535#include <linux/seq_file.h>
536
537/*
538 * This shows more info than the generic gpio dump code:
539 * pullups, deglitching, open drain drive.
540 */
541static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
542{
543 struct mcp23s08 *mcp;
544 char bank;
1d1c1d9b 545 int t;
e58b9e27
DB
546 unsigned mask;
547
9e03cf0b 548 mcp = gpiochip_get_data(chip);
e58b9e27
DB
549
550 /* NOTE: we only handle one bank for now ... */
0b7bb77f 551 bank = '0' + ((mcp->addr >> 1) & 0x7);
e58b9e27
DB
552
553 mutex_lock(&mcp->lock);
0b7bb77f 554 t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
e58b9e27
DB
555 if (t < 0) {
556 seq_printf(s, " I/O ERROR %d\n", t);
557 goto done;
558 }
559
0b7bb77f 560 for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
e58b9e27
DB
561 const char *label;
562
563 label = gpiochip_is_requested(chip, t);
564 if (!label)
565 continue;
566
567 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s",
568 chip->base + t, bank, t, label,
569 (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
570 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
eb1567f7 571 (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
e58b9e27 572 /* NOTE: ignoring the irq-related registers */
33bc8411 573 seq_puts(s, "\n");
e58b9e27
DB
574 }
575done:
576 mutex_unlock(&mcp->lock);
577}
578
579#else
580#define mcp23s08_dbg_show NULL
581#endif
582
583/*----------------------------------------------------------------------*/
584
d62b98f3 585static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
4e47f91b 586 void *data, unsigned addr, unsigned type,
3af0dbd5 587 struct mcp23s08_platform_data *pdata, int cs)
e58b9e27 588{
d62b98f3 589 int status;
4e47f91b 590 bool mirror = false;
e58b9e27 591
e58b9e27
DB
592 mutex_init(&mcp->lock);
593
d62b98f3
PK
594 mcp->data = data;
595 mcp->addr = addr;
a4e63554 596 mcp->irq_active_high = false;
e58b9e27 597
e58b9e27
DB
598 mcp->chip.direction_input = mcp23s08_direction_input;
599 mcp->chip.get = mcp23s08_get;
600 mcp->chip.direction_output = mcp23s08_direction_output;
601 mcp->chip.set = mcp23s08_set;
602 mcp->chip.dbg_show = mcp23s08_dbg_show;
97ddb1c8
LP
603#ifdef CONFIG_OF
604 mcp->chip.of_gpio_n_cells = 2;
605 mcp->chip.of_node = dev->of_node;
606#endif
e58b9e27 607
d62b98f3
PK
608 switch (type) {
609#ifdef CONFIG_SPI_MASTER
610 case MCP_TYPE_S08:
0b7bb77f
PK
611 mcp->ops = &mcp23s08_ops;
612 mcp->chip.ngpio = 8;
613 mcp->chip.label = "mcp23s08";
d62b98f3
PK
614 break;
615
616 case MCP_TYPE_S17:
617 mcp->ops = &mcp23s17_ops;
618 mcp->chip.ngpio = 16;
619 mcp->chip.label = "mcp23s17";
620 break;
28c5a41e
PR
621
622 case MCP_TYPE_S18:
623 mcp->ops = &mcp23s17_ops;
624 mcp->chip.ngpio = 16;
625 mcp->chip.label = "mcp23s18";
626 break;
d62b98f3
PK
627#endif /* CONFIG_SPI_MASTER */
628
cbf24fad 629#if IS_ENABLED(CONFIG_I2C)
752ad5e8
PK
630 case MCP_TYPE_008:
631 mcp->ops = &mcp23008_ops;
632 mcp->chip.ngpio = 8;
633 mcp->chip.label = "mcp23008";
634 break;
635
636 case MCP_TYPE_017:
637 mcp->ops = &mcp23017_ops;
638 mcp->chip.ngpio = 16;
639 mcp->chip.label = "mcp23017";
640 break;
641#endif /* CONFIG_I2C */
642
d62b98f3
PK
643 default:
644 dev_err(dev, "invalid device type (%d)\n", type);
645 return -EINVAL;
0b7bb77f 646 }
d62b98f3 647
3af0dbd5 648 mcp->chip.base = pdata->base;
9fb1f39e 649 mcp->chip.can_sleep = true;
58383c78 650 mcp->chip.parent = dev;
d72cbed0 651 mcp->chip.owner = THIS_MODULE;
e58b9e27 652
8f1cc3b1
DB
653 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
654 * and MCP_IOCON.HAEN = 1, so we work with all chips.
655 */
4e47f91b 656
0b7bb77f 657 status = mcp->ops->read(mcp, MCP_IOCON);
e58b9e27
DB
658 if (status < 0)
659 goto fail;
4e47f91b 660
3af0dbd5 661 mcp->irq_controller = pdata->irq_controller;
a4e63554 662 if (mcp->irq && mcp->irq_controller) {
170680ab 663 mcp->irq_active_high =
58383c78 664 of_property_read_bool(mcp->chip.parent->of_node,
170680ab 665 "microchip,irq-active-high");
4e47f91b 666
28c5a41e 667 mirror = pdata->mirror;
a4e63554
AS
668 }
669
670 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
671 mcp->irq_active_high) {
0b7bb77f
PK
672 /* mcp23s17 has IOCON twice, make sure they are in sync */
673 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
674 status |= IOCON_HAEN | (IOCON_HAEN << 8);
a4e63554
AS
675 if (mcp->irq_active_high)
676 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
677 else
678 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
679
4e47f91b
LP
680 if (mirror)
681 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
682
0b7bb77f 683 status = mcp->ops->write(mcp, MCP_IOCON, status);
e58b9e27
DB
684 if (status < 0)
685 goto fail;
686 }
687
688 /* configure ~100K pullups */
3af0dbd5 689 status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups);
e58b9e27
DB
690 if (status < 0)
691 goto fail;
692
0b7bb77f 693 status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
e58b9e27
DB
694 if (status < 0)
695 goto fail;
696
697 /* disable inverter on input */
698 if (mcp->cache[MCP_IPOL] != 0) {
699 mcp->cache[MCP_IPOL] = 0;
0b7bb77f
PK
700 status = mcp->ops->write(mcp, MCP_IPOL, 0);
701 if (status < 0)
702 goto fail;
e58b9e27
DB
703 }
704
705 /* disable irqs */
706 if (mcp->cache[MCP_GPINTEN] != 0) {
707 mcp->cache[MCP_GPINTEN] = 0;
0b7bb77f 708 status = mcp->ops->write(mcp, MCP_GPINTEN, 0);
8f1cc3b1
DB
709 if (status < 0)
710 goto fail;
e58b9e27
DB
711 }
712
9e03cf0b 713 status = gpiochip_add_data(&mcp->chip, mcp);
4e47f91b
LP
714 if (status < 0)
715 goto fail;
716
717 if (mcp->irq && mcp->irq_controller) {
718 status = mcp23s08_irq_setup(mcp);
719 if (status) {
720 mcp23s08_irq_teardown(mcp);
721 goto fail;
722 }
723 }
8f1cc3b1
DB
724fail:
725 if (status < 0)
d62b98f3
PK
726 dev_dbg(dev, "can't setup chip %d, --> %d\n",
727 addr, status);
8f1cc3b1
DB
728 return status;
729}
730
752ad5e8
PK
731/*----------------------------------------------------------------------*/
732
97ddb1c8
LP
733#ifdef CONFIG_OF
734#ifdef CONFIG_SPI_MASTER
ac791804 735static const struct of_device_id mcp23s08_spi_of_match[] = {
97ddb1c8 736 {
45971686
LP
737 .compatible = "microchip,mcp23s08",
738 .data = (void *) MCP_TYPE_S08,
97ddb1c8
LP
739 },
740 {
45971686
LP
741 .compatible = "microchip,mcp23s17",
742 .data = (void *) MCP_TYPE_S17,
743 },
28c5a41e
PR
744 {
745 .compatible = "microchip,mcp23s18",
746 .data = (void *) MCP_TYPE_S18,
747 },
45971686
LP
748/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
749 {
750 .compatible = "mcp,mcp23s08",
751 .data = (void *) MCP_TYPE_S08,
752 },
753 {
754 .compatible = "mcp,mcp23s17",
755 .data = (void *) MCP_TYPE_S17,
97ddb1c8
LP
756 },
757 { },
758};
759MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
760#endif
761
762#if IS_ENABLED(CONFIG_I2C)
ac791804 763static const struct of_device_id mcp23s08_i2c_of_match[] = {
97ddb1c8 764 {
45971686
LP
765 .compatible = "microchip,mcp23008",
766 .data = (void *) MCP_TYPE_008,
97ddb1c8
LP
767 },
768 {
45971686
LP
769 .compatible = "microchip,mcp23017",
770 .data = (void *) MCP_TYPE_017,
771 },
772/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
773 {
774 .compatible = "mcp,mcp23008",
775 .data = (void *) MCP_TYPE_008,
776 },
777 {
778 .compatible = "mcp,mcp23017",
779 .data = (void *) MCP_TYPE_017,
97ddb1c8
LP
780 },
781 { },
782};
783MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
784#endif
785#endif /* CONFIG_OF */
786
787
cbf24fad 788#if IS_ENABLED(CONFIG_I2C)
752ad5e8 789
3836309d 790static int mcp230xx_probe(struct i2c_client *client,
752ad5e8
PK
791 const struct i2c_device_id *id)
792{
3af0dbd5 793 struct mcp23s08_platform_data *pdata, local_pdata;
752ad5e8 794 struct mcp23s08 *mcp;
3af0dbd5 795 int status;
97ddb1c8
LP
796 const struct of_device_id *match;
797
798 match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match),
799 &client->dev);
3af0dbd5
SZ
800 if (match) {
801 pdata = &local_pdata;
802 pdata->base = -1;
803 pdata->chip[0].pullups = 0;
804 pdata->irq_controller = of_property_read_bool(
805 client->dev.of_node,
806 "interrupt-controller");
807 pdata->mirror = of_property_read_bool(client->dev.of_node,
808 "microchip,irq-mirror");
4e47f91b 809 client->irq = irq_of_parse_and_map(client->dev.of_node, 0);
97ddb1c8 810 } else {
3af0dbd5 811 pdata = dev_get_platdata(&client->dev);
b184c388
SZ
812 if (!pdata) {
813 pdata = devm_kzalloc(&client->dev,
814 sizeof(struct mcp23s08_platform_data),
815 GFP_KERNEL);
aaf2b3af
IY
816 if (!pdata)
817 return -ENOMEM;
b184c388 818 pdata->base = -1;
97ddb1c8 819 }
752ad5e8
PK
820 }
821
33bc8411 822 mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
752ad5e8
PK
823 if (!mcp)
824 return -ENOMEM;
825
4e47f91b 826 mcp->irq = client->irq;
752ad5e8 827 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
3af0dbd5 828 id->driver_data, pdata, 0);
752ad5e8
PK
829 if (status)
830 goto fail;
831
832 i2c_set_clientdata(client, mcp);
833
834 return 0;
835
836fail:
837 kfree(mcp);
838
839 return status;
840}
841
206210ce 842static int mcp230xx_remove(struct i2c_client *client)
752ad5e8
PK
843{
844 struct mcp23s08 *mcp = i2c_get_clientdata(client);
752ad5e8 845
4e47f91b
LP
846 if (client->irq && mcp->irq_controller)
847 mcp23s08_irq_teardown(mcp);
848
9f5132ae 849 gpiochip_remove(&mcp->chip);
850 kfree(mcp);
752ad5e8 851
9f5132ae 852 return 0;
752ad5e8
PK
853}
854
855static const struct i2c_device_id mcp230xx_id[] = {
856 { "mcp23008", MCP_TYPE_008 },
857 { "mcp23017", MCP_TYPE_017 },
858 { },
859};
860MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
861
862static struct i2c_driver mcp230xx_driver = {
863 .driver = {
864 .name = "mcp230xx",
97ddb1c8 865 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
752ad5e8
PK
866 },
867 .probe = mcp230xx_probe,
8283c4ff 868 .remove = mcp230xx_remove,
752ad5e8
PK
869 .id_table = mcp230xx_id,
870};
871
872static int __init mcp23s08_i2c_init(void)
873{
874 return i2c_add_driver(&mcp230xx_driver);
875}
876
877static void mcp23s08_i2c_exit(void)
878{
879 i2c_del_driver(&mcp230xx_driver);
880}
881
882#else
883
884static int __init mcp23s08_i2c_init(void) { return 0; }
885static void mcp23s08_i2c_exit(void) { }
886
887#endif /* CONFIG_I2C */
888
889/*----------------------------------------------------------------------*/
890
d62b98f3
PK
891#ifdef CONFIG_SPI_MASTER
892
8f1cc3b1
DB
893static int mcp23s08_probe(struct spi_device *spi)
894{
3af0dbd5 895 struct mcp23s08_platform_data *pdata, local_pdata;
8f1cc3b1 896 unsigned addr;
596a1c5f 897 int chips = 0;
8f1cc3b1 898 struct mcp23s08_driver_data *data;
0b7bb77f 899 int status, type;
3af0dbd5 900 unsigned ngpio = 0;
97ddb1c8
LP
901 const struct of_device_id *match;
902 u32 spi_present_mask = 0;
903
904 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
905 if (match) {
de755c33 906 type = (int)(uintptr_t)match->data;
97ddb1c8 907 status = of_property_read_u32(spi->dev.of_node,
45971686 908 "microchip,spi-present-mask", &spi_present_mask);
97ddb1c8 909 if (status) {
45971686
LP
910 status = of_property_read_u32(spi->dev.of_node,
911 "mcp,spi-present-mask", &spi_present_mask);
912 if (status) {
913 dev_err(&spi->dev,
914 "DT has no spi-present-mask\n");
915 return -ENODEV;
916 }
97ddb1c8
LP
917 }
918 if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) {
919 dev_err(&spi->dev, "invalid spi-present-mask\n");
920 return -ENODEV;
921 }
8f1cc3b1 922
3af0dbd5
SZ
923 pdata = &local_pdata;
924 pdata->base = -1;
99e4b98d 925 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
3af0dbd5 926 pdata->chip[addr].pullups = 0;
3e3bed91
MS
927 if (spi_present_mask & (1 << addr))
928 chips++;
99e4b98d 929 }
3af0dbd5
SZ
930 pdata->irq_controller = of_property_read_bool(
931 spi->dev.of_node,
932 "interrupt-controller");
933 pdata->mirror = of_property_read_bool(spi->dev.of_node,
934 "microchip,irq-mirror");
97ddb1c8
LP
935 } else {
936 type = spi_get_device_id(spi)->driver_data;
e56aee18 937 pdata = dev_get_platdata(&spi->dev);
b184c388
SZ
938 if (!pdata) {
939 pdata = devm_kzalloc(&spi->dev,
940 sizeof(struct mcp23s08_platform_data),
941 GFP_KERNEL);
942 pdata->base = -1;
0b7bb77f 943 }
97ddb1c8
LP
944
945 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
946 if (!pdata->chip[addr].is_present)
947 continue;
948 chips++;
949 if ((type == MCP_TYPE_S08) && (addr > 3)) {
950 dev_err(&spi->dev,
951 "mcp23s08 only supports address 0..3\n");
952 return -EINVAL;
953 }
954 spi_present_mask |= 1 << addr;
97ddb1c8 955 }
8f1cc3b1 956 }
8f1cc3b1 957
99e4b98d
MW
958 if (!chips)
959 return -ENODEV;
960
7898b31e
VB
961 data = devm_kzalloc(&spi->dev,
962 sizeof(*data) + chips * sizeof(struct mcp23s08),
963 GFP_KERNEL);
8f1cc3b1
DB
964 if (!data)
965 return -ENOMEM;
7898b31e 966
8f1cc3b1
DB
967 spi_set_drvdata(spi, data);
968
a231b88c
AS
969 spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
970
0b7bb77f 971 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
97ddb1c8 972 if (!(spi_present_mask & (1 << addr)))
8f1cc3b1
DB
973 continue;
974 chips--;
975 data->mcp[addr] = &data->chip[chips];
a231b88c 976 data->mcp[addr]->irq = spi->irq;
d62b98f3 977 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
3af0dbd5
SZ
978 0x40 | (addr << 1), type, pdata,
979 addr);
8f1cc3b1
DB
980 if (status < 0)
981 goto fail;
0b7bb77f 982
3af0dbd5 983 if (pdata->base != -1)
28c5a41e
PR
984 pdata->base += data->mcp[addr]->chip.ngpio;
985 ngpio += data->mcp[addr]->chip.ngpio;
8f1cc3b1 986 }
97ddb1c8 987 data->ngpio = ngpio;
e58b9e27
DB
988
989 /* NOTE: these chips have a relatively sane IRQ framework, with
990 * per-signal masking and level/edge triggering. It's not yet
991 * handled here...
992 */
993
e58b9e27
DB
994 return 0;
995
996fail:
0b7bb77f 997 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
998
999 if (!data->mcp[addr])
1000 continue;
9f5132ae 1001 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 1002 }
e58b9e27
DB
1003 return status;
1004}
1005
1006static int mcp23s08_remove(struct spi_device *spi)
1007{
8f1cc3b1 1008 struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
8f1cc3b1 1009 unsigned addr;
e58b9e27 1010
0b7bb77f 1011 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
1012
1013 if (!data->mcp[addr])
1014 continue;
1015
a231b88c
AS
1016 if (spi->irq && data->mcp[addr]->irq_controller)
1017 mcp23s08_irq_teardown(data->mcp[addr]);
9f5132ae 1018 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 1019 }
c4941e07 1020
9f5132ae 1021 return 0;
e58b9e27
DB
1022}
1023
0b7bb77f
PK
1024static const struct spi_device_id mcp23s08_ids[] = {
1025 { "mcp23s08", MCP_TYPE_S08 },
1026 { "mcp23s17", MCP_TYPE_S17 },
28c5a41e 1027 { "mcp23s18", MCP_TYPE_S18 },
0b7bb77f
PK
1028 { },
1029};
1030MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
1031
e58b9e27
DB
1032static struct spi_driver mcp23s08_driver = {
1033 .probe = mcp23s08_probe,
1034 .remove = mcp23s08_remove,
0b7bb77f 1035 .id_table = mcp23s08_ids,
e58b9e27
DB
1036 .driver = {
1037 .name = "mcp23s08",
97ddb1c8 1038 .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
e58b9e27
DB
1039 },
1040};
1041
d62b98f3
PK
1042static int __init mcp23s08_spi_init(void)
1043{
1044 return spi_register_driver(&mcp23s08_driver);
1045}
1046
1047static void mcp23s08_spi_exit(void)
1048{
1049 spi_unregister_driver(&mcp23s08_driver);
1050}
1051
1052#else
1053
1054static int __init mcp23s08_spi_init(void) { return 0; }
1055static void mcp23s08_spi_exit(void) { }
1056
1057#endif /* CONFIG_SPI_MASTER */
1058
e58b9e27
DB
1059/*----------------------------------------------------------------------*/
1060
1061static int __init mcp23s08_init(void)
1062{
752ad5e8
PK
1063 int ret;
1064
1065 ret = mcp23s08_spi_init();
1066 if (ret)
1067 goto spi_fail;
1068
1069 ret = mcp23s08_i2c_init();
1070 if (ret)
1071 goto i2c_fail;
1072
1073 return 0;
1074
1075 i2c_fail:
1076 mcp23s08_spi_exit();
1077 spi_fail:
1078 return ret;
e58b9e27 1079}
752ad5e8 1080/* register after spi/i2c postcore initcall and before
673c0c00
DB
1081 * subsys initcalls that may rely on these GPIOs
1082 */
1083subsys_initcall(mcp23s08_init);
e58b9e27
DB
1084
1085static void __exit mcp23s08_exit(void)
1086{
d62b98f3 1087 mcp23s08_spi_exit();
752ad5e8 1088 mcp23s08_i2c_exit();
e58b9e27
DB
1089}
1090module_exit(mcp23s08_exit);
1091
1092MODULE_LICENSE("GPL");