Commit | Line | Data |
---|---|---|
e58b9e27 | 1 | /* |
4e47f91b LP |
2 | * MCP23S08 SPI/I2C GPIO gpio expander driver |
3 | * | |
4 | * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are | |
5 | * supported. | |
6 | * For the I2C versions of the chips (mcp23008 and mcp23017) generation of | |
7 | * interrupts is also supported. | |
8 | * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is | |
9 | * also capable of generating interrupts, but the linux driver does not | |
10 | * support that yet. | |
e58b9e27 DB |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/device.h> | |
e58b9e27 | 15 | #include <linux/mutex.h> |
bb207ef1 | 16 | #include <linux/module.h> |
d120c17f | 17 | #include <linux/gpio.h> |
752ad5e8 | 18 | #include <linux/i2c.h> |
e58b9e27 DB |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0b7bb77f | 22 | #include <asm/byteorder.h> |
4e47f91b LP |
23 | #include <linux/interrupt.h> |
24 | #include <linux/of_irq.h> | |
97ddb1c8 | 25 | #include <linux/of_device.h> |
e58b9e27 | 26 | |
0b7bb77f PK |
27 | /** |
28 | * MCP types supported by driver | |
29 | */ | |
30 | #define MCP_TYPE_S08 0 | |
31 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
32 | #define MCP_TYPE_008 2 |
33 | #define MCP_TYPE_017 3 | |
28c5a41e | 34 | #define MCP_TYPE_S18 4 |
e58b9e27 DB |
35 | |
36 | /* Registers are all 8 bits wide. | |
37 | * | |
38 | * The mcp23s17 has twice as many bits, and can be configured to work | |
39 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
40 | */ |
41 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
42 | #define MCP_IPOL 0x01 | |
43 | #define MCP_GPINTEN 0x02 | |
44 | #define MCP_DEFVAL 0x03 | |
45 | #define MCP_INTCON 0x04 | |
46 | #define MCP_IOCON 0x05 | |
4e47f91b | 47 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
48 | # define IOCON_SEQOP (1 << 5) |
49 | # define IOCON_HAEN (1 << 3) | |
50 | # define IOCON_ODR (1 << 2) | |
51 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 52 | # define IOCON_INTCC (1) |
e58b9e27 DB |
53 | #define MCP_GPPU 0x06 |
54 | #define MCP_INTF 0x07 | |
55 | #define MCP_INTCAP 0x08 | |
56 | #define MCP_GPIO 0x09 | |
57 | #define MCP_OLAT 0x0a | |
58 | ||
0b7bb77f PK |
59 | struct mcp23s08; |
60 | ||
61 | struct mcp23s08_ops { | |
62 | int (*read)(struct mcp23s08 *mcp, unsigned reg); | |
63 | int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val); | |
64 | int (*read_regs)(struct mcp23s08 *mcp, unsigned reg, | |
65 | u16 *vals, unsigned n); | |
66 | }; | |
67 | ||
e58b9e27 | 68 | struct mcp23s08 { |
e58b9e27 | 69 | u8 addr; |
a4e63554 | 70 | bool irq_active_high; |
e58b9e27 | 71 | |
0b7bb77f | 72 | u16 cache[11]; |
4e47f91b LP |
73 | u16 irq_rise; |
74 | u16 irq_fall; | |
75 | int irq; | |
76 | bool irq_controller; | |
e58b9e27 DB |
77 | /* lock protects the cached values */ |
78 | struct mutex lock; | |
4e47f91b | 79 | struct mutex irq_lock; |
e58b9e27 DB |
80 | |
81 | struct gpio_chip chip; | |
82 | ||
0b7bb77f | 83 | const struct mcp23s08_ops *ops; |
d62b98f3 | 84 | void *data; /* ops specific data */ |
e58b9e27 DB |
85 | }; |
86 | ||
0b7bb77f | 87 | /* A given spi_device can represent up to eight mcp23sxx chips |
8f1cc3b1 DB |
88 | * sharing the same chipselect but using different addresses |
89 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
90 | * Driver data holds all the per-chip data. | |
91 | */ | |
92 | struct mcp23s08_driver_data { | |
93 | unsigned ngpio; | |
0b7bb77f | 94 | struct mcp23s08 *mcp[8]; |
8f1cc3b1 DB |
95 | struct mcp23s08 chip[]; |
96 | }; | |
97 | ||
752ad5e8 PK |
98 | /*----------------------------------------------------------------------*/ |
99 | ||
cbf24fad | 100 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 PK |
101 | |
102 | static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg) | |
103 | { | |
104 | return i2c_smbus_read_byte_data(mcp->data, reg); | |
105 | } | |
106 | ||
107 | static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
108 | { | |
109 | return i2c_smbus_write_byte_data(mcp->data, reg, val); | |
110 | } | |
111 | ||
112 | static int | |
113 | mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
114 | { | |
115 | while (n--) { | |
116 | int ret = mcp23008_read(mcp, reg++); | |
117 | if (ret < 0) | |
118 | return ret; | |
119 | *vals++ = ret; | |
120 | } | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg) | |
126 | { | |
127 | return i2c_smbus_read_word_data(mcp->data, reg << 1); | |
128 | } | |
129 | ||
130 | static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
131 | { | |
132 | return i2c_smbus_write_word_data(mcp->data, reg << 1, val); | |
133 | } | |
134 | ||
135 | static int | |
136 | mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
137 | { | |
138 | while (n--) { | |
139 | int ret = mcp23017_read(mcp, reg++); | |
140 | if (ret < 0) | |
141 | return ret; | |
142 | *vals++ = ret; | |
143 | } | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static const struct mcp23s08_ops mcp23008_ops = { | |
149 | .read = mcp23008_read, | |
150 | .write = mcp23008_write, | |
151 | .read_regs = mcp23008_read_regs, | |
152 | }; | |
153 | ||
154 | static const struct mcp23s08_ops mcp23017_ops = { | |
155 | .read = mcp23017_read, | |
156 | .write = mcp23017_write, | |
157 | .read_regs = mcp23017_read_regs, | |
158 | }; | |
159 | ||
160 | #endif /* CONFIG_I2C */ | |
161 | ||
162 | /*----------------------------------------------------------------------*/ | |
163 | ||
d62b98f3 PK |
164 | #ifdef CONFIG_SPI_MASTER |
165 | ||
e58b9e27 DB |
166 | static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg) |
167 | { | |
168 | u8 tx[2], rx[1]; | |
169 | int status; | |
170 | ||
171 | tx[0] = mcp->addr | 0x01; | |
172 | tx[1] = reg; | |
33bc8411 | 173 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx)); |
e58b9e27 DB |
174 | return (status < 0) ? status : rx[0]; |
175 | } | |
176 | ||
0b7bb77f | 177 | static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) |
e58b9e27 DB |
178 | { |
179 | u8 tx[3]; | |
180 | ||
181 | tx[0] = mcp->addr; | |
182 | tx[1] = reg; | |
183 | tx[2] = val; | |
33bc8411 | 184 | return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0); |
e58b9e27 DB |
185 | } |
186 | ||
187 | static int | |
0b7bb77f | 188 | mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) |
e58b9e27 | 189 | { |
0b7bb77f PK |
190 | u8 tx[2], *tmp; |
191 | int status; | |
e58b9e27 | 192 | |
33bc8411 | 193 | if ((n + reg) > sizeof(mcp->cache)) |
e58b9e27 DB |
194 | return -EINVAL; |
195 | tx[0] = mcp->addr | 0x01; | |
196 | tx[1] = reg; | |
0b7bb77f PK |
197 | |
198 | tmp = (u8 *)vals; | |
33bc8411 | 199 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n); |
0b7bb77f PK |
200 | if (status >= 0) { |
201 | while (n--) | |
202 | vals[n] = tmp[n]; /* expand to 16bit */ | |
203 | } | |
204 | return status; | |
205 | } | |
206 | ||
207 | static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg) | |
208 | { | |
209 | u8 tx[2], rx[2]; | |
210 | int status; | |
211 | ||
212 | tx[0] = mcp->addr | 0x01; | |
213 | tx[1] = reg << 1; | |
33bc8411 | 214 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx)); |
0b7bb77f PK |
215 | return (status < 0) ? status : (rx[0] | (rx[1] << 8)); |
216 | } | |
217 | ||
218 | static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
219 | { | |
220 | u8 tx[4]; | |
221 | ||
222 | tx[0] = mcp->addr; | |
223 | tx[1] = reg << 1; | |
224 | tx[2] = val; | |
225 | tx[3] = val >> 8; | |
33bc8411 | 226 | return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0); |
0b7bb77f PK |
227 | } |
228 | ||
229 | static int | |
230 | mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
231 | { | |
232 | u8 tx[2]; | |
233 | int status; | |
234 | ||
33bc8411 | 235 | if ((n + reg) > sizeof(mcp->cache)) |
0b7bb77f PK |
236 | return -EINVAL; |
237 | tx[0] = mcp->addr | 0x01; | |
238 | tx[1] = reg << 1; | |
239 | ||
33bc8411 | 240 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), |
0b7bb77f PK |
241 | (u8 *)vals, n * 2); |
242 | if (status >= 0) { | |
243 | while (n--) | |
244 | vals[n] = __le16_to_cpu((__le16)vals[n]); | |
245 | } | |
246 | ||
247 | return status; | |
e58b9e27 DB |
248 | } |
249 | ||
0b7bb77f PK |
250 | static const struct mcp23s08_ops mcp23s08_ops = { |
251 | .read = mcp23s08_read, | |
252 | .write = mcp23s08_write, | |
253 | .read_regs = mcp23s08_read_regs, | |
254 | }; | |
255 | ||
256 | static const struct mcp23s08_ops mcp23s17_ops = { | |
257 | .read = mcp23s17_read, | |
258 | .write = mcp23s17_write, | |
259 | .read_regs = mcp23s17_read_regs, | |
260 | }; | |
261 | ||
d62b98f3 | 262 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 263 | |
e58b9e27 DB |
264 | /*----------------------------------------------------------------------*/ |
265 | ||
266 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
267 | { | |
9e03cf0b | 268 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
269 | int status; |
270 | ||
271 | mutex_lock(&mcp->lock); | |
272 | mcp->cache[MCP_IODIR] |= (1 << offset); | |
0b7bb77f | 273 | status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
274 | mutex_unlock(&mcp->lock); |
275 | return status; | |
276 | } | |
277 | ||
278 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
279 | { | |
9e03cf0b | 280 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
281 | int status; |
282 | ||
283 | mutex_lock(&mcp->lock); | |
284 | ||
285 | /* REVISIT reading this clears any IRQ ... */ | |
0b7bb77f | 286 | status = mcp->ops->read(mcp, MCP_GPIO); |
e58b9e27 DB |
287 | if (status < 0) |
288 | status = 0; | |
289 | else { | |
290 | mcp->cache[MCP_GPIO] = status; | |
291 | status = !!(status & (1 << offset)); | |
292 | } | |
293 | mutex_unlock(&mcp->lock); | |
294 | return status; | |
295 | } | |
296 | ||
297 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value) | |
298 | { | |
0b7bb77f | 299 | unsigned olat = mcp->cache[MCP_OLAT]; |
e58b9e27 DB |
300 | |
301 | if (value) | |
302 | olat |= mask; | |
303 | else | |
304 | olat &= ~mask; | |
305 | mcp->cache[MCP_OLAT] = olat; | |
0b7bb77f | 306 | return mcp->ops->write(mcp, MCP_OLAT, olat); |
e58b9e27 DB |
307 | } |
308 | ||
309 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
310 | { | |
9e03cf0b | 311 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
0b7bb77f | 312 | unsigned mask = 1 << offset; |
e58b9e27 DB |
313 | |
314 | mutex_lock(&mcp->lock); | |
315 | __mcp23s08_set(mcp, mask, value); | |
316 | mutex_unlock(&mcp->lock); | |
317 | } | |
318 | ||
319 | static int | |
320 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
321 | { | |
9e03cf0b | 322 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
0b7bb77f | 323 | unsigned mask = 1 << offset; |
e58b9e27 DB |
324 | int status; |
325 | ||
326 | mutex_lock(&mcp->lock); | |
327 | status = __mcp23s08_set(mcp, mask, value); | |
328 | if (status == 0) { | |
329 | mcp->cache[MCP_IODIR] &= ~mask; | |
0b7bb77f | 330 | status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
331 | } |
332 | mutex_unlock(&mcp->lock); | |
333 | return status; | |
334 | } | |
335 | ||
4e47f91b LP |
336 | /*----------------------------------------------------------------------*/ |
337 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
338 | { | |
339 | struct mcp23s08 *mcp = data; | |
340 | int intcap, intf, i; | |
341 | unsigned int child_irq; | |
342 | ||
343 | mutex_lock(&mcp->lock); | |
344 | intf = mcp->ops->read(mcp, MCP_INTF); | |
345 | if (intf < 0) { | |
346 | mutex_unlock(&mcp->lock); | |
347 | return IRQ_HANDLED; | |
348 | } | |
349 | ||
350 | mcp->cache[MCP_INTF] = intf; | |
351 | ||
352 | intcap = mcp->ops->read(mcp, MCP_INTCAP); | |
353 | if (intcap < 0) { | |
354 | mutex_unlock(&mcp->lock); | |
355 | return IRQ_HANDLED; | |
356 | } | |
357 | ||
358 | mcp->cache[MCP_INTCAP] = intcap; | |
359 | mutex_unlock(&mcp->lock); | |
360 | ||
361 | ||
362 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
363 | if ((BIT(i) & mcp->cache[MCP_INTF]) && | |
364 | ((BIT(i) & intcap & mcp->irq_rise) || | |
365 | (mcp->irq_fall & ~intcap & BIT(i)))) { | |
dad3d272 | 366 | child_irq = irq_find_mapping(mcp->chip.irqdomain, i); |
4e47f91b LP |
367 | handle_nested_irq(child_irq); |
368 | } | |
369 | } | |
370 | ||
371 | return IRQ_HANDLED; | |
372 | } | |
373 | ||
4e47f91b LP |
374 | static void mcp23s08_irq_mask(struct irq_data *data) |
375 | { | |
dad3d272 PR |
376 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
377 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
378 | unsigned int pos = data->hwirq; |
379 | ||
380 | mcp->cache[MCP_GPINTEN] &= ~BIT(pos); | |
381 | } | |
382 | ||
383 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
384 | { | |
dad3d272 PR |
385 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
386 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
387 | unsigned int pos = data->hwirq; |
388 | ||
389 | mcp->cache[MCP_GPINTEN] |= BIT(pos); | |
390 | } | |
391 | ||
392 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
393 | { | |
dad3d272 PR |
394 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
395 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
396 | unsigned int pos = data->hwirq; |
397 | int status = 0; | |
398 | ||
399 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
400 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
401 | mcp->irq_rise |= BIT(pos); | |
402 | mcp->irq_fall |= BIT(pos); | |
403 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
404 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
405 | mcp->irq_rise |= BIT(pos); | |
406 | mcp->irq_fall &= ~BIT(pos); | |
407 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
408 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
409 | mcp->irq_rise &= ~BIT(pos); | |
410 | mcp->irq_fall |= BIT(pos); | |
411 | } else | |
412 | return -EINVAL; | |
413 | ||
414 | return status; | |
415 | } | |
416 | ||
417 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
418 | { | |
dad3d272 PR |
419 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
420 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
421 | |
422 | mutex_lock(&mcp->irq_lock); | |
423 | } | |
424 | ||
425 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
426 | { | |
dad3d272 PR |
427 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
428 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
429 | |
430 | mutex_lock(&mcp->lock); | |
431 | mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]); | |
432 | mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]); | |
433 | mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]); | |
434 | mutex_unlock(&mcp->lock); | |
435 | mutex_unlock(&mcp->irq_lock); | |
436 | } | |
437 | ||
4e47f91b LP |
438 | static struct irq_chip mcp23s08_irq_chip = { |
439 | .name = "gpio-mcp23xxx", | |
440 | .irq_mask = mcp23s08_irq_mask, | |
441 | .irq_unmask = mcp23s08_irq_unmask, | |
442 | .irq_set_type = mcp23s08_irq_set_type, | |
443 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
444 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
4e47f91b LP |
445 | }; |
446 | ||
447 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
448 | { | |
449 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 450 | int err; |
a4e63554 | 451 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b LP |
452 | |
453 | mutex_init(&mcp->irq_lock); | |
454 | ||
a4e63554 AS |
455 | if (mcp->irq_active_high) |
456 | irqflags |= IRQF_TRIGGER_HIGH; | |
457 | else | |
458 | irqflags |= IRQF_TRIGGER_LOW; | |
459 | ||
58383c78 LW |
460 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
461 | mcp23s08_irq, | |
462 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 463 | if (err != 0) { |
58383c78 | 464 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
465 | mcp->irq, err); |
466 | return err; | |
467 | } | |
468 | ||
dad3d272 PR |
469 | err = gpiochip_irqchip_add(chip, |
470 | &mcp23s08_irq_chip, | |
471 | 0, | |
472 | handle_simple_irq, | |
473 | IRQ_TYPE_NONE); | |
474 | if (err) { | |
475 | dev_err(chip->parent, | |
476 | "could not connect irqchip to gpiochip: %d\n", err); | |
477 | return err; | |
4e47f91b | 478 | } |
4e47f91b | 479 | |
dad3d272 PR |
480 | gpiochip_set_chained_irqchip(chip, |
481 | &mcp23s08_irq_chip, | |
482 | mcp->irq, | |
483 | NULL); | |
4e47f91b | 484 | |
dad3d272 | 485 | return 0; |
4e47f91b LP |
486 | } |
487 | ||
e58b9e27 DB |
488 | /*----------------------------------------------------------------------*/ |
489 | ||
490 | #ifdef CONFIG_DEBUG_FS | |
491 | ||
492 | #include <linux/seq_file.h> | |
493 | ||
494 | /* | |
495 | * This shows more info than the generic gpio dump code: | |
496 | * pullups, deglitching, open drain drive. | |
497 | */ | |
498 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
499 | { | |
500 | struct mcp23s08 *mcp; | |
501 | char bank; | |
1d1c1d9b | 502 | int t; |
e58b9e27 DB |
503 | unsigned mask; |
504 | ||
9e03cf0b | 505 | mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
506 | |
507 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 508 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
509 | |
510 | mutex_lock(&mcp->lock); | |
0b7bb77f | 511 | t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache)); |
e58b9e27 DB |
512 | if (t < 0) { |
513 | seq_printf(s, " I/O ERROR %d\n", t); | |
514 | goto done; | |
515 | } | |
516 | ||
0b7bb77f | 517 | for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) { |
e58b9e27 DB |
518 | const char *label; |
519 | ||
520 | label = gpiochip_is_requested(chip, t); | |
521 | if (!label) | |
522 | continue; | |
523 | ||
524 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
525 | chip->base + t, bank, t, label, | |
526 | (mcp->cache[MCP_IODIR] & mask) ? "in " : "out", | |
527 | (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", | |
eb1567f7 | 528 | (mcp->cache[MCP_GPPU] & mask) ? "up" : " "); |
e58b9e27 | 529 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 530 | seq_puts(s, "\n"); |
e58b9e27 DB |
531 | } |
532 | done: | |
533 | mutex_unlock(&mcp->lock); | |
534 | } | |
535 | ||
536 | #else | |
537 | #define mcp23s08_dbg_show NULL | |
538 | #endif | |
539 | ||
540 | /*----------------------------------------------------------------------*/ | |
541 | ||
d62b98f3 | 542 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 543 | void *data, unsigned addr, unsigned type, |
3af0dbd5 | 544 | struct mcp23s08_platform_data *pdata, int cs) |
e58b9e27 | 545 | { |
d62b98f3 | 546 | int status; |
4e47f91b | 547 | bool mirror = false; |
e58b9e27 | 548 | |
e58b9e27 DB |
549 | mutex_init(&mcp->lock); |
550 | ||
d62b98f3 PK |
551 | mcp->data = data; |
552 | mcp->addr = addr; | |
a4e63554 | 553 | mcp->irq_active_high = false; |
e58b9e27 | 554 | |
e58b9e27 DB |
555 | mcp->chip.direction_input = mcp23s08_direction_input; |
556 | mcp->chip.get = mcp23s08_get; | |
557 | mcp->chip.direction_output = mcp23s08_direction_output; | |
558 | mcp->chip.set = mcp23s08_set; | |
559 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
97ddb1c8 LP |
560 | #ifdef CONFIG_OF |
561 | mcp->chip.of_gpio_n_cells = 2; | |
562 | mcp->chip.of_node = dev->of_node; | |
563 | #endif | |
e58b9e27 | 564 | |
d62b98f3 PK |
565 | switch (type) { |
566 | #ifdef CONFIG_SPI_MASTER | |
567 | case MCP_TYPE_S08: | |
0b7bb77f PK |
568 | mcp->ops = &mcp23s08_ops; |
569 | mcp->chip.ngpio = 8; | |
570 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
571 | break; |
572 | ||
573 | case MCP_TYPE_S17: | |
574 | mcp->ops = &mcp23s17_ops; | |
575 | mcp->chip.ngpio = 16; | |
576 | mcp->chip.label = "mcp23s17"; | |
577 | break; | |
28c5a41e PR |
578 | |
579 | case MCP_TYPE_S18: | |
580 | mcp->ops = &mcp23s17_ops; | |
581 | mcp->chip.ngpio = 16; | |
582 | mcp->chip.label = "mcp23s18"; | |
583 | break; | |
d62b98f3 PK |
584 | #endif /* CONFIG_SPI_MASTER */ |
585 | ||
cbf24fad | 586 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 PK |
587 | case MCP_TYPE_008: |
588 | mcp->ops = &mcp23008_ops; | |
589 | mcp->chip.ngpio = 8; | |
590 | mcp->chip.label = "mcp23008"; | |
591 | break; | |
592 | ||
593 | case MCP_TYPE_017: | |
594 | mcp->ops = &mcp23017_ops; | |
595 | mcp->chip.ngpio = 16; | |
596 | mcp->chip.label = "mcp23017"; | |
597 | break; | |
598 | #endif /* CONFIG_I2C */ | |
599 | ||
d62b98f3 PK |
600 | default: |
601 | dev_err(dev, "invalid device type (%d)\n", type); | |
602 | return -EINVAL; | |
0b7bb77f | 603 | } |
d62b98f3 | 604 | |
3af0dbd5 | 605 | mcp->chip.base = pdata->base; |
9fb1f39e | 606 | mcp->chip.can_sleep = true; |
58383c78 | 607 | mcp->chip.parent = dev; |
d72cbed0 | 608 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 609 | |
8f1cc3b1 DB |
610 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
611 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
612 | */ | |
4e47f91b | 613 | |
0b7bb77f | 614 | status = mcp->ops->read(mcp, MCP_IOCON); |
e58b9e27 DB |
615 | if (status < 0) |
616 | goto fail; | |
4e47f91b | 617 | |
3af0dbd5 | 618 | mcp->irq_controller = pdata->irq_controller; |
a4e63554 | 619 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 620 | mcp->irq_active_high = |
58383c78 | 621 | of_property_read_bool(mcp->chip.parent->of_node, |
170680ab | 622 | "microchip,irq-active-high"); |
4e47f91b | 623 | |
28c5a41e | 624 | mirror = pdata->mirror; |
a4e63554 AS |
625 | } |
626 | ||
627 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
628 | mcp->irq_active_high) { | |
0b7bb77f PK |
629 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
630 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
631 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
632 | if (mcp->irq_active_high) |
633 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
634 | else | |
635 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
636 | ||
4e47f91b LP |
637 | if (mirror) |
638 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
639 | ||
3539699c PR |
640 | if (type == MCP_TYPE_S18) |
641 | status |= IOCON_INTCC | (IOCON_INTCC << 8); | |
642 | ||
0b7bb77f | 643 | status = mcp->ops->write(mcp, MCP_IOCON, status); |
e58b9e27 DB |
644 | if (status < 0) |
645 | goto fail; | |
646 | } | |
647 | ||
648 | /* configure ~100K pullups */ | |
3af0dbd5 | 649 | status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups); |
e58b9e27 DB |
650 | if (status < 0) |
651 | goto fail; | |
652 | ||
0b7bb77f | 653 | status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache)); |
e58b9e27 DB |
654 | if (status < 0) |
655 | goto fail; | |
656 | ||
657 | /* disable inverter on input */ | |
658 | if (mcp->cache[MCP_IPOL] != 0) { | |
659 | mcp->cache[MCP_IPOL] = 0; | |
0b7bb77f PK |
660 | status = mcp->ops->write(mcp, MCP_IPOL, 0); |
661 | if (status < 0) | |
662 | goto fail; | |
e58b9e27 DB |
663 | } |
664 | ||
665 | /* disable irqs */ | |
666 | if (mcp->cache[MCP_GPINTEN] != 0) { | |
667 | mcp->cache[MCP_GPINTEN] = 0; | |
0b7bb77f | 668 | status = mcp->ops->write(mcp, MCP_GPINTEN, 0); |
8f1cc3b1 DB |
669 | if (status < 0) |
670 | goto fail; | |
e58b9e27 DB |
671 | } |
672 | ||
9e03cf0b | 673 | status = gpiochip_add_data(&mcp->chip, mcp); |
4e47f91b LP |
674 | if (status < 0) |
675 | goto fail; | |
676 | ||
677 | if (mcp->irq && mcp->irq_controller) { | |
678 | status = mcp23s08_irq_setup(mcp); | |
679 | if (status) { | |
4e47f91b LP |
680 | goto fail; |
681 | } | |
682 | } | |
8f1cc3b1 DB |
683 | fail: |
684 | if (status < 0) | |
d62b98f3 PK |
685 | dev_dbg(dev, "can't setup chip %d, --> %d\n", |
686 | addr, status); | |
8f1cc3b1 DB |
687 | return status; |
688 | } | |
689 | ||
752ad5e8 PK |
690 | /*----------------------------------------------------------------------*/ |
691 | ||
97ddb1c8 LP |
692 | #ifdef CONFIG_OF |
693 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 694 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 695 | { |
45971686 LP |
696 | .compatible = "microchip,mcp23s08", |
697 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
698 | }, |
699 | { | |
45971686 LP |
700 | .compatible = "microchip,mcp23s17", |
701 | .data = (void *) MCP_TYPE_S17, | |
702 | }, | |
28c5a41e PR |
703 | { |
704 | .compatible = "microchip,mcp23s18", | |
705 | .data = (void *) MCP_TYPE_S18, | |
706 | }, | |
45971686 LP |
707 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
708 | { | |
709 | .compatible = "mcp,mcp23s08", | |
710 | .data = (void *) MCP_TYPE_S08, | |
711 | }, | |
712 | { | |
713 | .compatible = "mcp,mcp23s17", | |
714 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
715 | }, |
716 | { }, | |
717 | }; | |
718 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
719 | #endif | |
720 | ||
721 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 722 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 723 | { |
45971686 LP |
724 | .compatible = "microchip,mcp23008", |
725 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
726 | }, |
727 | { | |
45971686 LP |
728 | .compatible = "microchip,mcp23017", |
729 | .data = (void *) MCP_TYPE_017, | |
730 | }, | |
731 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
732 | { | |
733 | .compatible = "mcp,mcp23008", | |
734 | .data = (void *) MCP_TYPE_008, | |
735 | }, | |
736 | { | |
737 | .compatible = "mcp,mcp23017", | |
738 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
739 | }, |
740 | { }, | |
741 | }; | |
742 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
743 | #endif | |
744 | #endif /* CONFIG_OF */ | |
745 | ||
746 | ||
cbf24fad | 747 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 748 | |
3836309d | 749 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
750 | const struct i2c_device_id *id) |
751 | { | |
3af0dbd5 | 752 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 753 | struct mcp23s08 *mcp; |
3af0dbd5 | 754 | int status; |
97ddb1c8 LP |
755 | const struct of_device_id *match; |
756 | ||
757 | match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match), | |
758 | &client->dev); | |
3af0dbd5 SZ |
759 | if (match) { |
760 | pdata = &local_pdata; | |
761 | pdata->base = -1; | |
762 | pdata->chip[0].pullups = 0; | |
763 | pdata->irq_controller = of_property_read_bool( | |
764 | client->dev.of_node, | |
765 | "interrupt-controller"); | |
766 | pdata->mirror = of_property_read_bool(client->dev.of_node, | |
767 | "microchip,irq-mirror"); | |
4e47f91b | 768 | client->irq = irq_of_parse_and_map(client->dev.of_node, 0); |
97ddb1c8 | 769 | } else { |
3af0dbd5 | 770 | pdata = dev_get_platdata(&client->dev); |
b184c388 SZ |
771 | if (!pdata) { |
772 | pdata = devm_kzalloc(&client->dev, | |
773 | sizeof(struct mcp23s08_platform_data), | |
774 | GFP_KERNEL); | |
aaf2b3af IY |
775 | if (!pdata) |
776 | return -ENOMEM; | |
b184c388 | 777 | pdata->base = -1; |
97ddb1c8 | 778 | } |
752ad5e8 PK |
779 | } |
780 | ||
33bc8411 | 781 | mcp = kzalloc(sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
782 | if (!mcp) |
783 | return -ENOMEM; | |
784 | ||
4e47f91b | 785 | mcp->irq = client->irq; |
752ad5e8 | 786 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
3af0dbd5 | 787 | id->driver_data, pdata, 0); |
752ad5e8 PK |
788 | if (status) |
789 | goto fail; | |
790 | ||
791 | i2c_set_clientdata(client, mcp); | |
792 | ||
793 | return 0; | |
794 | ||
795 | fail: | |
796 | kfree(mcp); | |
797 | ||
798 | return status; | |
799 | } | |
800 | ||
206210ce | 801 | static int mcp230xx_remove(struct i2c_client *client) |
752ad5e8 PK |
802 | { |
803 | struct mcp23s08 *mcp = i2c_get_clientdata(client); | |
752ad5e8 | 804 | |
9f5132ae | 805 | gpiochip_remove(&mcp->chip); |
806 | kfree(mcp); | |
752ad5e8 | 807 | |
9f5132ae | 808 | return 0; |
752ad5e8 PK |
809 | } |
810 | ||
811 | static const struct i2c_device_id mcp230xx_id[] = { | |
812 | { "mcp23008", MCP_TYPE_008 }, | |
813 | { "mcp23017", MCP_TYPE_017 }, | |
814 | { }, | |
815 | }; | |
816 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
817 | ||
818 | static struct i2c_driver mcp230xx_driver = { | |
819 | .driver = { | |
820 | .name = "mcp230xx", | |
97ddb1c8 | 821 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
822 | }, |
823 | .probe = mcp230xx_probe, | |
8283c4ff | 824 | .remove = mcp230xx_remove, |
752ad5e8 PK |
825 | .id_table = mcp230xx_id, |
826 | }; | |
827 | ||
828 | static int __init mcp23s08_i2c_init(void) | |
829 | { | |
830 | return i2c_add_driver(&mcp230xx_driver); | |
831 | } | |
832 | ||
833 | static void mcp23s08_i2c_exit(void) | |
834 | { | |
835 | i2c_del_driver(&mcp230xx_driver); | |
836 | } | |
837 | ||
838 | #else | |
839 | ||
840 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
841 | static void mcp23s08_i2c_exit(void) { } | |
842 | ||
843 | #endif /* CONFIG_I2C */ | |
844 | ||
845 | /*----------------------------------------------------------------------*/ | |
846 | ||
d62b98f3 PK |
847 | #ifdef CONFIG_SPI_MASTER |
848 | ||
8f1cc3b1 DB |
849 | static int mcp23s08_probe(struct spi_device *spi) |
850 | { | |
3af0dbd5 | 851 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 852 | unsigned addr; |
596a1c5f | 853 | int chips = 0; |
8f1cc3b1 | 854 | struct mcp23s08_driver_data *data; |
0b7bb77f | 855 | int status, type; |
3af0dbd5 | 856 | unsigned ngpio = 0; |
97ddb1c8 LP |
857 | const struct of_device_id *match; |
858 | u32 spi_present_mask = 0; | |
859 | ||
860 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
861 | if (match) { | |
de755c33 | 862 | type = (int)(uintptr_t)match->data; |
97ddb1c8 | 863 | status = of_property_read_u32(spi->dev.of_node, |
45971686 | 864 | "microchip,spi-present-mask", &spi_present_mask); |
97ddb1c8 | 865 | if (status) { |
45971686 LP |
866 | status = of_property_read_u32(spi->dev.of_node, |
867 | "mcp,spi-present-mask", &spi_present_mask); | |
868 | if (status) { | |
869 | dev_err(&spi->dev, | |
870 | "DT has no spi-present-mask\n"); | |
871 | return -ENODEV; | |
872 | } | |
97ddb1c8 LP |
873 | } |
874 | if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) { | |
875 | dev_err(&spi->dev, "invalid spi-present-mask\n"); | |
876 | return -ENODEV; | |
877 | } | |
8f1cc3b1 | 878 | |
3af0dbd5 SZ |
879 | pdata = &local_pdata; |
880 | pdata->base = -1; | |
99e4b98d | 881 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
3af0dbd5 | 882 | pdata->chip[addr].pullups = 0; |
3e3bed91 MS |
883 | if (spi_present_mask & (1 << addr)) |
884 | chips++; | |
99e4b98d | 885 | } |
3af0dbd5 SZ |
886 | pdata->irq_controller = of_property_read_bool( |
887 | spi->dev.of_node, | |
888 | "interrupt-controller"); | |
889 | pdata->mirror = of_property_read_bool(spi->dev.of_node, | |
890 | "microchip,irq-mirror"); | |
97ddb1c8 LP |
891 | } else { |
892 | type = spi_get_device_id(spi)->driver_data; | |
e56aee18 | 893 | pdata = dev_get_platdata(&spi->dev); |
b184c388 SZ |
894 | if (!pdata) { |
895 | pdata = devm_kzalloc(&spi->dev, | |
896 | sizeof(struct mcp23s08_platform_data), | |
897 | GFP_KERNEL); | |
898 | pdata->base = -1; | |
0b7bb77f | 899 | } |
97ddb1c8 LP |
900 | |
901 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { | |
902 | if (!pdata->chip[addr].is_present) | |
903 | continue; | |
904 | chips++; | |
905 | if ((type == MCP_TYPE_S08) && (addr > 3)) { | |
906 | dev_err(&spi->dev, | |
907 | "mcp23s08 only supports address 0..3\n"); | |
908 | return -EINVAL; | |
909 | } | |
910 | spi_present_mask |= 1 << addr; | |
97ddb1c8 | 911 | } |
8f1cc3b1 | 912 | } |
8f1cc3b1 | 913 | |
99e4b98d MW |
914 | if (!chips) |
915 | return -ENODEV; | |
916 | ||
7898b31e VB |
917 | data = devm_kzalloc(&spi->dev, |
918 | sizeof(*data) + chips * sizeof(struct mcp23s08), | |
919 | GFP_KERNEL); | |
8f1cc3b1 DB |
920 | if (!data) |
921 | return -ENOMEM; | |
7898b31e | 922 | |
8f1cc3b1 DB |
923 | spi_set_drvdata(spi, data); |
924 | ||
a231b88c AS |
925 | spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0); |
926 | ||
0b7bb77f | 927 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
97ddb1c8 | 928 | if (!(spi_present_mask & (1 << addr))) |
8f1cc3b1 DB |
929 | continue; |
930 | chips--; | |
931 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 932 | data->mcp[addr]->irq = spi->irq; |
d62b98f3 | 933 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
3af0dbd5 SZ |
934 | 0x40 | (addr << 1), type, pdata, |
935 | addr); | |
8f1cc3b1 DB |
936 | if (status < 0) |
937 | goto fail; | |
0b7bb77f | 938 | |
3af0dbd5 | 939 | if (pdata->base != -1) |
28c5a41e PR |
940 | pdata->base += data->mcp[addr]->chip.ngpio; |
941 | ngpio += data->mcp[addr]->chip.ngpio; | |
8f1cc3b1 | 942 | } |
97ddb1c8 | 943 | data->ngpio = ngpio; |
e58b9e27 DB |
944 | |
945 | /* NOTE: these chips have a relatively sane IRQ framework, with | |
946 | * per-signal masking and level/edge triggering. It's not yet | |
947 | * handled here... | |
948 | */ | |
949 | ||
e58b9e27 DB |
950 | return 0; |
951 | ||
952 | fail: | |
0b7bb77f | 953 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
954 | |
955 | if (!data->mcp[addr]) | |
956 | continue; | |
9f5132ae | 957 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 958 | } |
e58b9e27 DB |
959 | return status; |
960 | } | |
961 | ||
962 | static int mcp23s08_remove(struct spi_device *spi) | |
963 | { | |
8f1cc3b1 | 964 | struct mcp23s08_driver_data *data = spi_get_drvdata(spi); |
8f1cc3b1 | 965 | unsigned addr; |
e58b9e27 | 966 | |
0b7bb77f | 967 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
968 | |
969 | if (!data->mcp[addr]) | |
970 | continue; | |
971 | ||
9f5132ae | 972 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 973 | } |
c4941e07 | 974 | |
9f5132ae | 975 | return 0; |
e58b9e27 DB |
976 | } |
977 | ||
0b7bb77f PK |
978 | static const struct spi_device_id mcp23s08_ids[] = { |
979 | { "mcp23s08", MCP_TYPE_S08 }, | |
980 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 981 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
982 | { }, |
983 | }; | |
984 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
985 | ||
e58b9e27 DB |
986 | static struct spi_driver mcp23s08_driver = { |
987 | .probe = mcp23s08_probe, | |
988 | .remove = mcp23s08_remove, | |
0b7bb77f | 989 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
990 | .driver = { |
991 | .name = "mcp23s08", | |
97ddb1c8 | 992 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
993 | }, |
994 | }; | |
995 | ||
d62b98f3 PK |
996 | static int __init mcp23s08_spi_init(void) |
997 | { | |
998 | return spi_register_driver(&mcp23s08_driver); | |
999 | } | |
1000 | ||
1001 | static void mcp23s08_spi_exit(void) | |
1002 | { | |
1003 | spi_unregister_driver(&mcp23s08_driver); | |
1004 | } | |
1005 | ||
1006 | #else | |
1007 | ||
1008 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1009 | static void mcp23s08_spi_exit(void) { } | |
1010 | ||
1011 | #endif /* CONFIG_SPI_MASTER */ | |
1012 | ||
e58b9e27 DB |
1013 | /*----------------------------------------------------------------------*/ |
1014 | ||
1015 | static int __init mcp23s08_init(void) | |
1016 | { | |
752ad5e8 PK |
1017 | int ret; |
1018 | ||
1019 | ret = mcp23s08_spi_init(); | |
1020 | if (ret) | |
1021 | goto spi_fail; | |
1022 | ||
1023 | ret = mcp23s08_i2c_init(); | |
1024 | if (ret) | |
1025 | goto i2c_fail; | |
1026 | ||
1027 | return 0; | |
1028 | ||
1029 | i2c_fail: | |
1030 | mcp23s08_spi_exit(); | |
1031 | spi_fail: | |
1032 | return ret; | |
e58b9e27 | 1033 | } |
752ad5e8 | 1034 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1035 | * subsys initcalls that may rely on these GPIOs |
1036 | */ | |
1037 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1038 | |
1039 | static void __exit mcp23s08_exit(void) | |
1040 | { | |
d62b98f3 | 1041 | mcp23s08_spi_exit(); |
752ad5e8 | 1042 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1043 | } |
1044 | module_exit(mcp23s08_exit); | |
1045 | ||
1046 | MODULE_LICENSE("GPL"); |