dell-smbios: rename release_buffer() to dell_smbios_release_buffer()
[linux-2.6-block.git] / drivers / gpio / gpio-mcp23s08.c
CommitLineData
e58b9e27 1/*
4e47f91b
LP
2 * MCP23S08 SPI/I2C GPIO gpio expander driver
3 *
4 * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are
5 * supported.
6 * For the I2C versions of the chips (mcp23008 and mcp23017) generation of
7 * interrupts is also supported.
8 * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is
9 * also capable of generating interrupts, but the linux driver does not
10 * support that yet.
e58b9e27
DB
11 */
12
13#include <linux/kernel.h>
14#include <linux/device.h>
e58b9e27 15#include <linux/mutex.h>
bb207ef1 16#include <linux/module.h>
d120c17f 17#include <linux/gpio.h>
752ad5e8 18#include <linux/i2c.h>
e58b9e27
DB
19#include <linux/spi/spi.h>
20#include <linux/spi/mcp23s08.h>
5a0e3ad6 21#include <linux/slab.h>
0b7bb77f 22#include <asm/byteorder.h>
4e47f91b
LP
23#include <linux/interrupt.h>
24#include <linux/of_irq.h>
97ddb1c8 25#include <linux/of_device.h>
e58b9e27 26
0b7bb77f
PK
27/**
28 * MCP types supported by driver
29 */
30#define MCP_TYPE_S08 0
31#define MCP_TYPE_S17 1
752ad5e8
PK
32#define MCP_TYPE_008 2
33#define MCP_TYPE_017 3
e58b9e27
DB
34
35/* Registers are all 8 bits wide.
36 *
37 * The mcp23s17 has twice as many bits, and can be configured to work
38 * with either 16 bit registers or with two adjacent 8 bit banks.
e58b9e27
DB
39 */
40#define MCP_IODIR 0x00 /* init/reset: all ones */
41#define MCP_IPOL 0x01
42#define MCP_GPINTEN 0x02
43#define MCP_DEFVAL 0x03
44#define MCP_INTCON 0x04
45#define MCP_IOCON 0x05
4e47f91b 46# define IOCON_MIRROR (1 << 6)
e58b9e27
DB
47# define IOCON_SEQOP (1 << 5)
48# define IOCON_HAEN (1 << 3)
49# define IOCON_ODR (1 << 2)
50# define IOCON_INTPOL (1 << 1)
51#define MCP_GPPU 0x06
52#define MCP_INTF 0x07
53#define MCP_INTCAP 0x08
54#define MCP_GPIO 0x09
55#define MCP_OLAT 0x0a
56
0b7bb77f
PK
57struct mcp23s08;
58
59struct mcp23s08_ops {
60 int (*read)(struct mcp23s08 *mcp, unsigned reg);
61 int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val);
62 int (*read_regs)(struct mcp23s08 *mcp, unsigned reg,
63 u16 *vals, unsigned n);
64};
65
e58b9e27 66struct mcp23s08 {
e58b9e27 67 u8 addr;
a4e63554 68 bool irq_active_high;
e58b9e27 69
0b7bb77f 70 u16 cache[11];
4e47f91b
LP
71 u16 irq_rise;
72 u16 irq_fall;
73 int irq;
74 bool irq_controller;
e58b9e27
DB
75 /* lock protects the cached values */
76 struct mutex lock;
4e47f91b
LP
77 struct mutex irq_lock;
78 struct irq_domain *irq_domain;
e58b9e27
DB
79
80 struct gpio_chip chip;
81
0b7bb77f 82 const struct mcp23s08_ops *ops;
d62b98f3 83 void *data; /* ops specific data */
e58b9e27
DB
84};
85
0b7bb77f 86/* A given spi_device can represent up to eight mcp23sxx chips
8f1cc3b1
DB
87 * sharing the same chipselect but using different addresses
88 * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
89 * Driver data holds all the per-chip data.
90 */
91struct mcp23s08_driver_data {
92 unsigned ngpio;
0b7bb77f 93 struct mcp23s08 *mcp[8];
8f1cc3b1
DB
94 struct mcp23s08 chip[];
95};
96
4e47f91b
LP
97/* This lock class tells lockdep that GPIO irqs are in a different
98 * category than their parents, so it won't report false recursion.
99 */
100static struct lock_class_key gpio_lock_class;
101
752ad5e8
PK
102/*----------------------------------------------------------------------*/
103
cbf24fad 104#if IS_ENABLED(CONFIG_I2C)
752ad5e8
PK
105
106static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
107{
108 return i2c_smbus_read_byte_data(mcp->data, reg);
109}
110
111static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
112{
113 return i2c_smbus_write_byte_data(mcp->data, reg, val);
114}
115
116static int
117mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
118{
119 while (n--) {
120 int ret = mcp23008_read(mcp, reg++);
121 if (ret < 0)
122 return ret;
123 *vals++ = ret;
124 }
125
126 return 0;
127}
128
129static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg)
130{
131 return i2c_smbus_read_word_data(mcp->data, reg << 1);
132}
133
134static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
135{
136 return i2c_smbus_write_word_data(mcp->data, reg << 1, val);
137}
138
139static int
140mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
141{
142 while (n--) {
143 int ret = mcp23017_read(mcp, reg++);
144 if (ret < 0)
145 return ret;
146 *vals++ = ret;
147 }
148
149 return 0;
150}
151
152static const struct mcp23s08_ops mcp23008_ops = {
153 .read = mcp23008_read,
154 .write = mcp23008_write,
155 .read_regs = mcp23008_read_regs,
156};
157
158static const struct mcp23s08_ops mcp23017_ops = {
159 .read = mcp23017_read,
160 .write = mcp23017_write,
161 .read_regs = mcp23017_read_regs,
162};
163
164#endif /* CONFIG_I2C */
165
166/*----------------------------------------------------------------------*/
167
d62b98f3
PK
168#ifdef CONFIG_SPI_MASTER
169
e58b9e27
DB
170static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
171{
172 u8 tx[2], rx[1];
173 int status;
174
175 tx[0] = mcp->addr | 0x01;
176 tx[1] = reg;
33bc8411 177 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
e58b9e27
DB
178 return (status < 0) ? status : rx[0];
179}
180
0b7bb77f 181static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
e58b9e27
DB
182{
183 u8 tx[3];
184
185 tx[0] = mcp->addr;
186 tx[1] = reg;
187 tx[2] = val;
33bc8411 188 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
e58b9e27
DB
189}
190
191static int
0b7bb77f 192mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
e58b9e27 193{
0b7bb77f
PK
194 u8 tx[2], *tmp;
195 int status;
e58b9e27 196
33bc8411 197 if ((n + reg) > sizeof(mcp->cache))
e58b9e27
DB
198 return -EINVAL;
199 tx[0] = mcp->addr | 0x01;
200 tx[1] = reg;
0b7bb77f
PK
201
202 tmp = (u8 *)vals;
33bc8411 203 status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n);
0b7bb77f
PK
204 if (status >= 0) {
205 while (n--)
206 vals[n] = tmp[n]; /* expand to 16bit */
207 }
208 return status;
209}
210
211static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
212{
213 u8 tx[2], rx[2];
214 int status;
215
216 tx[0] = mcp->addr | 0x01;
217 tx[1] = reg << 1;
33bc8411 218 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
0b7bb77f
PK
219 return (status < 0) ? status : (rx[0] | (rx[1] << 8));
220}
221
222static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
223{
224 u8 tx[4];
225
226 tx[0] = mcp->addr;
227 tx[1] = reg << 1;
228 tx[2] = val;
229 tx[3] = val >> 8;
33bc8411 230 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
0b7bb77f
PK
231}
232
233static int
234mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
235{
236 u8 tx[2];
237 int status;
238
33bc8411 239 if ((n + reg) > sizeof(mcp->cache))
0b7bb77f
PK
240 return -EINVAL;
241 tx[0] = mcp->addr | 0x01;
242 tx[1] = reg << 1;
243
33bc8411 244 status = spi_write_then_read(mcp->data, tx, sizeof(tx),
0b7bb77f
PK
245 (u8 *)vals, n * 2);
246 if (status >= 0) {
247 while (n--)
248 vals[n] = __le16_to_cpu((__le16)vals[n]);
249 }
250
251 return status;
e58b9e27
DB
252}
253
0b7bb77f
PK
254static const struct mcp23s08_ops mcp23s08_ops = {
255 .read = mcp23s08_read,
256 .write = mcp23s08_write,
257 .read_regs = mcp23s08_read_regs,
258};
259
260static const struct mcp23s08_ops mcp23s17_ops = {
261 .read = mcp23s17_read,
262 .write = mcp23s17_write,
263 .read_regs = mcp23s17_read_regs,
264};
265
d62b98f3 266#endif /* CONFIG_SPI_MASTER */
0b7bb77f 267
e58b9e27
DB
268/*----------------------------------------------------------------------*/
269
270static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
271{
9e03cf0b 272 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
273 int status;
274
275 mutex_lock(&mcp->lock);
276 mcp->cache[MCP_IODIR] |= (1 << offset);
0b7bb77f 277 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
278 mutex_unlock(&mcp->lock);
279 return status;
280}
281
282static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
283{
9e03cf0b 284 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
285 int status;
286
287 mutex_lock(&mcp->lock);
288
289 /* REVISIT reading this clears any IRQ ... */
0b7bb77f 290 status = mcp->ops->read(mcp, MCP_GPIO);
e58b9e27
DB
291 if (status < 0)
292 status = 0;
293 else {
294 mcp->cache[MCP_GPIO] = status;
295 status = !!(status & (1 << offset));
296 }
297 mutex_unlock(&mcp->lock);
298 return status;
299}
300
301static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
302{
0b7bb77f 303 unsigned olat = mcp->cache[MCP_OLAT];
e58b9e27
DB
304
305 if (value)
306 olat |= mask;
307 else
308 olat &= ~mask;
309 mcp->cache[MCP_OLAT] = olat;
0b7bb77f 310 return mcp->ops->write(mcp, MCP_OLAT, olat);
e58b9e27
DB
311}
312
313static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
314{
9e03cf0b 315 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 316 unsigned mask = 1 << offset;
e58b9e27
DB
317
318 mutex_lock(&mcp->lock);
319 __mcp23s08_set(mcp, mask, value);
320 mutex_unlock(&mcp->lock);
321}
322
323static int
324mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
325{
9e03cf0b 326 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 327 unsigned mask = 1 << offset;
e58b9e27
DB
328 int status;
329
330 mutex_lock(&mcp->lock);
331 status = __mcp23s08_set(mcp, mask, value);
332 if (status == 0) {
333 mcp->cache[MCP_IODIR] &= ~mask;
0b7bb77f 334 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
335 }
336 mutex_unlock(&mcp->lock);
337 return status;
338}
339
4e47f91b
LP
340/*----------------------------------------------------------------------*/
341static irqreturn_t mcp23s08_irq(int irq, void *data)
342{
343 struct mcp23s08 *mcp = data;
344 int intcap, intf, i;
345 unsigned int child_irq;
346
347 mutex_lock(&mcp->lock);
348 intf = mcp->ops->read(mcp, MCP_INTF);
349 if (intf < 0) {
350 mutex_unlock(&mcp->lock);
351 return IRQ_HANDLED;
352 }
353
354 mcp->cache[MCP_INTF] = intf;
355
356 intcap = mcp->ops->read(mcp, MCP_INTCAP);
357 if (intcap < 0) {
358 mutex_unlock(&mcp->lock);
359 return IRQ_HANDLED;
360 }
361
362 mcp->cache[MCP_INTCAP] = intcap;
363 mutex_unlock(&mcp->lock);
364
365
366 for (i = 0; i < mcp->chip.ngpio; i++) {
367 if ((BIT(i) & mcp->cache[MCP_INTF]) &&
368 ((BIT(i) & intcap & mcp->irq_rise) ||
369 (mcp->irq_fall & ~intcap & BIT(i)))) {
370 child_irq = irq_find_mapping(mcp->irq_domain, i);
371 handle_nested_irq(child_irq);
372 }
373 }
374
375 return IRQ_HANDLED;
376}
377
378static int mcp23s08_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
379{
9e03cf0b 380 struct mcp23s08 *mcp = gpiochip_get_data(chip);
4e47f91b
LP
381
382 return irq_find_mapping(mcp->irq_domain, offset);
383}
384
385static void mcp23s08_irq_mask(struct irq_data *data)
386{
387 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
388 unsigned int pos = data->hwirq;
389
390 mcp->cache[MCP_GPINTEN] &= ~BIT(pos);
391}
392
393static void mcp23s08_irq_unmask(struct irq_data *data)
394{
395 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
396 unsigned int pos = data->hwirq;
397
398 mcp->cache[MCP_GPINTEN] |= BIT(pos);
399}
400
401static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
402{
403 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
404 unsigned int pos = data->hwirq;
405 int status = 0;
406
407 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
408 mcp->cache[MCP_INTCON] &= ~BIT(pos);
409 mcp->irq_rise |= BIT(pos);
410 mcp->irq_fall |= BIT(pos);
411 } else if (type & IRQ_TYPE_EDGE_RISING) {
412 mcp->cache[MCP_INTCON] &= ~BIT(pos);
413 mcp->irq_rise |= BIT(pos);
414 mcp->irq_fall &= ~BIT(pos);
415 } else if (type & IRQ_TYPE_EDGE_FALLING) {
416 mcp->cache[MCP_INTCON] &= ~BIT(pos);
417 mcp->irq_rise &= ~BIT(pos);
418 mcp->irq_fall |= BIT(pos);
419 } else
420 return -EINVAL;
421
422 return status;
423}
424
425static void mcp23s08_irq_bus_lock(struct irq_data *data)
426{
427 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
428
429 mutex_lock(&mcp->irq_lock);
430}
431
432static void mcp23s08_irq_bus_unlock(struct irq_data *data)
433{
434 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
435
436 mutex_lock(&mcp->lock);
437 mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]);
438 mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]);
439 mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]);
440 mutex_unlock(&mcp->lock);
441 mutex_unlock(&mcp->irq_lock);
442}
443
57ef0428 444static int mcp23s08_irq_reqres(struct irq_data *data)
4e47f91b
LP
445{
446 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
447
e3a2e878 448 if (gpiochip_lock_as_irq(&mcp->chip, data->hwirq)) {
58383c78 449 dev_err(mcp->chip.parent,
4e47f91b
LP
450 "unable to lock HW IRQ %lu for IRQ usage\n",
451 data->hwirq);
57ef0428
LW
452 return -EINVAL;
453 }
4e47f91b 454
4e47f91b
LP
455 return 0;
456}
457
57ef0428 458static void mcp23s08_irq_relres(struct irq_data *data)
4e47f91b
LP
459{
460 struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
461
e3a2e878 462 gpiochip_unlock_as_irq(&mcp->chip, data->hwirq);
4e47f91b
LP
463}
464
465static struct irq_chip mcp23s08_irq_chip = {
466 .name = "gpio-mcp23xxx",
467 .irq_mask = mcp23s08_irq_mask,
468 .irq_unmask = mcp23s08_irq_unmask,
469 .irq_set_type = mcp23s08_irq_set_type,
470 .irq_bus_lock = mcp23s08_irq_bus_lock,
471 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
57ef0428
LW
472 .irq_request_resources = mcp23s08_irq_reqres,
473 .irq_release_resources = mcp23s08_irq_relres,
4e47f91b
LP
474};
475
476static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
477{
478 struct gpio_chip *chip = &mcp->chip;
479 int err, irq, j;
a4e63554 480 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
4e47f91b
LP
481
482 mutex_init(&mcp->irq_lock);
483
58383c78
LW
484 mcp->irq_domain = irq_domain_add_linear(chip->parent->of_node,
485 chip->ngpio,
4e47f91b
LP
486 &irq_domain_simple_ops, mcp);
487 if (!mcp->irq_domain)
488 return -ENODEV;
489
a4e63554
AS
490 if (mcp->irq_active_high)
491 irqflags |= IRQF_TRIGGER_HIGH;
492 else
493 irqflags |= IRQF_TRIGGER_LOW;
494
58383c78
LW
495 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
496 mcp23s08_irq,
497 irqflags, dev_name(chip->parent), mcp);
4e47f91b 498 if (err != 0) {
58383c78 499 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
4e47f91b
LP
500 mcp->irq, err);
501 return err;
502 }
503
504 chip->to_irq = mcp23s08_gpio_to_irq;
505
506 for (j = 0; j < mcp->chip.ngpio; j++) {
507 irq = irq_create_mapping(mcp->irq_domain, j);
508 irq_set_lockdep_class(irq, &gpio_lock_class);
509 irq_set_chip_data(irq, mcp);
510 irq_set_chip(irq, &mcp23s08_irq_chip);
511 irq_set_nested_thread(irq, true);
4e47f91b 512 irq_set_noprobe(irq);
4e47f91b
LP
513 }
514 return 0;
515}
516
517static void mcp23s08_irq_teardown(struct mcp23s08 *mcp)
518{
519 unsigned int irq, i;
520
4e47f91b
LP
521 for (i = 0; i < mcp->chip.ngpio; i++) {
522 irq = irq_find_mapping(mcp->irq_domain, i);
523 if (irq > 0)
524 irq_dispose_mapping(irq);
525 }
526
527 irq_domain_remove(mcp->irq_domain);
528}
529
e58b9e27
DB
530/*----------------------------------------------------------------------*/
531
532#ifdef CONFIG_DEBUG_FS
533
534#include <linux/seq_file.h>
535
536/*
537 * This shows more info than the generic gpio dump code:
538 * pullups, deglitching, open drain drive.
539 */
540static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
541{
542 struct mcp23s08 *mcp;
543 char bank;
1d1c1d9b 544 int t;
e58b9e27
DB
545 unsigned mask;
546
9e03cf0b 547 mcp = gpiochip_get_data(chip);
e58b9e27
DB
548
549 /* NOTE: we only handle one bank for now ... */
0b7bb77f 550 bank = '0' + ((mcp->addr >> 1) & 0x7);
e58b9e27
DB
551
552 mutex_lock(&mcp->lock);
0b7bb77f 553 t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
e58b9e27
DB
554 if (t < 0) {
555 seq_printf(s, " I/O ERROR %d\n", t);
556 goto done;
557 }
558
0b7bb77f 559 for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
e58b9e27
DB
560 const char *label;
561
562 label = gpiochip_is_requested(chip, t);
563 if (!label)
564 continue;
565
566 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s",
567 chip->base + t, bank, t, label,
568 (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
569 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
eb1567f7 570 (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
e58b9e27 571 /* NOTE: ignoring the irq-related registers */
33bc8411 572 seq_puts(s, "\n");
e58b9e27
DB
573 }
574done:
575 mutex_unlock(&mcp->lock);
576}
577
578#else
579#define mcp23s08_dbg_show NULL
580#endif
581
582/*----------------------------------------------------------------------*/
583
d62b98f3 584static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
4e47f91b 585 void *data, unsigned addr, unsigned type,
3af0dbd5 586 struct mcp23s08_platform_data *pdata, int cs)
e58b9e27 587{
d62b98f3 588 int status;
4e47f91b 589 bool mirror = false;
e58b9e27 590
e58b9e27
DB
591 mutex_init(&mcp->lock);
592
d62b98f3
PK
593 mcp->data = data;
594 mcp->addr = addr;
a4e63554 595 mcp->irq_active_high = false;
e58b9e27 596
e58b9e27
DB
597 mcp->chip.direction_input = mcp23s08_direction_input;
598 mcp->chip.get = mcp23s08_get;
599 mcp->chip.direction_output = mcp23s08_direction_output;
600 mcp->chip.set = mcp23s08_set;
601 mcp->chip.dbg_show = mcp23s08_dbg_show;
97ddb1c8
LP
602#ifdef CONFIG_OF
603 mcp->chip.of_gpio_n_cells = 2;
604 mcp->chip.of_node = dev->of_node;
605#endif
e58b9e27 606
d62b98f3
PK
607 switch (type) {
608#ifdef CONFIG_SPI_MASTER
609 case MCP_TYPE_S08:
0b7bb77f
PK
610 mcp->ops = &mcp23s08_ops;
611 mcp->chip.ngpio = 8;
612 mcp->chip.label = "mcp23s08";
d62b98f3
PK
613 break;
614
615 case MCP_TYPE_S17:
616 mcp->ops = &mcp23s17_ops;
617 mcp->chip.ngpio = 16;
618 mcp->chip.label = "mcp23s17";
619 break;
620#endif /* CONFIG_SPI_MASTER */
621
cbf24fad 622#if IS_ENABLED(CONFIG_I2C)
752ad5e8
PK
623 case MCP_TYPE_008:
624 mcp->ops = &mcp23008_ops;
625 mcp->chip.ngpio = 8;
626 mcp->chip.label = "mcp23008";
627 break;
628
629 case MCP_TYPE_017:
630 mcp->ops = &mcp23017_ops;
631 mcp->chip.ngpio = 16;
632 mcp->chip.label = "mcp23017";
633 break;
634#endif /* CONFIG_I2C */
635
d62b98f3
PK
636 default:
637 dev_err(dev, "invalid device type (%d)\n", type);
638 return -EINVAL;
0b7bb77f 639 }
d62b98f3 640
3af0dbd5 641 mcp->chip.base = pdata->base;
9fb1f39e 642 mcp->chip.can_sleep = true;
58383c78 643 mcp->chip.parent = dev;
d72cbed0 644 mcp->chip.owner = THIS_MODULE;
e58b9e27 645
8f1cc3b1
DB
646 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
647 * and MCP_IOCON.HAEN = 1, so we work with all chips.
648 */
4e47f91b 649
0b7bb77f 650 status = mcp->ops->read(mcp, MCP_IOCON);
e58b9e27
DB
651 if (status < 0)
652 goto fail;
4e47f91b 653
3af0dbd5 654 mcp->irq_controller = pdata->irq_controller;
a4e63554 655 if (mcp->irq && mcp->irq_controller) {
170680ab 656 mcp->irq_active_high =
58383c78 657 of_property_read_bool(mcp->chip.parent->of_node,
170680ab 658 "microchip,irq-active-high");
4e47f91b 659
a4e63554
AS
660 if (type == MCP_TYPE_017)
661 mirror = pdata->mirror;
662 }
663
664 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
665 mcp->irq_active_high) {
0b7bb77f
PK
666 /* mcp23s17 has IOCON twice, make sure they are in sync */
667 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
668 status |= IOCON_HAEN | (IOCON_HAEN << 8);
a4e63554
AS
669 if (mcp->irq_active_high)
670 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
671 else
672 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
673
4e47f91b
LP
674 if (mirror)
675 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
676
0b7bb77f 677 status = mcp->ops->write(mcp, MCP_IOCON, status);
e58b9e27
DB
678 if (status < 0)
679 goto fail;
680 }
681
682 /* configure ~100K pullups */
3af0dbd5 683 status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups);
e58b9e27
DB
684 if (status < 0)
685 goto fail;
686
0b7bb77f 687 status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
e58b9e27
DB
688 if (status < 0)
689 goto fail;
690
691 /* disable inverter on input */
692 if (mcp->cache[MCP_IPOL] != 0) {
693 mcp->cache[MCP_IPOL] = 0;
0b7bb77f
PK
694 status = mcp->ops->write(mcp, MCP_IPOL, 0);
695 if (status < 0)
696 goto fail;
e58b9e27
DB
697 }
698
699 /* disable irqs */
700 if (mcp->cache[MCP_GPINTEN] != 0) {
701 mcp->cache[MCP_GPINTEN] = 0;
0b7bb77f 702 status = mcp->ops->write(mcp, MCP_GPINTEN, 0);
8f1cc3b1
DB
703 if (status < 0)
704 goto fail;
e58b9e27
DB
705 }
706
9e03cf0b 707 status = gpiochip_add_data(&mcp->chip, mcp);
4e47f91b
LP
708 if (status < 0)
709 goto fail;
710
711 if (mcp->irq && mcp->irq_controller) {
712 status = mcp23s08_irq_setup(mcp);
713 if (status) {
714 mcp23s08_irq_teardown(mcp);
715 goto fail;
716 }
717 }
8f1cc3b1
DB
718fail:
719 if (status < 0)
d62b98f3
PK
720 dev_dbg(dev, "can't setup chip %d, --> %d\n",
721 addr, status);
8f1cc3b1
DB
722 return status;
723}
724
752ad5e8
PK
725/*----------------------------------------------------------------------*/
726
97ddb1c8
LP
727#ifdef CONFIG_OF
728#ifdef CONFIG_SPI_MASTER
ac791804 729static const struct of_device_id mcp23s08_spi_of_match[] = {
97ddb1c8 730 {
45971686
LP
731 .compatible = "microchip,mcp23s08",
732 .data = (void *) MCP_TYPE_S08,
97ddb1c8
LP
733 },
734 {
45971686
LP
735 .compatible = "microchip,mcp23s17",
736 .data = (void *) MCP_TYPE_S17,
737 },
738/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
739 {
740 .compatible = "mcp,mcp23s08",
741 .data = (void *) MCP_TYPE_S08,
742 },
743 {
744 .compatible = "mcp,mcp23s17",
745 .data = (void *) MCP_TYPE_S17,
97ddb1c8
LP
746 },
747 { },
748};
749MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
750#endif
751
752#if IS_ENABLED(CONFIG_I2C)
ac791804 753static const struct of_device_id mcp23s08_i2c_of_match[] = {
97ddb1c8 754 {
45971686
LP
755 .compatible = "microchip,mcp23008",
756 .data = (void *) MCP_TYPE_008,
97ddb1c8
LP
757 },
758 {
45971686
LP
759 .compatible = "microchip,mcp23017",
760 .data = (void *) MCP_TYPE_017,
761 },
762/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
763 {
764 .compatible = "mcp,mcp23008",
765 .data = (void *) MCP_TYPE_008,
766 },
767 {
768 .compatible = "mcp,mcp23017",
769 .data = (void *) MCP_TYPE_017,
97ddb1c8
LP
770 },
771 { },
772};
773MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
774#endif
775#endif /* CONFIG_OF */
776
777
cbf24fad 778#if IS_ENABLED(CONFIG_I2C)
752ad5e8 779
3836309d 780static int mcp230xx_probe(struct i2c_client *client,
752ad5e8
PK
781 const struct i2c_device_id *id)
782{
3af0dbd5 783 struct mcp23s08_platform_data *pdata, local_pdata;
752ad5e8 784 struct mcp23s08 *mcp;
3af0dbd5 785 int status;
97ddb1c8
LP
786 const struct of_device_id *match;
787
788 match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match),
789 &client->dev);
3af0dbd5
SZ
790 if (match) {
791 pdata = &local_pdata;
792 pdata->base = -1;
793 pdata->chip[0].pullups = 0;
794 pdata->irq_controller = of_property_read_bool(
795 client->dev.of_node,
796 "interrupt-controller");
797 pdata->mirror = of_property_read_bool(client->dev.of_node,
798 "microchip,irq-mirror");
4e47f91b 799 client->irq = irq_of_parse_and_map(client->dev.of_node, 0);
97ddb1c8 800 } else {
3af0dbd5 801 pdata = dev_get_platdata(&client->dev);
b184c388
SZ
802 if (!pdata) {
803 pdata = devm_kzalloc(&client->dev,
804 sizeof(struct mcp23s08_platform_data),
805 GFP_KERNEL);
806 pdata->base = -1;
97ddb1c8 807 }
752ad5e8
PK
808 }
809
33bc8411 810 mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
752ad5e8
PK
811 if (!mcp)
812 return -ENOMEM;
813
4e47f91b 814 mcp->irq = client->irq;
752ad5e8 815 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
3af0dbd5 816 id->driver_data, pdata, 0);
752ad5e8
PK
817 if (status)
818 goto fail;
819
820 i2c_set_clientdata(client, mcp);
821
822 return 0;
823
824fail:
825 kfree(mcp);
826
827 return status;
828}
829
206210ce 830static int mcp230xx_remove(struct i2c_client *client)
752ad5e8
PK
831{
832 struct mcp23s08 *mcp = i2c_get_clientdata(client);
752ad5e8 833
4e47f91b
LP
834 if (client->irq && mcp->irq_controller)
835 mcp23s08_irq_teardown(mcp);
836
9f5132ae 837 gpiochip_remove(&mcp->chip);
838 kfree(mcp);
752ad5e8 839
9f5132ae 840 return 0;
752ad5e8
PK
841}
842
843static const struct i2c_device_id mcp230xx_id[] = {
844 { "mcp23008", MCP_TYPE_008 },
845 { "mcp23017", MCP_TYPE_017 },
846 { },
847};
848MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
849
850static struct i2c_driver mcp230xx_driver = {
851 .driver = {
852 .name = "mcp230xx",
97ddb1c8 853 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
752ad5e8
PK
854 },
855 .probe = mcp230xx_probe,
8283c4ff 856 .remove = mcp230xx_remove,
752ad5e8
PK
857 .id_table = mcp230xx_id,
858};
859
860static int __init mcp23s08_i2c_init(void)
861{
862 return i2c_add_driver(&mcp230xx_driver);
863}
864
865static void mcp23s08_i2c_exit(void)
866{
867 i2c_del_driver(&mcp230xx_driver);
868}
869
870#else
871
872static int __init mcp23s08_i2c_init(void) { return 0; }
873static void mcp23s08_i2c_exit(void) { }
874
875#endif /* CONFIG_I2C */
876
877/*----------------------------------------------------------------------*/
878
d62b98f3
PK
879#ifdef CONFIG_SPI_MASTER
880
8f1cc3b1
DB
881static int mcp23s08_probe(struct spi_device *spi)
882{
3af0dbd5 883 struct mcp23s08_platform_data *pdata, local_pdata;
8f1cc3b1 884 unsigned addr;
596a1c5f 885 int chips = 0;
8f1cc3b1 886 struct mcp23s08_driver_data *data;
0b7bb77f 887 int status, type;
3af0dbd5 888 unsigned ngpio = 0;
97ddb1c8
LP
889 const struct of_device_id *match;
890 u32 spi_present_mask = 0;
891
892 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
893 if (match) {
de755c33 894 type = (int)(uintptr_t)match->data;
97ddb1c8 895 status = of_property_read_u32(spi->dev.of_node,
45971686 896 "microchip,spi-present-mask", &spi_present_mask);
97ddb1c8 897 if (status) {
45971686
LP
898 status = of_property_read_u32(spi->dev.of_node,
899 "mcp,spi-present-mask", &spi_present_mask);
900 if (status) {
901 dev_err(&spi->dev,
902 "DT has no spi-present-mask\n");
903 return -ENODEV;
904 }
97ddb1c8
LP
905 }
906 if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) {
907 dev_err(&spi->dev, "invalid spi-present-mask\n");
908 return -ENODEV;
909 }
8f1cc3b1 910
3af0dbd5
SZ
911 pdata = &local_pdata;
912 pdata->base = -1;
99e4b98d 913 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
3af0dbd5 914 pdata->chip[addr].pullups = 0;
3e3bed91
MS
915 if (spi_present_mask & (1 << addr))
916 chips++;
99e4b98d 917 }
3af0dbd5
SZ
918 pdata->irq_controller = of_property_read_bool(
919 spi->dev.of_node,
920 "interrupt-controller");
921 pdata->mirror = of_property_read_bool(spi->dev.of_node,
922 "microchip,irq-mirror");
97ddb1c8
LP
923 } else {
924 type = spi_get_device_id(spi)->driver_data;
e56aee18 925 pdata = dev_get_platdata(&spi->dev);
b184c388
SZ
926 if (!pdata) {
927 pdata = devm_kzalloc(&spi->dev,
928 sizeof(struct mcp23s08_platform_data),
929 GFP_KERNEL);
930 pdata->base = -1;
0b7bb77f 931 }
97ddb1c8
LP
932
933 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
934 if (!pdata->chip[addr].is_present)
935 continue;
936 chips++;
937 if ((type == MCP_TYPE_S08) && (addr > 3)) {
938 dev_err(&spi->dev,
939 "mcp23s08 only supports address 0..3\n");
940 return -EINVAL;
941 }
942 spi_present_mask |= 1 << addr;
97ddb1c8 943 }
8f1cc3b1 944 }
8f1cc3b1 945
99e4b98d
MW
946 if (!chips)
947 return -ENODEV;
948
7898b31e
VB
949 data = devm_kzalloc(&spi->dev,
950 sizeof(*data) + chips * sizeof(struct mcp23s08),
951 GFP_KERNEL);
8f1cc3b1
DB
952 if (!data)
953 return -ENOMEM;
7898b31e 954
8f1cc3b1
DB
955 spi_set_drvdata(spi, data);
956
a231b88c
AS
957 spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
958
0b7bb77f 959 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
97ddb1c8 960 if (!(spi_present_mask & (1 << addr)))
8f1cc3b1
DB
961 continue;
962 chips--;
963 data->mcp[addr] = &data->chip[chips];
a231b88c 964 data->mcp[addr]->irq = spi->irq;
d62b98f3 965 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
3af0dbd5
SZ
966 0x40 | (addr << 1), type, pdata,
967 addr);
8f1cc3b1
DB
968 if (status < 0)
969 goto fail;
0b7bb77f 970
3af0dbd5
SZ
971 if (pdata->base != -1)
972 pdata->base += (type == MCP_TYPE_S17) ? 16 : 8;
97ddb1c8 973 ngpio += (type == MCP_TYPE_S17) ? 16 : 8;
8f1cc3b1 974 }
97ddb1c8 975 data->ngpio = ngpio;
e58b9e27
DB
976
977 /* NOTE: these chips have a relatively sane IRQ framework, with
978 * per-signal masking and level/edge triggering. It's not yet
979 * handled here...
980 */
981
e58b9e27
DB
982 return 0;
983
984fail:
0b7bb77f 985 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
986
987 if (!data->mcp[addr])
988 continue;
9f5132ae 989 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 990 }
e58b9e27
DB
991 return status;
992}
993
994static int mcp23s08_remove(struct spi_device *spi)
995{
8f1cc3b1 996 struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
8f1cc3b1 997 unsigned addr;
e58b9e27 998
0b7bb77f 999 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
1000
1001 if (!data->mcp[addr])
1002 continue;
1003
a231b88c
AS
1004 if (spi->irq && data->mcp[addr]->irq_controller)
1005 mcp23s08_irq_teardown(data->mcp[addr]);
9f5132ae 1006 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 1007 }
c4941e07 1008
9f5132ae 1009 return 0;
e58b9e27
DB
1010}
1011
0b7bb77f
PK
1012static const struct spi_device_id mcp23s08_ids[] = {
1013 { "mcp23s08", MCP_TYPE_S08 },
1014 { "mcp23s17", MCP_TYPE_S17 },
1015 { },
1016};
1017MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
1018
e58b9e27
DB
1019static struct spi_driver mcp23s08_driver = {
1020 .probe = mcp23s08_probe,
1021 .remove = mcp23s08_remove,
0b7bb77f 1022 .id_table = mcp23s08_ids,
e58b9e27
DB
1023 .driver = {
1024 .name = "mcp23s08",
97ddb1c8 1025 .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
e58b9e27
DB
1026 },
1027};
1028
d62b98f3
PK
1029static int __init mcp23s08_spi_init(void)
1030{
1031 return spi_register_driver(&mcp23s08_driver);
1032}
1033
1034static void mcp23s08_spi_exit(void)
1035{
1036 spi_unregister_driver(&mcp23s08_driver);
1037}
1038
1039#else
1040
1041static int __init mcp23s08_spi_init(void) { return 0; }
1042static void mcp23s08_spi_exit(void) { }
1043
1044#endif /* CONFIG_SPI_MASTER */
1045
e58b9e27
DB
1046/*----------------------------------------------------------------------*/
1047
1048static int __init mcp23s08_init(void)
1049{
752ad5e8
PK
1050 int ret;
1051
1052 ret = mcp23s08_spi_init();
1053 if (ret)
1054 goto spi_fail;
1055
1056 ret = mcp23s08_i2c_init();
1057 if (ret)
1058 goto i2c_fail;
1059
1060 return 0;
1061
1062 i2c_fail:
1063 mcp23s08_spi_exit();
1064 spi_fail:
1065 return ret;
e58b9e27 1066}
752ad5e8 1067/* register after spi/i2c postcore initcall and before
673c0c00
DB
1068 * subsys initcalls that may rely on these GPIOs
1069 */
1070subsys_initcall(mcp23s08_init);
e58b9e27
DB
1071
1072static void __exit mcp23s08_exit(void)
1073{
d62b98f3 1074 mcp23s08_spi_exit();
752ad5e8 1075 mcp23s08_i2c_exit();
e58b9e27
DB
1076}
1077module_exit(mcp23s08_exit);
1078
1079MODULE_LICENSE("GPL");