Commit | Line | Data |
---|---|---|
b886d83c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
bbcd6d54 | 2 | /* |
c103de24 | 3 | * MAX732x I2C Port Expander with 8/16 I/O |
bbcd6d54 EM |
4 | * |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * Copyright (C) 2008 Jack Ren <jack.ren@marvell.com> | |
7 | * Copyright (C) 2008 Eric Miao <eric.miao@marvell.com> | |
984f6643 | 8 | * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org> |
bbcd6d54 EM |
9 | * |
10 | * Derived from drivers/gpio/pca953x.c | |
bbcd6d54 EM |
11 | */ |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/string.h> | |
984f6643 | 17 | #include <linux/gpio/driver.h> |
a80a0bbe | 18 | #include <linux/interrupt.h> |
bbcd6d54 | 19 | #include <linux/i2c.h> |
0a848d63 | 20 | #include <linux/platform_data/max732x.h> |
bbcd6d54 EM |
21 | |
22 | /* | |
23 | * Each port of MAX732x (including MAX7319) falls into one of the | |
24 | * following three types: | |
25 | * | |
26 | * - Push Pull Output | |
27 | * - Input | |
28 | * - Open Drain I/O | |
29 | * | |
30 | * designated by 'O', 'I' and 'P' individually according to MAXIM's | |
a80a0bbe MZ |
31 | * datasheets. 'I' and 'P' ports are interrupt capables, some with |
32 | * a dedicated interrupt mask. | |
bbcd6d54 EM |
33 | * |
34 | * There are two groups of I/O ports, each group usually includes | |
35 | * up to 8 I/O ports, and is accessed by a specific I2C address: | |
36 | * | |
37 | * - Group A : by I2C address 0b'110xxxx | |
38 | * - Group B : by I2C address 0b'101xxxx | |
39 | * | |
40 | * where 'xxxx' is decided by the connections of pin AD2/AD0. The | |
41 | * address used also affects the initial state of output signals. | |
42 | * | |
43 | * Within each group of ports, there are five known combinations of | |
44 | * I/O ports: 4I4O, 4P4O, 8I, 8P, 8O, see the definitions below for | |
a80a0bbe MZ |
45 | * the detailed organization of these ports. Only Goup A is interrupt |
46 | * capable. | |
bbcd6d54 EM |
47 | * |
48 | * GPIO numbers start from 'gpio_base + 0' to 'gpio_base + 8/16', | |
49 | * and GPIOs from GROUP_A are numbered before those from GROUP_B | |
50 | * (if there are two groups). | |
51 | * | |
52 | * NOTE: MAX7328/MAX7329 are drop-in replacements for PCF8574/a, so | |
53 | * they are not supported by this driver. | |
54 | */ | |
55 | ||
56 | #define PORT_NONE 0x0 /* '/' No Port */ | |
57 | #define PORT_OUTPUT 0x1 /* 'O' Push-Pull, Output Only */ | |
58 | #define PORT_INPUT 0x2 /* 'I' Input Only */ | |
59 | #define PORT_OPENDRAIN 0x3 /* 'P' Open-Drain, I/O */ | |
60 | ||
61 | #define IO_4I4O 0x5AA5 /* O7 O6 I5 I4 I3 I2 O1 O0 */ | |
62 | #define IO_4P4O 0x5FF5 /* O7 O6 P5 P4 P3 P2 O1 O0 */ | |
63 | #define IO_8I 0xAAAA /* I7 I6 I5 I4 I3 I2 I1 I0 */ | |
64 | #define IO_8P 0xFFFF /* P7 P6 P5 P4 P3 P2 P1 P0 */ | |
65 | #define IO_8O 0x5555 /* O7 O6 O5 O4 O3 O2 O1 O0 */ | |
66 | ||
67 | #define GROUP_A(x) ((x) & 0xffff) /* I2C Addr: 0b'110xxxx */ | |
68 | #define GROUP_B(x) ((x) << 16) /* I2C Addr: 0b'101xxxx */ | |
69 | ||
a80a0bbe MZ |
70 | #define INT_NONE 0x0 /* No interrupt capability */ |
71 | #define INT_NO_MASK 0x1 /* Has interrupts, no mask */ | |
72 | #define INT_INDEP_MASK 0x2 /* Has interrupts, independent mask */ | |
73 | #define INT_MERGED_MASK 0x3 /* Has interrupts, merged mask */ | |
74 | ||
75 | #define INT_CAPS(x) (((uint64_t)(x)) << 32) | |
76 | ||
77 | enum { | |
78 | MAX7319, | |
79 | MAX7320, | |
80 | MAX7321, | |
81 | MAX7322, | |
82 | MAX7323, | |
83 | MAX7324, | |
84 | MAX7325, | |
85 | MAX7326, | |
86 | MAX7327, | |
87 | }; | |
88 | ||
89 | static uint64_t max732x_features[] = { | |
90 | [MAX7319] = GROUP_A(IO_8I) | INT_CAPS(INT_MERGED_MASK), | |
91 | [MAX7320] = GROUP_B(IO_8O), | |
92 | [MAX7321] = GROUP_A(IO_8P) | INT_CAPS(INT_NO_MASK), | |
93 | [MAX7322] = GROUP_A(IO_4I4O) | INT_CAPS(INT_MERGED_MASK), | |
94 | [MAX7323] = GROUP_A(IO_4P4O) | INT_CAPS(INT_INDEP_MASK), | |
95 | [MAX7324] = GROUP_A(IO_8I) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK), | |
96 | [MAX7325] = GROUP_A(IO_8P) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK), | |
97 | [MAX7326] = GROUP_A(IO_4I4O) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK), | |
98 | [MAX7327] = GROUP_A(IO_4P4O) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK), | |
99 | }; | |
100 | ||
bbcd6d54 | 101 | static const struct i2c_device_id max732x_id[] = { |
a80a0bbe MZ |
102 | { "max7319", MAX7319 }, |
103 | { "max7320", MAX7320 }, | |
104 | { "max7321", MAX7321 }, | |
105 | { "max7322", MAX7322 }, | |
106 | { "max7323", MAX7323 }, | |
107 | { "max7324", MAX7324 }, | |
108 | { "max7325", MAX7325 }, | |
109 | { "max7326", MAX7326 }, | |
110 | { "max7327", MAX7327 }, | |
bbcd6d54 EM |
111 | { }, |
112 | }; | |
113 | MODULE_DEVICE_TABLE(i2c, max732x_id); | |
114 | ||
43c4bcf9 SP |
115 | static const struct of_device_id max732x_of_table[] = { |
116 | { .compatible = "maxim,max7319" }, | |
117 | { .compatible = "maxim,max7320" }, | |
118 | { .compatible = "maxim,max7321" }, | |
119 | { .compatible = "maxim,max7322" }, | |
120 | { .compatible = "maxim,max7323" }, | |
121 | { .compatible = "maxim,max7324" }, | |
122 | { .compatible = "maxim,max7325" }, | |
123 | { .compatible = "maxim,max7326" }, | |
124 | { .compatible = "maxim,max7327" }, | |
125 | { } | |
126 | }; | |
127 | MODULE_DEVICE_TABLE(of, max732x_of_table); | |
43c4bcf9 | 128 | |
bbcd6d54 EM |
129 | struct max732x_chip { |
130 | struct gpio_chip gpio_chip; | |
131 | ||
132 | struct i2c_client *client; /* "main" client */ | |
133 | struct i2c_client *client_dummy; | |
134 | struct i2c_client *client_group_a; | |
135 | struct i2c_client *client_group_b; | |
136 | ||
137 | unsigned int mask_group_a; | |
138 | unsigned int dir_input; | |
139 | unsigned int dir_output; | |
140 | ||
141 | struct mutex lock; | |
142 | uint8_t reg_out[2]; | |
a80a0bbe MZ |
143 | |
144 | #ifdef CONFIG_GPIO_MAX732X_IRQ | |
479f8a57 | 145 | struct mutex irq_lock; |
479f8a57 SP |
146 | uint8_t irq_mask; |
147 | uint8_t irq_mask_cur; | |
148 | uint8_t irq_trig_raise; | |
149 | uint8_t irq_trig_fall; | |
150 | uint8_t irq_features; | |
a80a0bbe | 151 | #endif |
bbcd6d54 EM |
152 | }; |
153 | ||
a80a0bbe | 154 | static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val) |
bbcd6d54 EM |
155 | { |
156 | struct i2c_client *client; | |
157 | int ret; | |
158 | ||
159 | client = group_a ? chip->client_group_a : chip->client_group_b; | |
160 | ret = i2c_smbus_write_byte(client, val); | |
161 | if (ret < 0) { | |
162 | dev_err(&client->dev, "failed writing\n"); | |
163 | return ret; | |
164 | } | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
a80a0bbe | 169 | static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val) |
bbcd6d54 EM |
170 | { |
171 | struct i2c_client *client; | |
172 | int ret; | |
173 | ||
174 | client = group_a ? chip->client_group_a : chip->client_group_b; | |
175 | ret = i2c_smbus_read_byte(client); | |
176 | if (ret < 0) { | |
177 | dev_err(&client->dev, "failed reading\n"); | |
178 | return ret; | |
179 | } | |
180 | ||
181 | *val = (uint8_t)ret; | |
182 | return 0; | |
183 | } | |
184 | ||
185 | static inline int is_group_a(struct max732x_chip *chip, unsigned off) | |
186 | { | |
187 | return (1u << off) & chip->mask_group_a; | |
188 | } | |
189 | ||
190 | static int max732x_gpio_get_value(struct gpio_chip *gc, unsigned off) | |
191 | { | |
0788b644 | 192 | struct max732x_chip *chip = gpiochip_get_data(gc); |
bbcd6d54 EM |
193 | uint8_t reg_val; |
194 | int ret; | |
195 | ||
a80a0bbe | 196 | ret = max732x_readb(chip, is_group_a(chip, off), ®_val); |
bbcd6d54 | 197 | if (ret < 0) |
f9660087 | 198 | return ret; |
bbcd6d54 | 199 | |
f9660087 | 200 | return !!(reg_val & (1u << (off & 0x7))); |
bbcd6d54 EM |
201 | } |
202 | ||
161af6cd MR |
203 | static void max732x_gpio_set_mask(struct gpio_chip *gc, unsigned off, int mask, |
204 | int val) | |
bbcd6d54 | 205 | { |
0788b644 | 206 | struct max732x_chip *chip = gpiochip_get_data(gc); |
161af6cd | 207 | uint8_t reg_out; |
bbcd6d54 EM |
208 | int ret; |
209 | ||
bbcd6d54 EM |
210 | mutex_lock(&chip->lock); |
211 | ||
212 | reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0]; | |
161af6cd | 213 | reg_out = (reg_out & ~mask) | (val & mask); |
bbcd6d54 | 214 | |
a80a0bbe | 215 | ret = max732x_writeb(chip, is_group_a(chip, off), reg_out); |
bbcd6d54 EM |
216 | if (ret < 0) |
217 | goto out; | |
218 | ||
219 | /* update the shadow register then */ | |
220 | if (off > 7) | |
221 | chip->reg_out[1] = reg_out; | |
222 | else | |
223 | chip->reg_out[0] = reg_out; | |
224 | out: | |
225 | mutex_unlock(&chip->lock); | |
226 | } | |
227 | ||
66a6d0e5 BG |
228 | static int max732x_gpio_set_value(struct gpio_chip *gc, unsigned int off, |
229 | int val) | |
161af6cd MR |
230 | { |
231 | unsigned base = off & ~0x7; | |
232 | uint8_t mask = 1u << (off & 0x7); | |
233 | ||
234 | max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7)); | |
66a6d0e5 BG |
235 | |
236 | return 0; | |
161af6cd MR |
237 | } |
238 | ||
66a6d0e5 BG |
239 | static int max732x_gpio_set_multiple(struct gpio_chip *gc, |
240 | unsigned long *mask, unsigned long *bits) | |
161af6cd MR |
241 | { |
242 | unsigned mask_lo = mask[0] & 0xff; | |
243 | unsigned mask_hi = (mask[0] >> 8) & 0xff; | |
244 | ||
245 | if (mask_lo) | |
246 | max732x_gpio_set_mask(gc, 0, mask_lo, bits[0] & 0xff); | |
247 | if (mask_hi) | |
248 | max732x_gpio_set_mask(gc, 8, mask_hi, (bits[0] >> 8) & 0xff); | |
66a6d0e5 BG |
249 | |
250 | return 0; | |
161af6cd MR |
251 | } |
252 | ||
bbcd6d54 EM |
253 | static int max732x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
254 | { | |
0788b644 | 255 | struct max732x_chip *chip = gpiochip_get_data(gc); |
bbcd6d54 EM |
256 | unsigned int mask = 1u << off; |
257 | ||
bbcd6d54 EM |
258 | if ((mask & chip->dir_input) == 0) { |
259 | dev_dbg(&chip->client->dev, "%s port %d is output only\n", | |
260 | chip->client->name, off); | |
261 | return -EACCES; | |
262 | } | |
263 | ||
a13c1868 MZ |
264 | /* |
265 | * Open-drain pins must be set to high impedance (which is | |
266 | * equivalent to output-high) to be turned into an input. | |
267 | */ | |
268 | if ((mask & chip->dir_output)) | |
269 | max732x_gpio_set_value(gc, off, 1); | |
270 | ||
bbcd6d54 EM |
271 | return 0; |
272 | } | |
273 | ||
274 | static int max732x_gpio_direction_output(struct gpio_chip *gc, | |
275 | unsigned off, int val) | |
276 | { | |
0788b644 | 277 | struct max732x_chip *chip = gpiochip_get_data(gc); |
bbcd6d54 EM |
278 | unsigned int mask = 1u << off; |
279 | ||
bbcd6d54 EM |
280 | if ((mask & chip->dir_output) == 0) { |
281 | dev_dbg(&chip->client->dev, "%s port %d is input only\n", | |
282 | chip->client->name, off); | |
283 | return -EACCES; | |
284 | } | |
285 | ||
286 | max732x_gpio_set_value(gc, off, val); | |
287 | return 0; | |
288 | } | |
289 | ||
a80a0bbe MZ |
290 | #ifdef CONFIG_GPIO_MAX732X_IRQ |
291 | static int max732x_writew(struct max732x_chip *chip, uint16_t val) | |
292 | { | |
293 | int ret; | |
294 | ||
295 | val = cpu_to_le16(val); | |
296 | ||
297 | ret = i2c_master_send(chip->client_group_a, (char *)&val, 2); | |
298 | if (ret < 0) { | |
299 | dev_err(&chip->client_group_a->dev, "failed writing\n"); | |
300 | return ret; | |
301 | } | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static int max732x_readw(struct max732x_chip *chip, uint16_t *val) | |
307 | { | |
308 | int ret; | |
309 | ||
310 | ret = i2c_master_recv(chip->client_group_a, (char *)val, 2); | |
311 | if (ret < 0) { | |
312 | dev_err(&chip->client_group_a->dev, "failed reading\n"); | |
313 | return ret; | |
314 | } | |
315 | ||
316 | *val = le16_to_cpu(*val); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static void max732x_irq_update_mask(struct max732x_chip *chip) | |
321 | { | |
322 | uint16_t msg; | |
323 | ||
324 | if (chip->irq_mask == chip->irq_mask_cur) | |
325 | return; | |
326 | ||
327 | chip->irq_mask = chip->irq_mask_cur; | |
328 | ||
329 | if (chip->irq_features == INT_NO_MASK) | |
330 | return; | |
331 | ||
332 | mutex_lock(&chip->lock); | |
333 | ||
334 | switch (chip->irq_features) { | |
335 | case INT_INDEP_MASK: | |
336 | msg = (chip->irq_mask << 8) | chip->reg_out[0]; | |
337 | max732x_writew(chip, msg); | |
338 | break; | |
339 | ||
340 | case INT_MERGED_MASK: | |
341 | msg = chip->irq_mask | chip->reg_out[0]; | |
342 | max732x_writeb(chip, 1, (uint8_t)msg); | |
343 | break; | |
344 | } | |
345 | ||
346 | mutex_unlock(&chip->lock); | |
347 | } | |
348 | ||
fbc4667a | 349 | static void max732x_irq_mask(struct irq_data *d) |
a80a0bbe | 350 | { |
984f6643 | 351 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
0788b644 | 352 | struct max732x_chip *chip = gpiochip_get_data(gc); |
a80a0bbe | 353 | |
479f8a57 | 354 | chip->irq_mask_cur &= ~(1 << d->hwirq); |
706cdfc5 | 355 | gpiochip_disable_irq(gc, irqd_to_hwirq(d)); |
a80a0bbe MZ |
356 | } |
357 | ||
fbc4667a | 358 | static void max732x_irq_unmask(struct irq_data *d) |
a80a0bbe | 359 | { |
984f6643 | 360 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
0788b644 | 361 | struct max732x_chip *chip = gpiochip_get_data(gc); |
a80a0bbe | 362 | |
706cdfc5 | 363 | gpiochip_enable_irq(gc, irqd_to_hwirq(d)); |
479f8a57 | 364 | chip->irq_mask_cur |= 1 << d->hwirq; |
a80a0bbe MZ |
365 | } |
366 | ||
fbc4667a | 367 | static void max732x_irq_bus_lock(struct irq_data *d) |
a80a0bbe | 368 | { |
984f6643 | 369 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
0788b644 | 370 | struct max732x_chip *chip = gpiochip_get_data(gc); |
a80a0bbe MZ |
371 | |
372 | mutex_lock(&chip->irq_lock); | |
373 | chip->irq_mask_cur = chip->irq_mask; | |
374 | } | |
375 | ||
fbc4667a | 376 | static void max732x_irq_bus_sync_unlock(struct irq_data *d) |
a80a0bbe | 377 | { |
984f6643 | 378 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
0788b644 | 379 | struct max732x_chip *chip = gpiochip_get_data(gc); |
09afa276 SP |
380 | uint16_t new_irqs; |
381 | uint16_t level; | |
a80a0bbe MZ |
382 | |
383 | max732x_irq_update_mask(chip); | |
09afa276 SP |
384 | |
385 | new_irqs = chip->irq_trig_fall | chip->irq_trig_raise; | |
386 | while (new_irqs) { | |
387 | level = __ffs(new_irqs); | |
388 | max732x_gpio_direction_input(&chip->gpio_chip, level); | |
389 | new_irqs &= ~(1 << level); | |
390 | } | |
391 | ||
a80a0bbe MZ |
392 | mutex_unlock(&chip->irq_lock); |
393 | } | |
394 | ||
fbc4667a | 395 | static int max732x_irq_set_type(struct irq_data *d, unsigned int type) |
a80a0bbe | 396 | { |
984f6643 | 397 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
0788b644 | 398 | struct max732x_chip *chip = gpiochip_get_data(gc); |
479f8a57 | 399 | uint16_t off = d->hwirq; |
a80a0bbe MZ |
400 | uint16_t mask = 1 << off; |
401 | ||
402 | if (!(mask & chip->dir_input)) { | |
403 | dev_dbg(&chip->client->dev, "%s port %d is output only\n", | |
404 | chip->client->name, off); | |
405 | return -EACCES; | |
406 | } | |
407 | ||
408 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
409 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
fbc4667a | 410 | d->irq, type); |
a80a0bbe MZ |
411 | return -EINVAL; |
412 | } | |
413 | ||
414 | if (type & IRQ_TYPE_EDGE_FALLING) | |
415 | chip->irq_trig_fall |= mask; | |
416 | else | |
417 | chip->irq_trig_fall &= ~mask; | |
418 | ||
419 | if (type & IRQ_TYPE_EDGE_RISING) | |
420 | chip->irq_trig_raise |= mask; | |
421 | else | |
422 | chip->irq_trig_raise &= ~mask; | |
423 | ||
09afa276 | 424 | return 0; |
a80a0bbe MZ |
425 | } |
426 | ||
67ddd32b SP |
427 | static int max732x_irq_set_wake(struct irq_data *data, unsigned int on) |
428 | { | |
429 | struct max732x_chip *chip = irq_data_get_irq_chip_data(data); | |
430 | ||
431 | irq_set_irq_wake(chip->client->irq, on); | |
432 | return 0; | |
433 | } | |
434 | ||
706cdfc5 | 435 | static const struct irq_chip max732x_irq_chip = { |
a80a0bbe | 436 | .name = "max732x", |
fbc4667a LB |
437 | .irq_mask = max732x_irq_mask, |
438 | .irq_unmask = max732x_irq_unmask, | |
439 | .irq_bus_lock = max732x_irq_bus_lock, | |
440 | .irq_bus_sync_unlock = max732x_irq_bus_sync_unlock, | |
441 | .irq_set_type = max732x_irq_set_type, | |
67ddd32b | 442 | .irq_set_wake = max732x_irq_set_wake, |
706cdfc5 LW |
443 | .flags = IRQCHIP_IMMUTABLE, |
444 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
a80a0bbe MZ |
445 | }; |
446 | ||
447 | static uint8_t max732x_irq_pending(struct max732x_chip *chip) | |
448 | { | |
449 | uint8_t cur_stat; | |
450 | uint8_t old_stat; | |
451 | uint8_t trigger; | |
452 | uint8_t pending; | |
453 | uint16_t status; | |
454 | int ret; | |
455 | ||
456 | ret = max732x_readw(chip, &status); | |
457 | if (ret) | |
458 | return 0; | |
459 | ||
460 | trigger = status >> 8; | |
461 | trigger &= chip->irq_mask; | |
462 | ||
463 | if (!trigger) | |
464 | return 0; | |
465 | ||
466 | cur_stat = status & 0xFF; | |
467 | cur_stat &= chip->irq_mask; | |
468 | ||
469 | old_stat = cur_stat ^ trigger; | |
470 | ||
471 | pending = (old_stat & chip->irq_trig_fall) | | |
472 | (cur_stat & chip->irq_trig_raise); | |
473 | pending &= trigger; | |
474 | ||
475 | return pending; | |
476 | } | |
477 | ||
478 | static irqreturn_t max732x_irq_handler(int irq, void *devid) | |
479 | { | |
480 | struct max732x_chip *chip = devid; | |
481 | uint8_t pending; | |
482 | uint8_t level; | |
483 | ||
484 | pending = max732x_irq_pending(chip); | |
485 | ||
486 | if (!pending) | |
487 | return IRQ_HANDLED; | |
488 | ||
489 | do { | |
490 | level = __ffs(pending); | |
f0fbe7bc | 491 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, |
984f6643 | 492 | level)); |
a80a0bbe MZ |
493 | |
494 | pending &= ~(1 << level); | |
495 | } while (pending); | |
496 | ||
497 | return IRQ_HANDLED; | |
498 | } | |
499 | ||
500 | static int max732x_irq_setup(struct max732x_chip *chip, | |
501 | const struct i2c_device_id *id) | |
502 | { | |
503 | struct i2c_client *client = chip->client; | |
a80a0bbe | 504 | int has_irq = max732x_features[id->driver_data] >> 32; |
984f6643 | 505 | int irq_base = 0; |
a80a0bbe MZ |
506 | int ret; |
507 | ||
6d5f2207 | 508 | if (client->irq && has_irq != INT_NONE) { |
bb58a47a LW |
509 | struct gpio_irq_chip *girq; |
510 | ||
a80a0bbe MZ |
511 | chip->irq_features = has_irq; |
512 | mutex_init(&chip->irq_lock); | |
513 | ||
68689dbf SP |
514 | ret = devm_request_threaded_irq(&client->dev, client->irq, |
515 | NULL, max732x_irq_handler, IRQF_ONESHOT | | |
516 | IRQF_TRIGGER_FALLING | IRQF_SHARED, | |
517 | dev_name(&client->dev), chip); | |
a80a0bbe MZ |
518 | if (ret) { |
519 | dev_err(&client->dev, "failed to request irq %d\n", | |
520 | client->irq); | |
984f6643 | 521 | return ret; |
a80a0bbe | 522 | } |
bb58a47a LW |
523 | |
524 | girq = &chip->gpio_chip.irq; | |
706cdfc5 | 525 | gpio_irq_chip_set_chip(girq, &max732x_irq_chip); |
bb58a47a LW |
526 | /* This will let us handle the parent IRQ in the driver */ |
527 | girq->parent_handler = NULL; | |
528 | girq->num_parents = 0; | |
529 | girq->parents = NULL; | |
530 | girq->default_type = IRQ_TYPE_NONE; | |
531 | girq->handler = handle_simple_irq; | |
532 | girq->threaded = true; | |
533 | girq->first = irq_base; /* FIXME: get rid of this */ | |
a80a0bbe MZ |
534 | } |
535 | ||
536 | return 0; | |
a80a0bbe MZ |
537 | } |
538 | ||
a80a0bbe MZ |
539 | #else /* CONFIG_GPIO_MAX732X_IRQ */ |
540 | static int max732x_irq_setup(struct max732x_chip *chip, | |
541 | const struct i2c_device_id *id) | |
542 | { | |
543 | struct i2c_client *client = chip->client; | |
a80a0bbe MZ |
544 | int has_irq = max732x_features[id->driver_data] >> 32; |
545 | ||
6d5f2207 | 546 | if (client->irq && has_irq != INT_NONE) |
a80a0bbe MZ |
547 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
548 | ||
549 | return 0; | |
550 | } | |
a80a0bbe MZ |
551 | #endif |
552 | ||
3836309d | 553 | static int max732x_setup_gpio(struct max732x_chip *chip, |
bbcd6d54 EM |
554 | const struct i2c_device_id *id, |
555 | unsigned gpio_start) | |
556 | { | |
557 | struct gpio_chip *gc = &chip->gpio_chip; | |
a80a0bbe | 558 | uint32_t id_data = (uint32_t)max732x_features[id->driver_data]; |
bbcd6d54 EM |
559 | int i, port = 0; |
560 | ||
561 | for (i = 0; i < 16; i++, id_data >>= 2) { | |
562 | unsigned int mask = 1 << port; | |
563 | ||
564 | switch (id_data & 0x3) { | |
565 | case PORT_OUTPUT: | |
566 | chip->dir_output |= mask; | |
567 | break; | |
568 | case PORT_INPUT: | |
569 | chip->dir_input |= mask; | |
570 | break; | |
571 | case PORT_OPENDRAIN: | |
572 | chip->dir_output |= mask; | |
573 | chip->dir_input |= mask; | |
574 | break; | |
575 | default: | |
576 | continue; | |
577 | } | |
578 | ||
579 | if (i < 8) | |
580 | chip->mask_group_a |= mask; | |
581 | port++; | |
582 | } | |
583 | ||
584 | if (chip->dir_input) | |
585 | gc->direction_input = max732x_gpio_direction_input; | |
586 | if (chip->dir_output) { | |
587 | gc->direction_output = max732x_gpio_direction_output; | |
66a6d0e5 BG |
588 | gc->set_rv = max732x_gpio_set_value; |
589 | gc->set_multiple_rv = max732x_gpio_set_multiple; | |
bbcd6d54 EM |
590 | } |
591 | gc->get = max732x_gpio_get_value; | |
9fb1f39e | 592 | gc->can_sleep = true; |
bbcd6d54 EM |
593 | |
594 | gc->base = gpio_start; | |
595 | gc->ngpio = port; | |
596 | gc->label = chip->client->name; | |
58383c78 | 597 | gc->parent = &chip->client->dev; |
bbcd6d54 EM |
598 | gc->owner = THIS_MODULE; |
599 | ||
600 | return port; | |
601 | } | |
602 | ||
43c4bcf9 SP |
603 | static struct max732x_platform_data *of_gpio_max732x(struct device *dev) |
604 | { | |
605 | struct max732x_platform_data *pdata; | |
606 | ||
607 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
608 | if (!pdata) | |
609 | return NULL; | |
610 | ||
611 | pdata->gpio_base = -1; | |
612 | ||
613 | return pdata; | |
614 | } | |
615 | ||
8ac813f7 | 616 | static int max732x_probe(struct i2c_client *client) |
bbcd6d54 | 617 | { |
8ac813f7 | 618 | const struct i2c_device_id *id = i2c_client_get_device_id(client); |
bbcd6d54 | 619 | struct max732x_platform_data *pdata; |
43c4bcf9 | 620 | struct device_node *node; |
bbcd6d54 EM |
621 | struct max732x_chip *chip; |
622 | struct i2c_client *c; | |
623 | uint16_t addr_a, addr_b; | |
624 | int ret, nr_port; | |
625 | ||
e56aee18 | 626 | pdata = dev_get_platdata(&client->dev); |
43c4bcf9 SP |
627 | node = client->dev.of_node; |
628 | ||
629 | if (!pdata && node) | |
630 | pdata = of_gpio_max732x(&client->dev); | |
631 | ||
632 | if (!pdata) { | |
a342d215 BD |
633 | dev_dbg(&client->dev, "no platform data\n"); |
634 | return -EINVAL; | |
635 | } | |
bbcd6d54 | 636 | |
43c4bcf9 | 637 | chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); |
bbcd6d54 EM |
638 | if (chip == NULL) |
639 | return -ENOMEM; | |
640 | chip->client = client; | |
641 | ||
642 | nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base); | |
58383c78 | 643 | chip->gpio_chip.parent = &client->dev; |
bbcd6d54 EM |
644 | |
645 | addr_a = (client->addr & 0x0f) | 0x60; | |
646 | addr_b = (client->addr & 0x0f) | 0x50; | |
647 | ||
648 | switch (client->addr & 0x70) { | |
649 | case 0x60: | |
650 | chip->client_group_a = client; | |
5535cb68 | 651 | if (nr_port > 8) { |
375b9424 BG |
652 | c = devm_i2c_new_dummy_device(&client->dev, |
653 | client->adapter, addr_b); | |
654 | if (IS_ERR(c)) { | |
f3a049e7 ZJ |
655 | dev_err(&client->dev, |
656 | "Failed to allocate I2C device\n"); | |
375b9424 | 657 | return PTR_ERR(c); |
f3a049e7 | 658 | } |
bbcd6d54 EM |
659 | chip->client_group_b = chip->client_dummy = c; |
660 | } | |
661 | break; | |
662 | case 0x50: | |
663 | chip->client_group_b = client; | |
5535cb68 | 664 | if (nr_port > 8) { |
375b9424 BG |
665 | c = devm_i2c_new_dummy_device(&client->dev, |
666 | client->adapter, addr_a); | |
667 | if (IS_ERR(c)) { | |
f3a049e7 ZJ |
668 | dev_err(&client->dev, |
669 | "Failed to allocate I2C device\n"); | |
375b9424 | 670 | return PTR_ERR(c); |
f3a049e7 | 671 | } |
bbcd6d54 EM |
672 | chip->client_group_a = chip->client_dummy = c; |
673 | } | |
674 | break; | |
675 | default: | |
676 | dev_err(&client->dev, "invalid I2C address specified %02x\n", | |
677 | client->addr); | |
375b9424 | 678 | return -EINVAL; |
f561b423 KK |
679 | } |
680 | ||
681 | if (nr_port > 8 && !chip->client_dummy) { | |
682 | dev_err(&client->dev, | |
683 | "Failed to allocate second group I2C device\n"); | |
375b9424 | 684 | return -ENODEV; |
bbcd6d54 EM |
685 | } |
686 | ||
687 | mutex_init(&chip->lock); | |
688 | ||
78de5d52 NK |
689 | ret = max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]); |
690 | if (ret) | |
375b9424 | 691 | return ret; |
78de5d52 NK |
692 | if (nr_port > 8) { |
693 | ret = max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]); | |
694 | if (ret) | |
375b9424 | 695 | return ret; |
78de5d52 | 696 | } |
a80a0bbe | 697 | |
bb58a47a | 698 | ret = max732x_irq_setup(chip, id); |
a80a0bbe | 699 | if (ret) |
375b9424 | 700 | return ret; |
bbcd6d54 | 701 | |
bb58a47a | 702 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
2674700c | 703 | if (ret) |
375b9424 | 704 | return ret; |
bbcd6d54 | 705 | |
bbcd6d54 EM |
706 | i2c_set_clientdata(client, chip); |
707 | return 0; | |
bbcd6d54 EM |
708 | } |
709 | ||
bbcd6d54 EM |
710 | static struct i2c_driver max732x_driver = { |
711 | .driver = { | |
43c4bcf9 | 712 | .name = "max732x", |
9c573074 | 713 | .of_match_table = max732x_of_table, |
bbcd6d54 | 714 | }, |
b41cabb7 | 715 | .probe = max732x_probe, |
bbcd6d54 EM |
716 | .id_table = max732x_id, |
717 | }; | |
718 | ||
719 | static int __init max732x_init(void) | |
720 | { | |
721 | return i2c_add_driver(&max732x_driver); | |
722 | } | |
2f8d1197 DB |
723 | /* register after i2c postcore initcall and before |
724 | * subsys initcalls that may rely on these GPIOs | |
725 | */ | |
726 | subsys_initcall(max732x_init); | |
bbcd6d54 EM |
727 | |
728 | static void __exit max732x_exit(void) | |
729 | { | |
730 | i2c_del_driver(&max732x_driver); | |
731 | } | |
732 | module_exit(max732x_exit); | |
733 | ||
734 | MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>"); | |
735 | MODULE_DESCRIPTION("GPIO expander driver for MAX732X"); | |
736 | MODULE_LICENSE("GPL"); |