Merge tag 'ubifs-for-linus-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / gpio / gpio-max732x.c
CommitLineData
b886d83c 1// SPDX-License-Identifier: GPL-2.0-only
bbcd6d54 2/*
c103de24 3 * MAX732x I2C Port Expander with 8/16 I/O
bbcd6d54
EM
4 *
5 * Copyright (C) 2007 Marvell International Ltd.
6 * Copyright (C) 2008 Jack Ren <jack.ren@marvell.com>
7 * Copyright (C) 2008 Eric Miao <eric.miao@marvell.com>
984f6643 8 * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org>
bbcd6d54
EM
9 *
10 * Derived from drivers/gpio/pca953x.c
bbcd6d54
EM
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/string.h>
984f6643 17#include <linux/gpio/driver.h>
a80a0bbe 18#include <linux/interrupt.h>
bbcd6d54 19#include <linux/i2c.h>
0a848d63 20#include <linux/platform_data/max732x.h>
bbcd6d54
EM
21
22/*
23 * Each port of MAX732x (including MAX7319) falls into one of the
24 * following three types:
25 *
26 * - Push Pull Output
27 * - Input
28 * - Open Drain I/O
29 *
30 * designated by 'O', 'I' and 'P' individually according to MAXIM's
a80a0bbe
MZ
31 * datasheets. 'I' and 'P' ports are interrupt capables, some with
32 * a dedicated interrupt mask.
bbcd6d54
EM
33 *
34 * There are two groups of I/O ports, each group usually includes
35 * up to 8 I/O ports, and is accessed by a specific I2C address:
36 *
37 * - Group A : by I2C address 0b'110xxxx
38 * - Group B : by I2C address 0b'101xxxx
39 *
40 * where 'xxxx' is decided by the connections of pin AD2/AD0. The
41 * address used also affects the initial state of output signals.
42 *
43 * Within each group of ports, there are five known combinations of
44 * I/O ports: 4I4O, 4P4O, 8I, 8P, 8O, see the definitions below for
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45 * the detailed organization of these ports. Only Goup A is interrupt
46 * capable.
bbcd6d54
EM
47 *
48 * GPIO numbers start from 'gpio_base + 0' to 'gpio_base + 8/16',
49 * and GPIOs from GROUP_A are numbered before those from GROUP_B
50 * (if there are two groups).
51 *
52 * NOTE: MAX7328/MAX7329 are drop-in replacements for PCF8574/a, so
53 * they are not supported by this driver.
54 */
55
56#define PORT_NONE 0x0 /* '/' No Port */
57#define PORT_OUTPUT 0x1 /* 'O' Push-Pull, Output Only */
58#define PORT_INPUT 0x2 /* 'I' Input Only */
59#define PORT_OPENDRAIN 0x3 /* 'P' Open-Drain, I/O */
60
61#define IO_4I4O 0x5AA5 /* O7 O6 I5 I4 I3 I2 O1 O0 */
62#define IO_4P4O 0x5FF5 /* O7 O6 P5 P4 P3 P2 O1 O0 */
63#define IO_8I 0xAAAA /* I7 I6 I5 I4 I3 I2 I1 I0 */
64#define IO_8P 0xFFFF /* P7 P6 P5 P4 P3 P2 P1 P0 */
65#define IO_8O 0x5555 /* O7 O6 O5 O4 O3 O2 O1 O0 */
66
67#define GROUP_A(x) ((x) & 0xffff) /* I2C Addr: 0b'110xxxx */
68#define GROUP_B(x) ((x) << 16) /* I2C Addr: 0b'101xxxx */
69
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70#define INT_NONE 0x0 /* No interrupt capability */
71#define INT_NO_MASK 0x1 /* Has interrupts, no mask */
72#define INT_INDEP_MASK 0x2 /* Has interrupts, independent mask */
73#define INT_MERGED_MASK 0x3 /* Has interrupts, merged mask */
74
75#define INT_CAPS(x) (((uint64_t)(x)) << 32)
76
77enum {
78 MAX7319,
79 MAX7320,
80 MAX7321,
81 MAX7322,
82 MAX7323,
83 MAX7324,
84 MAX7325,
85 MAX7326,
86 MAX7327,
87};
88
89static uint64_t max732x_features[] = {
90 [MAX7319] = GROUP_A(IO_8I) | INT_CAPS(INT_MERGED_MASK),
91 [MAX7320] = GROUP_B(IO_8O),
92 [MAX7321] = GROUP_A(IO_8P) | INT_CAPS(INT_NO_MASK),
93 [MAX7322] = GROUP_A(IO_4I4O) | INT_CAPS(INT_MERGED_MASK),
94 [MAX7323] = GROUP_A(IO_4P4O) | INT_CAPS(INT_INDEP_MASK),
95 [MAX7324] = GROUP_A(IO_8I) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
96 [MAX7325] = GROUP_A(IO_8P) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
97 [MAX7326] = GROUP_A(IO_4I4O) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
98 [MAX7327] = GROUP_A(IO_4P4O) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
99};
100
bbcd6d54 101static const struct i2c_device_id max732x_id[] = {
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MZ
102 { "max7319", MAX7319 },
103 { "max7320", MAX7320 },
104 { "max7321", MAX7321 },
105 { "max7322", MAX7322 },
106 { "max7323", MAX7323 },
107 { "max7324", MAX7324 },
108 { "max7325", MAX7325 },
109 { "max7326", MAX7326 },
110 { "max7327", MAX7327 },
bbcd6d54
EM
111 { },
112};
113MODULE_DEVICE_TABLE(i2c, max732x_id);
114
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SP
115static const struct of_device_id max732x_of_table[] = {
116 { .compatible = "maxim,max7319" },
117 { .compatible = "maxim,max7320" },
118 { .compatible = "maxim,max7321" },
119 { .compatible = "maxim,max7322" },
120 { .compatible = "maxim,max7323" },
121 { .compatible = "maxim,max7324" },
122 { .compatible = "maxim,max7325" },
123 { .compatible = "maxim,max7326" },
124 { .compatible = "maxim,max7327" },
125 { }
126};
127MODULE_DEVICE_TABLE(of, max732x_of_table);
43c4bcf9 128
bbcd6d54
EM
129struct max732x_chip {
130 struct gpio_chip gpio_chip;
131
132 struct i2c_client *client; /* "main" client */
133 struct i2c_client *client_dummy;
134 struct i2c_client *client_group_a;
135 struct i2c_client *client_group_b;
136
137 unsigned int mask_group_a;
138 unsigned int dir_input;
139 unsigned int dir_output;
140
141 struct mutex lock;
142 uint8_t reg_out[2];
a80a0bbe
MZ
143
144#ifdef CONFIG_GPIO_MAX732X_IRQ
479f8a57 145 struct mutex irq_lock;
479f8a57
SP
146 uint8_t irq_mask;
147 uint8_t irq_mask_cur;
148 uint8_t irq_trig_raise;
149 uint8_t irq_trig_fall;
150 uint8_t irq_features;
a80a0bbe 151#endif
bbcd6d54
EM
152};
153
a80a0bbe 154static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val)
bbcd6d54
EM
155{
156 struct i2c_client *client;
157 int ret;
158
159 client = group_a ? chip->client_group_a : chip->client_group_b;
160 ret = i2c_smbus_write_byte(client, val);
161 if (ret < 0) {
162 dev_err(&client->dev, "failed writing\n");
163 return ret;
164 }
165
166 return 0;
167}
168
a80a0bbe 169static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val)
bbcd6d54
EM
170{
171 struct i2c_client *client;
172 int ret;
173
174 client = group_a ? chip->client_group_a : chip->client_group_b;
175 ret = i2c_smbus_read_byte(client);
176 if (ret < 0) {
177 dev_err(&client->dev, "failed reading\n");
178 return ret;
179 }
180
181 *val = (uint8_t)ret;
182 return 0;
183}
184
185static inline int is_group_a(struct max732x_chip *chip, unsigned off)
186{
187 return (1u << off) & chip->mask_group_a;
188}
189
190static int max732x_gpio_get_value(struct gpio_chip *gc, unsigned off)
191{
0788b644 192 struct max732x_chip *chip = gpiochip_get_data(gc);
bbcd6d54
EM
193 uint8_t reg_val;
194 int ret;
195
a80a0bbe 196 ret = max732x_readb(chip, is_group_a(chip, off), &reg_val);
bbcd6d54 197 if (ret < 0)
f9660087 198 return ret;
bbcd6d54 199
f9660087 200 return !!(reg_val & (1u << (off & 0x7)));
bbcd6d54
EM
201}
202
161af6cd
MR
203static void max732x_gpio_set_mask(struct gpio_chip *gc, unsigned off, int mask,
204 int val)
bbcd6d54 205{
0788b644 206 struct max732x_chip *chip = gpiochip_get_data(gc);
161af6cd 207 uint8_t reg_out;
bbcd6d54
EM
208 int ret;
209
bbcd6d54
EM
210 mutex_lock(&chip->lock);
211
212 reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0];
161af6cd 213 reg_out = (reg_out & ~mask) | (val & mask);
bbcd6d54 214
a80a0bbe 215 ret = max732x_writeb(chip, is_group_a(chip, off), reg_out);
bbcd6d54
EM
216 if (ret < 0)
217 goto out;
218
219 /* update the shadow register then */
220 if (off > 7)
221 chip->reg_out[1] = reg_out;
222 else
223 chip->reg_out[0] = reg_out;
224out:
225 mutex_unlock(&chip->lock);
226}
227
161af6cd
MR
228static void max732x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
229{
230 unsigned base = off & ~0x7;
231 uint8_t mask = 1u << (off & 0x7);
232
233 max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7));
234}
235
236static void max732x_gpio_set_multiple(struct gpio_chip *gc,
237 unsigned long *mask, unsigned long *bits)
238{
239 unsigned mask_lo = mask[0] & 0xff;
240 unsigned mask_hi = (mask[0] >> 8) & 0xff;
241
242 if (mask_lo)
243 max732x_gpio_set_mask(gc, 0, mask_lo, bits[0] & 0xff);
244 if (mask_hi)
245 max732x_gpio_set_mask(gc, 8, mask_hi, (bits[0] >> 8) & 0xff);
246}
247
bbcd6d54
EM
248static int max732x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
249{
0788b644 250 struct max732x_chip *chip = gpiochip_get_data(gc);
bbcd6d54
EM
251 unsigned int mask = 1u << off;
252
bbcd6d54
EM
253 if ((mask & chip->dir_input) == 0) {
254 dev_dbg(&chip->client->dev, "%s port %d is output only\n",
255 chip->client->name, off);
256 return -EACCES;
257 }
258
a13c1868
MZ
259 /*
260 * Open-drain pins must be set to high impedance (which is
261 * equivalent to output-high) to be turned into an input.
262 */
263 if ((mask & chip->dir_output))
264 max732x_gpio_set_value(gc, off, 1);
265
bbcd6d54
EM
266 return 0;
267}
268
269static int max732x_gpio_direction_output(struct gpio_chip *gc,
270 unsigned off, int val)
271{
0788b644 272 struct max732x_chip *chip = gpiochip_get_data(gc);
bbcd6d54
EM
273 unsigned int mask = 1u << off;
274
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EM
275 if ((mask & chip->dir_output) == 0) {
276 dev_dbg(&chip->client->dev, "%s port %d is input only\n",
277 chip->client->name, off);
278 return -EACCES;
279 }
280
281 max732x_gpio_set_value(gc, off, val);
282 return 0;
283}
284
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MZ
285#ifdef CONFIG_GPIO_MAX732X_IRQ
286static int max732x_writew(struct max732x_chip *chip, uint16_t val)
287{
288 int ret;
289
290 val = cpu_to_le16(val);
291
292 ret = i2c_master_send(chip->client_group_a, (char *)&val, 2);
293 if (ret < 0) {
294 dev_err(&chip->client_group_a->dev, "failed writing\n");
295 return ret;
296 }
297
298 return 0;
299}
300
301static int max732x_readw(struct max732x_chip *chip, uint16_t *val)
302{
303 int ret;
304
305 ret = i2c_master_recv(chip->client_group_a, (char *)val, 2);
306 if (ret < 0) {
307 dev_err(&chip->client_group_a->dev, "failed reading\n");
308 return ret;
309 }
310
311 *val = le16_to_cpu(*val);
312 return 0;
313}
314
315static void max732x_irq_update_mask(struct max732x_chip *chip)
316{
317 uint16_t msg;
318
319 if (chip->irq_mask == chip->irq_mask_cur)
320 return;
321
322 chip->irq_mask = chip->irq_mask_cur;
323
324 if (chip->irq_features == INT_NO_MASK)
325 return;
326
327 mutex_lock(&chip->lock);
328
329 switch (chip->irq_features) {
330 case INT_INDEP_MASK:
331 msg = (chip->irq_mask << 8) | chip->reg_out[0];
332 max732x_writew(chip, msg);
333 break;
334
335 case INT_MERGED_MASK:
336 msg = chip->irq_mask | chip->reg_out[0];
337 max732x_writeb(chip, 1, (uint8_t)msg);
338 break;
339 }
340
341 mutex_unlock(&chip->lock);
342}
343
fbc4667a 344static void max732x_irq_mask(struct irq_data *d)
a80a0bbe 345{
984f6643 346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0788b644 347 struct max732x_chip *chip = gpiochip_get_data(gc);
a80a0bbe 348
479f8a57 349 chip->irq_mask_cur &= ~(1 << d->hwirq);
706cdfc5 350 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
a80a0bbe
MZ
351}
352
fbc4667a 353static void max732x_irq_unmask(struct irq_data *d)
a80a0bbe 354{
984f6643 355 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0788b644 356 struct max732x_chip *chip = gpiochip_get_data(gc);
a80a0bbe 357
706cdfc5 358 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
479f8a57 359 chip->irq_mask_cur |= 1 << d->hwirq;
a80a0bbe
MZ
360}
361
fbc4667a 362static void max732x_irq_bus_lock(struct irq_data *d)
a80a0bbe 363{
984f6643 364 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0788b644 365 struct max732x_chip *chip = gpiochip_get_data(gc);
a80a0bbe
MZ
366
367 mutex_lock(&chip->irq_lock);
368 chip->irq_mask_cur = chip->irq_mask;
369}
370
fbc4667a 371static void max732x_irq_bus_sync_unlock(struct irq_data *d)
a80a0bbe 372{
984f6643 373 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0788b644 374 struct max732x_chip *chip = gpiochip_get_data(gc);
09afa276
SP
375 uint16_t new_irqs;
376 uint16_t level;
a80a0bbe
MZ
377
378 max732x_irq_update_mask(chip);
09afa276
SP
379
380 new_irqs = chip->irq_trig_fall | chip->irq_trig_raise;
381 while (new_irqs) {
382 level = __ffs(new_irqs);
383 max732x_gpio_direction_input(&chip->gpio_chip, level);
384 new_irqs &= ~(1 << level);
385 }
386
a80a0bbe
MZ
387 mutex_unlock(&chip->irq_lock);
388}
389
fbc4667a 390static int max732x_irq_set_type(struct irq_data *d, unsigned int type)
a80a0bbe 391{
984f6643 392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0788b644 393 struct max732x_chip *chip = gpiochip_get_data(gc);
479f8a57 394 uint16_t off = d->hwirq;
a80a0bbe
MZ
395 uint16_t mask = 1 << off;
396
397 if (!(mask & chip->dir_input)) {
398 dev_dbg(&chip->client->dev, "%s port %d is output only\n",
399 chip->client->name, off);
400 return -EACCES;
401 }
402
403 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
404 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
fbc4667a 405 d->irq, type);
a80a0bbe
MZ
406 return -EINVAL;
407 }
408
409 if (type & IRQ_TYPE_EDGE_FALLING)
410 chip->irq_trig_fall |= mask;
411 else
412 chip->irq_trig_fall &= ~mask;
413
414 if (type & IRQ_TYPE_EDGE_RISING)
415 chip->irq_trig_raise |= mask;
416 else
417 chip->irq_trig_raise &= ~mask;
418
09afa276 419 return 0;
a80a0bbe
MZ
420}
421
67ddd32b
SP
422static int max732x_irq_set_wake(struct irq_data *data, unsigned int on)
423{
424 struct max732x_chip *chip = irq_data_get_irq_chip_data(data);
425
426 irq_set_irq_wake(chip->client->irq, on);
427 return 0;
428}
429
706cdfc5 430static const struct irq_chip max732x_irq_chip = {
a80a0bbe 431 .name = "max732x",
fbc4667a
LB
432 .irq_mask = max732x_irq_mask,
433 .irq_unmask = max732x_irq_unmask,
434 .irq_bus_lock = max732x_irq_bus_lock,
435 .irq_bus_sync_unlock = max732x_irq_bus_sync_unlock,
436 .irq_set_type = max732x_irq_set_type,
67ddd32b 437 .irq_set_wake = max732x_irq_set_wake,
706cdfc5
LW
438 .flags = IRQCHIP_IMMUTABLE,
439 GPIOCHIP_IRQ_RESOURCE_HELPERS,
a80a0bbe
MZ
440};
441
442static uint8_t max732x_irq_pending(struct max732x_chip *chip)
443{
444 uint8_t cur_stat;
445 uint8_t old_stat;
446 uint8_t trigger;
447 uint8_t pending;
448 uint16_t status;
449 int ret;
450
451 ret = max732x_readw(chip, &status);
452 if (ret)
453 return 0;
454
455 trigger = status >> 8;
456 trigger &= chip->irq_mask;
457
458 if (!trigger)
459 return 0;
460
461 cur_stat = status & 0xFF;
462 cur_stat &= chip->irq_mask;
463
464 old_stat = cur_stat ^ trigger;
465
466 pending = (old_stat & chip->irq_trig_fall) |
467 (cur_stat & chip->irq_trig_raise);
468 pending &= trigger;
469
470 return pending;
471}
472
473static irqreturn_t max732x_irq_handler(int irq, void *devid)
474{
475 struct max732x_chip *chip = devid;
476 uint8_t pending;
477 uint8_t level;
478
479 pending = max732x_irq_pending(chip);
480
481 if (!pending)
482 return IRQ_HANDLED;
483
484 do {
485 level = __ffs(pending);
f0fbe7bc 486 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
984f6643 487 level));
a80a0bbe
MZ
488
489 pending &= ~(1 << level);
490 } while (pending);
491
492 return IRQ_HANDLED;
493}
494
495static int max732x_irq_setup(struct max732x_chip *chip,
496 const struct i2c_device_id *id)
497{
498 struct i2c_client *client = chip->client;
a80a0bbe 499 int has_irq = max732x_features[id->driver_data] >> 32;
984f6643 500 int irq_base = 0;
a80a0bbe
MZ
501 int ret;
502
6d5f2207 503 if (client->irq && has_irq != INT_NONE) {
bb58a47a
LW
504 struct gpio_irq_chip *girq;
505
a80a0bbe
MZ
506 chip->irq_features = has_irq;
507 mutex_init(&chip->irq_lock);
508
68689dbf
SP
509 ret = devm_request_threaded_irq(&client->dev, client->irq,
510 NULL, max732x_irq_handler, IRQF_ONESHOT |
511 IRQF_TRIGGER_FALLING | IRQF_SHARED,
512 dev_name(&client->dev), chip);
a80a0bbe
MZ
513 if (ret) {
514 dev_err(&client->dev, "failed to request irq %d\n",
515 client->irq);
984f6643 516 return ret;
a80a0bbe 517 }
bb58a47a
LW
518
519 girq = &chip->gpio_chip.irq;
706cdfc5 520 gpio_irq_chip_set_chip(girq, &max732x_irq_chip);
bb58a47a
LW
521 /* This will let us handle the parent IRQ in the driver */
522 girq->parent_handler = NULL;
523 girq->num_parents = 0;
524 girq->parents = NULL;
525 girq->default_type = IRQ_TYPE_NONE;
526 girq->handler = handle_simple_irq;
527 girq->threaded = true;
528 girq->first = irq_base; /* FIXME: get rid of this */
a80a0bbe
MZ
529 }
530
531 return 0;
a80a0bbe
MZ
532}
533
a80a0bbe
MZ
534#else /* CONFIG_GPIO_MAX732X_IRQ */
535static int max732x_irq_setup(struct max732x_chip *chip,
536 const struct i2c_device_id *id)
537{
538 struct i2c_client *client = chip->client;
a80a0bbe
MZ
539 int has_irq = max732x_features[id->driver_data] >> 32;
540
6d5f2207 541 if (client->irq && has_irq != INT_NONE)
a80a0bbe
MZ
542 dev_warn(&client->dev, "interrupt support not compiled in\n");
543
544 return 0;
545}
a80a0bbe
MZ
546#endif
547
3836309d 548static int max732x_setup_gpio(struct max732x_chip *chip,
bbcd6d54
EM
549 const struct i2c_device_id *id,
550 unsigned gpio_start)
551{
552 struct gpio_chip *gc = &chip->gpio_chip;
a80a0bbe 553 uint32_t id_data = (uint32_t)max732x_features[id->driver_data];
bbcd6d54
EM
554 int i, port = 0;
555
556 for (i = 0; i < 16; i++, id_data >>= 2) {
557 unsigned int mask = 1 << port;
558
559 switch (id_data & 0x3) {
560 case PORT_OUTPUT:
561 chip->dir_output |= mask;
562 break;
563 case PORT_INPUT:
564 chip->dir_input |= mask;
565 break;
566 case PORT_OPENDRAIN:
567 chip->dir_output |= mask;
568 chip->dir_input |= mask;
569 break;
570 default:
571 continue;
572 }
573
574 if (i < 8)
575 chip->mask_group_a |= mask;
576 port++;
577 }
578
579 if (chip->dir_input)
580 gc->direction_input = max732x_gpio_direction_input;
581 if (chip->dir_output) {
582 gc->direction_output = max732x_gpio_direction_output;
583 gc->set = max732x_gpio_set_value;
161af6cd 584 gc->set_multiple = max732x_gpio_set_multiple;
bbcd6d54
EM
585 }
586 gc->get = max732x_gpio_get_value;
9fb1f39e 587 gc->can_sleep = true;
bbcd6d54
EM
588
589 gc->base = gpio_start;
590 gc->ngpio = port;
591 gc->label = chip->client->name;
58383c78 592 gc->parent = &chip->client->dev;
bbcd6d54
EM
593 gc->owner = THIS_MODULE;
594
595 return port;
596}
597
43c4bcf9
SP
598static struct max732x_platform_data *of_gpio_max732x(struct device *dev)
599{
600 struct max732x_platform_data *pdata;
601
602 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
603 if (!pdata)
604 return NULL;
605
606 pdata->gpio_base = -1;
607
608 return pdata;
609}
610
8ac813f7 611static int max732x_probe(struct i2c_client *client)
bbcd6d54 612{
8ac813f7 613 const struct i2c_device_id *id = i2c_client_get_device_id(client);
bbcd6d54 614 struct max732x_platform_data *pdata;
43c4bcf9 615 struct device_node *node;
bbcd6d54
EM
616 struct max732x_chip *chip;
617 struct i2c_client *c;
618 uint16_t addr_a, addr_b;
619 int ret, nr_port;
620
e56aee18 621 pdata = dev_get_platdata(&client->dev);
43c4bcf9
SP
622 node = client->dev.of_node;
623
624 if (!pdata && node)
625 pdata = of_gpio_max732x(&client->dev);
626
627 if (!pdata) {
a342d215
BD
628 dev_dbg(&client->dev, "no platform data\n");
629 return -EINVAL;
630 }
bbcd6d54 631
43c4bcf9 632 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
bbcd6d54
EM
633 if (chip == NULL)
634 return -ENOMEM;
635 chip->client = client;
636
637 nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base);
58383c78 638 chip->gpio_chip.parent = &client->dev;
bbcd6d54
EM
639
640 addr_a = (client->addr & 0x0f) | 0x60;
641 addr_b = (client->addr & 0x0f) | 0x50;
642
643 switch (client->addr & 0x70) {
644 case 0x60:
645 chip->client_group_a = client;
5535cb68 646 if (nr_port > 8) {
375b9424
BG
647 c = devm_i2c_new_dummy_device(&client->dev,
648 client->adapter, addr_b);
649 if (IS_ERR(c)) {
f3a049e7
ZJ
650 dev_err(&client->dev,
651 "Failed to allocate I2C device\n");
375b9424 652 return PTR_ERR(c);
f3a049e7 653 }
bbcd6d54
EM
654 chip->client_group_b = chip->client_dummy = c;
655 }
656 break;
657 case 0x50:
658 chip->client_group_b = client;
5535cb68 659 if (nr_port > 8) {
375b9424
BG
660 c = devm_i2c_new_dummy_device(&client->dev,
661 client->adapter, addr_a);
662 if (IS_ERR(c)) {
f3a049e7
ZJ
663 dev_err(&client->dev,
664 "Failed to allocate I2C device\n");
375b9424 665 return PTR_ERR(c);
f3a049e7 666 }
bbcd6d54
EM
667 chip->client_group_a = chip->client_dummy = c;
668 }
669 break;
670 default:
671 dev_err(&client->dev, "invalid I2C address specified %02x\n",
672 client->addr);
375b9424 673 return -EINVAL;
f561b423
KK
674 }
675
676 if (nr_port > 8 && !chip->client_dummy) {
677 dev_err(&client->dev,
678 "Failed to allocate second group I2C device\n");
375b9424 679 return -ENODEV;
bbcd6d54
EM
680 }
681
682 mutex_init(&chip->lock);
683
78de5d52
NK
684 ret = max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]);
685 if (ret)
375b9424 686 return ret;
78de5d52
NK
687 if (nr_port > 8) {
688 ret = max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]);
689 if (ret)
375b9424 690 return ret;
78de5d52 691 }
a80a0bbe 692
bb58a47a 693 ret = max732x_irq_setup(chip, id);
a80a0bbe 694 if (ret)
375b9424 695 return ret;
bbcd6d54 696
bb58a47a 697 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
2674700c 698 if (ret)
375b9424 699 return ret;
bbcd6d54 700
bbcd6d54
EM
701 i2c_set_clientdata(client, chip);
702 return 0;
bbcd6d54
EM
703}
704
bbcd6d54
EM
705static struct i2c_driver max732x_driver = {
706 .driver = {
43c4bcf9 707 .name = "max732x",
9c573074 708 .of_match_table = max732x_of_table,
bbcd6d54 709 },
b41cabb7 710 .probe = max732x_probe,
bbcd6d54
EM
711 .id_table = max732x_id,
712};
713
714static int __init max732x_init(void)
715{
716 return i2c_add_driver(&max732x_driver);
717}
2f8d1197
DB
718/* register after i2c postcore initcall and before
719 * subsys initcalls that may rely on these GPIOs
720 */
721subsys_initcall(max732x_init);
bbcd6d54
EM
722
723static void __exit max732x_exit(void)
724{
725 i2c_del_driver(&max732x_driver);
726}
727module_exit(max732x_exit);
728
729MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>");
730MODULE_DESCRIPTION("GPIO expander driver for MAX732X");
731MODULE_LICENSE("GPL");