Commit | Line | Data |
---|---|---|
c103de24 GL |
1 | /* |
2 | * Moorestown platform Langwell chip GPIO driver | |
3 | * | |
611a485b | 4 | * Copyright (c) 2008, 2009, 2013, Intel Corporation. |
8bf02617 AD |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* Supports: | |
21 | * Moorestown platform Langwell chip. | |
8081c84c | 22 | * Medfield platform Penwell chip. |
f89a768f DC |
23 | * Clovertrail platform Cloverview chip. |
24 | * Merrifield platform Tangier chip. | |
8bf02617 AD |
25 | */ |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
72b4379e | 29 | #include <linux/platform_device.h> |
8bf02617 AD |
30 | #include <linux/kernel.h> |
31 | #include <linux/delay.h> | |
32 | #include <linux/stddef.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/irq.h> | |
36 | #include <linux/io.h> | |
37 | #include <linux/gpio.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
7812803a | 39 | #include <linux/pm_runtime.h> |
465f2bd4 | 40 | #include <linux/irqdomain.h> |
8bf02617 | 41 | |
f89a768f DC |
42 | #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0) |
43 | #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1) | |
d56d6b3d | 44 | |
8081c84c AD |
45 | /* |
46 | * Langwell chip has 64 pins and thus there are 2 32bit registers to control | |
47 | * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit | |
48 | * registers to control them, so we only define the order here instead of a | |
49 | * structure, to get a bit offset for a pin (use GPDR as an example): | |
50 | * | |
51 | * nreg = ngpio / 32; | |
52 | * reg = offset / 32; | |
53 | * bit = offset % 32; | |
54 | * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4; | |
55 | * | |
56 | * so the bit of reg_addr is to control pin offset's GPDR feature | |
57 | */ | |
58 | ||
59 | enum GPIO_REG { | |
60 | GPLR = 0, /* pin level read-only */ | |
61 | GPDR, /* pin direction */ | |
62 | GPSR, /* pin set */ | |
63 | GPCR, /* pin clear */ | |
64 | GRER, /* rising edge detect */ | |
65 | GFER, /* falling edge detect */ | |
66 | GEDR, /* edge detect result */ | |
8c0f7b10 | 67 | GAFR, /* alt function */ |
8bf02617 AD |
68 | }; |
69 | ||
f89a768f DC |
70 | /* intel_mid gpio driver data */ |
71 | struct intel_mid_gpio_ddata { | |
d56d6b3d DC |
72 | u16 ngpio; /* number of gpio pins */ |
73 | u32 gplr_offset; /* offset of first GPLR register from base */ | |
74 | u32 flis_base; /* base address of FLIS registers */ | |
75 | u32 flis_len; /* length of FLIS registers */ | |
76 | u32 (*get_flis_offset)(int gpio); | |
77 | u32 chip_irq_type; /* chip interrupt type */ | |
78 | }; | |
79 | ||
f89a768f | 80 | struct intel_mid_gpio { |
8bf02617 | 81 | struct gpio_chip chip; |
64c8cbc1 | 82 | void __iomem *reg_base; |
8bf02617 | 83 | spinlock_t lock; |
7812803a | 84 | struct pci_dev *pdev; |
465f2bd4 | 85 | struct irq_domain *domain; |
8bf02617 AD |
86 | }; |
87 | ||
f89a768f | 88 | #define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip) |
46ebfbc3 | 89 | |
8081c84c | 90 | static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, |
611a485b | 91 | enum GPIO_REG reg_type) |
8bf02617 | 92 | { |
f89a768f | 93 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8081c84c | 94 | unsigned nreg = chip->ngpio / 32; |
8bf02617 | 95 | u8 reg = offset / 32; |
8081c84c | 96 | |
f89a768f | 97 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
8081c84c AD |
98 | } |
99 | ||
8c0f7b10 AH |
100 | static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, |
101 | enum GPIO_REG reg_type) | |
102 | { | |
f89a768f | 103 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8c0f7b10 AH |
104 | unsigned nreg = chip->ngpio / 32; |
105 | u8 reg = offset / 16; | |
8c0f7b10 | 106 | |
f89a768f | 107 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
8c0f7b10 AH |
108 | } |
109 | ||
f89a768f | 110 | static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) |
8c0f7b10 AH |
111 | { |
112 | void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR); | |
113 | u32 value = readl(gafr); | |
114 | int shift = (offset % 16) << 1, af = (value >> shift) & 3; | |
115 | ||
116 | if (af) { | |
117 | value &= ~(3 << shift); | |
118 | writel(value, gafr); | |
119 | } | |
120 | return 0; | |
121 | } | |
122 | ||
f89a768f | 123 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
8081c84c AD |
124 | { |
125 | void __iomem *gplr = gpio_reg(chip, offset, GPLR); | |
8bf02617 | 126 | |
8bf02617 AD |
127 | return readl(gplr) & BIT(offset % 32); |
128 | } | |
129 | ||
f89a768f | 130 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
8bf02617 | 131 | { |
8bf02617 AD |
132 | void __iomem *gpsr, *gpcr; |
133 | ||
134 | if (value) { | |
8081c84c | 135 | gpsr = gpio_reg(chip, offset, GPSR); |
8bf02617 AD |
136 | writel(BIT(offset % 32), gpsr); |
137 | } else { | |
8081c84c | 138 | gpcr = gpio_reg(chip, offset, GPCR); |
8bf02617 AD |
139 | writel(BIT(offset % 32), gpcr); |
140 | } | |
141 | } | |
142 | ||
f89a768f | 143 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
8bf02617 | 144 | { |
f89a768f | 145 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8081c84c | 146 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
8bf02617 AD |
147 | u32 value; |
148 | unsigned long flags; | |
8bf02617 | 149 | |
f89a768f DC |
150 | if (priv->pdev) |
151 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 152 | |
f89a768f | 153 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 AD |
154 | value = readl(gpdr); |
155 | value &= ~BIT(offset % 32); | |
156 | writel(value, gpdr); | |
f89a768f | 157 | spin_unlock_irqrestore(&priv->lock, flags); |
7812803a | 158 | |
f89a768f DC |
159 | if (priv->pdev) |
160 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 161 | |
8bf02617 AD |
162 | return 0; |
163 | } | |
164 | ||
f89a768f | 165 | static int intel_gpio_direction_output(struct gpio_chip *chip, |
8bf02617 AD |
166 | unsigned offset, int value) |
167 | { | |
f89a768f | 168 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
8081c84c | 169 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
8bf02617 | 170 | unsigned long flags; |
8bf02617 | 171 | |
f89a768f | 172 | intel_gpio_set(chip, offset, value); |
7812803a | 173 | |
f89a768f DC |
174 | if (priv->pdev) |
175 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 176 | |
f89a768f | 177 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 | 178 | value = readl(gpdr); |
6eab04a8 | 179 | value |= BIT(offset % 32); |
8bf02617 | 180 | writel(value, gpdr); |
f89a768f | 181 | spin_unlock_irqrestore(&priv->lock, flags); |
7812803a | 182 | |
f89a768f DC |
183 | if (priv->pdev) |
184 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 185 | |
8bf02617 AD |
186 | return 0; |
187 | } | |
188 | ||
f89a768f | 189 | static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
8bf02617 | 190 | { |
f89a768f DC |
191 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
192 | return irq_create_mapping(priv->domain, offset); | |
8bf02617 AD |
193 | } |
194 | ||
f89a768f | 195 | static int intel_mid_irq_type(struct irq_data *d, unsigned type) |
8bf02617 | 196 | { |
f89a768f | 197 | struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); |
465f2bd4 | 198 | u32 gpio = irqd_to_hwirq(d); |
8bf02617 AD |
199 | unsigned long flags; |
200 | u32 value; | |
f89a768f DC |
201 | void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); |
202 | void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); | |
8bf02617 | 203 | |
f89a768f | 204 | if (gpio >= priv->chip.ngpio) |
8bf02617 | 205 | return -EINVAL; |
7812803a | 206 | |
f89a768f DC |
207 | if (priv->pdev) |
208 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 209 | |
f89a768f | 210 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 AD |
211 | if (type & IRQ_TYPE_EDGE_RISING) |
212 | value = readl(grer) | BIT(gpio % 32); | |
213 | else | |
214 | value = readl(grer) & (~BIT(gpio % 32)); | |
215 | writel(value, grer); | |
216 | ||
217 | if (type & IRQ_TYPE_EDGE_FALLING) | |
218 | value = readl(gfer) | BIT(gpio % 32); | |
219 | else | |
220 | value = readl(gfer) & (~BIT(gpio % 32)); | |
221 | writel(value, gfer); | |
f89a768f | 222 | spin_unlock_irqrestore(&priv->lock, flags); |
8bf02617 | 223 | |
f89a768f DC |
224 | if (priv->pdev) |
225 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 226 | |
8bf02617 | 227 | return 0; |
fd0574cb | 228 | } |
8bf02617 | 229 | |
f89a768f | 230 | static void intel_mid_irq_unmask(struct irq_data *d) |
8bf02617 | 231 | { |
fd0574cb | 232 | } |
8bf02617 | 233 | |
f89a768f | 234 | static void intel_mid_irq_mask(struct irq_data *d) |
8bf02617 | 235 | { |
fd0574cb | 236 | } |
8bf02617 | 237 | |
aa6baa7e LW |
238 | static unsigned int intel_mid_irq_startup(struct irq_data *d) |
239 | { | |
240 | struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); | |
241 | ||
242 | if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) | |
243 | dev_err(priv->chip.dev, | |
244 | "unable to lock HW IRQ %lu for IRQ\n", | |
245 | irqd_to_hwirq(d)); | |
246 | intel_mid_irq_unmask(d); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static void intel_mid_irq_shutdown(struct irq_data *d) | |
251 | { | |
252 | struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); | |
253 | ||
254 | intel_mid_irq_mask(d); | |
255 | gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d)); | |
256 | } | |
257 | ||
f89a768f DC |
258 | static struct irq_chip intel_mid_irqchip = { |
259 | .name = "INTEL_MID-GPIO", | |
260 | .irq_mask = intel_mid_irq_mask, | |
261 | .irq_unmask = intel_mid_irq_unmask, | |
262 | .irq_set_type = intel_mid_irq_type, | |
aa6baa7e LW |
263 | .irq_startup = intel_mid_irq_startup, |
264 | .irq_shutdown = intel_mid_irq_shutdown, | |
8bf02617 AD |
265 | }; |
266 | ||
f89a768f | 267 | static const struct intel_mid_gpio_ddata gpio_lincroft = { |
d56d6b3d DC |
268 | .ngpio = 64, |
269 | }; | |
270 | ||
f89a768f | 271 | static const struct intel_mid_gpio_ddata gpio_penwell_aon = { |
d56d6b3d | 272 | .ngpio = 96, |
f89a768f | 273 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
274 | }; |
275 | ||
f89a768f | 276 | static const struct intel_mid_gpio_ddata gpio_penwell_core = { |
d56d6b3d | 277 | .ngpio = 96, |
f89a768f | 278 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
279 | }; |
280 | ||
f89a768f | 281 | static const struct intel_mid_gpio_ddata gpio_cloverview_aon = { |
d56d6b3d | 282 | .ngpio = 96, |
f89a768f | 283 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL, |
d56d6b3d DC |
284 | }; |
285 | ||
f89a768f | 286 | static const struct intel_mid_gpio_ddata gpio_cloverview_core = { |
d56d6b3d | 287 | .ngpio = 96, |
f89a768f | 288 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
289 | }; |
290 | ||
f89a768f | 291 | static const struct intel_mid_gpio_ddata gpio_tangier = { |
d56d6b3d DC |
292 | .ngpio = 192, |
293 | .gplr_offset = 4, | |
294 | .flis_base = 0xff0c0000, | |
295 | .flis_len = 0x8000, | |
296 | .get_flis_offset = NULL, | |
f89a768f | 297 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
298 | }; |
299 | ||
14f4a883 | 300 | static const struct pci_device_id intel_gpio_ids[] = { |
d56d6b3d DC |
301 | { |
302 | /* Lincroft */ | |
303 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), | |
304 | .driver_data = (kernel_ulong_t)&gpio_lincroft, | |
305 | }, | |
306 | { | |
307 | /* Penwell AON */ | |
308 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), | |
309 | .driver_data = (kernel_ulong_t)&gpio_penwell_aon, | |
310 | }, | |
311 | { | |
312 | /* Penwell Core */ | |
313 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), | |
314 | .driver_data = (kernel_ulong_t)&gpio_penwell_core, | |
315 | }, | |
316 | { | |
317 | /* Cloverview Aon */ | |
318 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), | |
319 | .driver_data = (kernel_ulong_t)&gpio_cloverview_aon, | |
320 | }, | |
321 | { | |
322 | /* Cloverview Core */ | |
323 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), | |
324 | .driver_data = (kernel_ulong_t)&gpio_cloverview_core, | |
325 | }, | |
326 | { | |
327 | /* Tangier */ | |
328 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199), | |
329 | .driver_data = (kernel_ulong_t)&gpio_tangier, | |
330 | }, | |
331 | { 0 } | |
8bf02617 | 332 | }; |
f89a768f | 333 | MODULE_DEVICE_TABLE(pci, intel_gpio_ids); |
8bf02617 | 334 | |
f89a768f | 335 | static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc) |
8bf02617 | 336 | { |
20e2aa91 | 337 | struct irq_data *data = irq_desc_get_irq_data(desc); |
f89a768f | 338 | struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data); |
20e2aa91 | 339 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
84bead6c | 340 | u32 base, gpio, mask; |
732063b9 | 341 | unsigned long pending; |
8bf02617 | 342 | void __iomem *gedr; |
8bf02617 AD |
343 | |
344 | /* check GPIO controller to check which pin triggered the interrupt */ | |
f89a768f DC |
345 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
346 | gedr = gpio_reg(&priv->chip, base, GEDR); | |
c8f925b6 | 347 | while ((pending = readl(gedr))) { |
2345b20f | 348 | gpio = __ffs(pending); |
84bead6c | 349 | mask = BIT(gpio); |
84bead6c TG |
350 | /* Clear before handling so we can't lose an edge */ |
351 | writel(mask, gedr); | |
f89a768f | 352 | generic_handle_irq(irq_find_mapping(priv->domain, |
465f2bd4 | 353 | base + gpio)); |
732063b9 | 354 | } |
8bf02617 | 355 | } |
0766d20f | 356 | |
20e2aa91 | 357 | chip->irq_eoi(data); |
8bf02617 AD |
358 | } |
359 | ||
f89a768f | 360 | static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) |
f5f93117 MW |
361 | { |
362 | void __iomem *reg; | |
363 | unsigned base; | |
364 | ||
f89a768f | 365 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
f5f93117 | 366 | /* Clear the rising-edge detect register */ |
f89a768f | 367 | reg = gpio_reg(&priv->chip, base, GRER); |
f5f93117 MW |
368 | writel(0, reg); |
369 | /* Clear the falling-edge detect register */ | |
f89a768f | 370 | reg = gpio_reg(&priv->chip, base, GFER); |
f5f93117 MW |
371 | writel(0, reg); |
372 | /* Clear the edge detect status register */ | |
f89a768f | 373 | reg = gpio_reg(&priv->chip, base, GEDR); |
f5f93117 MW |
374 | writel(~0, reg); |
375 | } | |
376 | } | |
377 | ||
ba519dd4 LW |
378 | static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
379 | irq_hw_number_t hwirq) | |
465f2bd4 | 380 | { |
f89a768f | 381 | struct intel_mid_gpio *priv = d->host_data; |
465f2bd4 | 382 | |
e5428a68 | 383 | irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq); |
ba519dd4 LW |
384 | irq_set_chip_data(irq, priv); |
385 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
465f2bd4 MW |
386 | |
387 | return 0; | |
388 | } | |
389 | ||
f89a768f DC |
390 | static const struct irq_domain_ops intel_gpio_irq_ops = { |
391 | .map = intel_gpio_irq_map, | |
465f2bd4 MW |
392 | .xlate = irq_domain_xlate_twocell, |
393 | }; | |
394 | ||
f89a768f | 395 | static int intel_gpio_runtime_idle(struct device *dev) |
7812803a | 396 | { |
45f0a85c | 397 | pm_schedule_suspend(dev, 500); |
7812803a KCA |
398 | return -EBUSY; |
399 | } | |
400 | ||
f89a768f DC |
401 | static const struct dev_pm_ops intel_gpio_pm_ops = { |
402 | SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle) | |
7812803a KCA |
403 | }; |
404 | ||
f89a768f | 405 | static int intel_gpio_probe(struct pci_dev *pdev, |
64c8cbc1 | 406 | const struct pci_device_id *id) |
8bf02617 | 407 | { |
64c8cbc1 | 408 | void __iomem *base; |
f89a768f | 409 | struct intel_mid_gpio *priv; |
8bf02617 | 410 | u32 gpio_base; |
2519f9ab | 411 | u32 irq_base; |
d6a2b7ba | 412 | int retval; |
f89a768f DC |
413 | struct intel_mid_gpio_ddata *ddata = |
414 | (struct intel_mid_gpio_ddata *)id->driver_data; | |
8bf02617 | 415 | |
786e07ec | 416 | retval = pcim_enable_device(pdev); |
8bf02617 | 417 | if (retval) |
8302c741 | 418 | return retval; |
8bf02617 | 419 | |
786e07ec | 420 | retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev)); |
8bf02617 | 421 | if (retval) { |
786e07ec AS |
422 | dev_err(&pdev->dev, "I/O memory mapping error\n"); |
423 | return retval; | |
8bf02617 | 424 | } |
64c8cbc1 | 425 | |
786e07ec AS |
426 | base = pcim_iomap_table(pdev)[1]; |
427 | ||
64c8cbc1 AS |
428 | irq_base = readl(base); |
429 | gpio_base = readl(sizeof(u32) + base); | |
430 | ||
8bf02617 | 431 | /* release the IO mapping, since we already get the info from bar1 */ |
786e07ec | 432 | pcim_iounmap_regions(pdev, 1 << 1); |
8bf02617 | 433 | |
f89a768f DC |
434 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
435 | if (!priv) { | |
8aca119f | 436 | dev_err(&pdev->dev, "can't allocate chip data\n"); |
786e07ec | 437 | return -ENOMEM; |
8bf02617 | 438 | } |
b3e35af2 | 439 | |
f89a768f DC |
440 | priv->reg_base = pcim_iomap_table(pdev)[0]; |
441 | priv->chip.label = dev_name(&pdev->dev); | |
aa6baa7e | 442 | priv->chip.dev = &pdev->dev; |
f89a768f DC |
443 | priv->chip.request = intel_gpio_request; |
444 | priv->chip.direction_input = intel_gpio_direction_input; | |
445 | priv->chip.direction_output = intel_gpio_direction_output; | |
446 | priv->chip.get = intel_gpio_get; | |
447 | priv->chip.set = intel_gpio_set; | |
448 | priv->chip.to_irq = intel_gpio_to_irq; | |
449 | priv->chip.base = gpio_base; | |
450 | priv->chip.ngpio = ddata->ngpio; | |
9fb1f39e | 451 | priv->chip.can_sleep = false; |
f89a768f DC |
452 | priv->pdev = pdev; |
453 | ||
454 | spin_lock_init(&priv->lock); | |
455 | ||
456 | priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio, | |
457 | irq_base, &intel_gpio_irq_ops, priv); | |
458 | if (!priv->domain) | |
786e07ec | 459 | return -ENOMEM; |
2519f9ab | 460 | |
f89a768f DC |
461 | pci_set_drvdata(pdev, priv); |
462 | retval = gpiochip_add(&priv->chip); | |
8bf02617 | 463 | if (retval) { |
8aca119f | 464 | dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
786e07ec | 465 | return retval; |
8bf02617 | 466 | } |
f5f93117 | 467 | |
f89a768f | 468 | intel_mid_irq_init_hw(priv); |
f5f93117 | 469 | |
f89a768f DC |
470 | irq_set_handler_data(pdev->irq, priv); |
471 | irq_set_chained_handler(pdev->irq, intel_mid_irq_handler); | |
8bf02617 | 472 | |
7812803a KCA |
473 | pm_runtime_put_noidle(&pdev->dev); |
474 | pm_runtime_allow(&pdev->dev); | |
475 | ||
8302c741 | 476 | return 0; |
8bf02617 AD |
477 | } |
478 | ||
f89a768f DC |
479 | static struct pci_driver intel_gpio_driver = { |
480 | .name = "intel_mid_gpio", | |
481 | .id_table = intel_gpio_ids, | |
482 | .probe = intel_gpio_probe, | |
7812803a | 483 | .driver = { |
f89a768f | 484 | .pm = &intel_gpio_pm_ops, |
7812803a | 485 | }, |
8bf02617 AD |
486 | }; |
487 | ||
f89a768f | 488 | static int __init intel_gpio_init(void) |
8bf02617 | 489 | { |
f89a768f | 490 | return pci_register_driver(&intel_gpio_driver); |
8bf02617 AD |
491 | } |
492 | ||
f89a768f | 493 | device_initcall(intel_gpio_init); |