[linux-2.6-block.git] / drivers / gpio / gpio-intel-mid.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel MID GPIO driver
 *
 * Copyright (c) 2008-2014,2016 Intel Corporation.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Clovertrail platform Cloverview chip.
 */

#include <linux/delay.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/stddef.h>

#define INTEL_MID_IRQ_TYPE_EDGE		(1 << 0)
#define INTEL_MID_IRQ_TYPE_LEVEL	(1 << 1)

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

/* intel_mid gpio driver data */
struct intel_mid_gpio_ddata {
	u16 ngpio;		/* number of gpio pins */
	u32 chip_irq_type;	/* chip interrupt type */
};

struct intel_mid_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
};

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return !!(readl(gplr) & BIT(offset % 32));
}

static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	intel_gpio_set(chip, offset, value);

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_mid_irq_type(struct irq_data *d, unsigned type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);

	if (gpio >= priv->chip.ngpio)
		return -EINVAL;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static void intel_mid_irq_unmask(struct irq_data *d)
{
}

static void intel_mid_irq_mask(struct irq_data *d)
{
}

static struct irq_chip intel_mid_irqchip = {
	.name		= "INTEL_MID-GPIO",
	.irq_mask	= intel_mid_irq_mask,
	.irq_unmask	= intel_mid_irq_unmask,
	.irq_set_type	= intel_mid_irq_type,
};

static const struct intel_mid_gpio_ddata gpio_lincroft = {
	.ngpio = 64,
};

static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_penwell_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct pci_device_id intel_gpio_ids[] = {
	{
		/* Lincroft */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
		.driver_data = (kernel_ulong_t)&gpio_lincroft,
	},
	{
		/* Penwell AON */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
		.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	},
	{
		/* Penwell Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
		.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	},
	{
		/* Cloverview Aon */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	},
	{
		/* Cloverview Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	},
	{ }
};

static void intel_mid_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < priv->chip.ngpio; base += 32) {
		gedr = gpio_reg(&priv->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(gc->irq.domain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < priv->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&priv->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&priv->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&priv->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
{
	int err = pm_schedule_suspend(dev, 500);
	return err ?: -EBUSY;
}

static const struct dev_pm_ops intel_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
};

static int intel_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct intel_mid_gpio *priv;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	struct intel_mid_gpio_ddata *ddata =
				(struct intel_mid_gpio_ddata *)id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->reg_base = pcim_iomap_table(pdev)[0];
	priv->chip.label = dev_name(&pdev->dev);
	priv->chip.parent = &pdev->dev;
	priv->chip.request = intel_gpio_request;
	priv->chip.direction_input = intel_gpio_direction_input;
	priv->chip.direction_output = intel_gpio_direction_output;
	priv->chip.get = intel_gpio_get;
	priv->chip.set = intel_gpio_set;
	priv->chip.base = gpio_base;
	priv->chip.ngpio = ddata->ngpio;
	priv->chip.can_sleep = false;
	priv->pdev = pdev;

	spin_lock_init(&priv->lock);

	pci_set_drvdata(pdev, priv);
	retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	retval = gpiochip_irqchip_add(&priv->chip,
				      &intel_mid_irqchip,
				      irq_base,
				      handle_simple_irq,
				      IRQ_TYPE_NONE);
	if (retval) {
		dev_err(&pdev->dev,
			"could not connect irqchip to gpiochip\n");
		return retval;
	}

	intel_mid_irq_init_hw(priv);

	gpiochip_set_chained_irqchip(&priv->chip,
				     &intel_mid_irqchip,
				     pdev->irq,
				     intel_mid_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver intel_gpio_driver = {
	.name		= "intel_mid_gpio",
	.id_table	= intel_gpio_ids,
	.probe		= intel_gpio_probe,
	.driver		= {
		.pm	= &intel_gpio_pm_ops,
	},
};

builtin_pci_driver(intel_gpio_driver);
Commit	Line	Data
917842f6	1	// SPDX-License-Identifier: GPL-2.0
c103de24	2	/*
a0bbf032	3	* Intel MID GPIO driver
c103de24	4	*
3cabe87b	5	* Copyright (c) 2008-2014,2016 Intel Corporation.
8bf02617 AD	6	*/
	7
	8	/* Supports:
	9	* Moorestown platform Langwell chip.
8081c84c	10	* Medfield platform Penwell chip.
f89a768f	11	* Clovertrail platform Cloverview chip.
8bf02617 AD	12	*/
8bf02617 AD	13
8bf02617	14	#include <linux/delay.h>
ddc53c40	15	#include <linux/gpio/driver.h>
8bf02617	16	#include <linux/init.h>
3cabe87b	17	#include <linux/interrupt.h>
8bf02617	18	#include <linux/io.h>
3cabe87b	19	#include <linux/kernel.h>
3cabe87b AS	20	#include <linux/pci.h>
3cabe87b AS	21	#include <linux/platform_device.h>
7812803a	22	#include <linux/pm_runtime.h>
3cabe87b AS	23	#include <linux/slab.h>
3cabe87b AS	24	#include <linux/stddef.h>
8bf02617	25
f89a768f DC	26	#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
f89a768f DC	27	#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
d56d6b3d	28
8081c84c AD	29	/*
	30	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	31	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	32	* registers to control them, so we only define the order here instead of a
	33	* structure, to get a bit offset for a pin (use GPDR as an example):
	34	*
	35	* nreg = ngpio / 32;
	36	* reg = offset / 32;
	37	* bit = offset % 32;
	38	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	39	*
	40	* so the bit of reg_addr is to control pin offset's GPDR feature
	41	*/
	42
	43	enum GPIO_REG {
	44	GPLR = 0, /* pin level read-only */
	45	GPDR, /* pin direction */
	46	GPSR, /* pin set */
	47	GPCR, /* pin clear */
	48	GRER, /* rising edge detect */
	49	GFER, /* falling edge detect */
	50	GEDR, /* edge detect result */
8c0f7b10	51	GAFR, /* alt function */
8bf02617 AD	52	};
8bf02617 AD	53
f89a768f DC	54	/* intel_mid gpio driver data */
f89a768f DC	55	struct intel_mid_gpio_ddata {
d56d6b3d	56	u16 ngpio; /* number of gpio pins */
d56d6b3d DC	57	u32 chip_irq_type; /* chip interrupt type */
	58	};
	59
f89a768f	60	struct intel_mid_gpio {
8bf02617	61	struct gpio_chip chip;
64c8cbc1	62	void __iomem *reg_base;
8bf02617	63	spinlock_t lock;
7812803a	64	struct pci_dev *pdev;
8bf02617 AD	65	};
8bf02617 AD	66
8081c84c	67	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	68	enum GPIO_REG reg_type)
8bf02617	69	{
5c77c021	70	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8081c84c	71	unsigned nreg = chip->ngpio / 32;
8bf02617	72	u8 reg = offset / 32;
8081c84c	73
f89a768f	74	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	75	}
8081c84c AD	76
8c0f7b10 AH	77	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	78	enum GPIO_REG reg_type)
	79	{
5c77c021	80	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8c0f7b10 AH	81	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	82	u8 reg = offset / 16;
8c0f7b10	83
f89a768f	84	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	85	}
8c0f7b10 AH	86
f89a768f	87	static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
8c0f7b10 AH	88	{
	89	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	90	u32 value = readl(gafr);
	91	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	92
	93	if (af) {
	94	value &= ~(3 << shift);
	95	writel(value, gafr);
	96	}
	97	return 0;
	98	}
	99
f89a768f	100	static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
8081c84c AD	101	{
8081c84c AD	102	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	103
4c628f3d	104	return !!(readl(gplr) & BIT(offset % 32));
8bf02617 AD	105	}
8bf02617 AD	106
f89a768f	107	static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
8bf02617	108	{
8bf02617 AD	109	void __iomem gpsr, gpcr;
	110
	111	if (value) {
8081c84c	112	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	113	writel(BIT(offset % 32), gpsr);
8bf02617 AD	114	} else {
8081c84c	115	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	116	writel(BIT(offset % 32), gpcr);
	117	}
	118	}
	119
f89a768f	120	static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
8bf02617	121	{
5c77c021	122	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8081c84c	123	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	124	u32 value;
8bf02617 AD	125	unsigned long flags;
8bf02617	126
f89a768f DC	127	if (priv->pdev)
f89a768f DC	128	pm_runtime_get(&priv->pdev->dev);
7812803a	129
f89a768f	130	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	131	value = readl(gpdr);
	132	value &= ~BIT(offset % 32);
	133	writel(value, gpdr);
f89a768f	134	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	135
f89a768f DC	136	if (priv->pdev)
f89a768f DC	137	pm_runtime_put(&priv->pdev->dev);
7812803a	138
8bf02617 AD	139	return 0;
	140	}
	141
f89a768f	142	static int intel_gpio_direction_output(struct gpio_chip *chip,
8bf02617 AD	143	unsigned offset, int value)
8bf02617 AD	144	{
5c77c021	145	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8081c84c	146	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	147	unsigned long flags;
8bf02617	148
f89a768f	149	intel_gpio_set(chip, offset, value);
7812803a	150
f89a768f DC	151	if (priv->pdev)
f89a768f DC	152	pm_runtime_get(&priv->pdev->dev);
7812803a	153
f89a768f	154	spin_lock_irqsave(&priv->lock, flags);
8bf02617	155	value = readl(gpdr);
6eab04a8	156	value \|= BIT(offset % 32);
8bf02617	157	writel(value, gpdr);
f89a768f	158	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	159
f89a768f DC	160	if (priv->pdev)
f89a768f DC	161	pm_runtime_put(&priv->pdev->dev);
7812803a	162
8bf02617 AD	163	return 0;
	164	}
	165
f89a768f	166	static int intel_mid_irq_type(struct irq_data *d, unsigned type)
8bf02617	167	{
3f7dbfd8	168	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5c77c021	169	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
465f2bd4	170	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	171	unsigned long flags;
8bf02617 AD	172	u32 value;
f89a768f DC	173	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
f89a768f DC	174	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
8bf02617	175
f89a768f	176	if (gpio >= priv->chip.ngpio)
8bf02617	177	return -EINVAL;
7812803a	178
f89a768f DC	179	if (priv->pdev)
f89a768f DC	180	pm_runtime_get(&priv->pdev->dev);
7812803a	181
f89a768f	182	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	183	if (type & IRQ_TYPE_EDGE_RISING)
	184	value = readl(grer) \| BIT(gpio % 32);
	185	else
	186	value = readl(grer) & (~BIT(gpio % 32));
	187	writel(value, grer);
	188
	189	if (type & IRQ_TYPE_EDGE_FALLING)
	190	value = readl(gfer) \| BIT(gpio % 32);
	191	else
	192	value = readl(gfer) & (~BIT(gpio % 32));
	193	writel(value, gfer);
f89a768f	194	spin_unlock_irqrestore(&priv->lock, flags);
8bf02617	195
f89a768f DC	196	if (priv->pdev)
f89a768f DC	197	pm_runtime_put(&priv->pdev->dev);
7812803a	198
8bf02617	199	return 0;
fd0574cb	200	}
8bf02617	201
f89a768f	202	static void intel_mid_irq_unmask(struct irq_data *d)
8bf02617	203	{
fd0574cb	204	}
8bf02617	205
f89a768f	206	static void intel_mid_irq_mask(struct irq_data *d)
8bf02617	207	{
fd0574cb	208	}
8bf02617	209
f89a768f DC	210	static struct irq_chip intel_mid_irqchip = {
	211	.name = "INTEL_MID-GPIO",
	212	.irq_mask = intel_mid_irq_mask,
	213	.irq_unmask = intel_mid_irq_unmask,
	214	.irq_set_type = intel_mid_irq_type,
8bf02617 AD	215	};
8bf02617 AD	216
f89a768f	217	static const struct intel_mid_gpio_ddata gpio_lincroft = {
d56d6b3d DC	218	.ngpio = 64,
	219	};
	220
f89a768f	221	static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
d56d6b3d	222	.ngpio = 96,
f89a768f	223	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	224	};
d56d6b3d DC	225
f89a768f	226	static const struct intel_mid_gpio_ddata gpio_penwell_core = {
d56d6b3d	227	.ngpio = 96,
f89a768f	228	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	229	};
d56d6b3d DC	230
f89a768f	231	static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
d56d6b3d	232	.ngpio = 96,
f89a768f	233	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE \| INTEL_MID_IRQ_TYPE_LEVEL,
d56d6b3d DC	234	};
d56d6b3d DC	235
f89a768f	236	static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
d56d6b3d	237	.ngpio = 96,
f89a768f	238	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	239	};
d56d6b3d DC	240
14f4a883	241	static const struct pci_device_id intel_gpio_ids[] = {
d56d6b3d DC	242	{
	243	/* Lincroft */
	244	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
	245	.driver_data = (kernel_ulong_t)&gpio_lincroft,
	246	},
	247	{
	248	/* Penwell AON */
	249	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
	250	.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	251	},
	252	{
	253	/* Penwell Core */
	254	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
	255	.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	256	},
	257	{
	258	/* Cloverview Aon */
	259	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
	260	.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	261	},
	262	{
	263	/* Cloverview Core */
	264	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
	265	.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	266	},
ddc53c40	267	{ }
8bf02617	268	};
8bf02617	269
bd0b9ac4	270	static void intel_mid_irq_handler(struct irq_desc *desc)
8bf02617	271	{
3f7dbfd8	272	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5c77c021	273	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
20e2aa91	274	struct irq_data *data = irq_desc_get_irq_data(desc);
20e2aa91	275	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	276	u32 base, gpio, mask;
732063b9	277	unsigned long pending;
8bf02617	278	void __iomem *gedr;
8bf02617 AD	279
8bf02617 AD	280	/* check GPIO controller to check which pin triggered the interrupt */
f89a768f DC	281	for (base = 0; base < priv->chip.ngpio; base += 32) {
f89a768f DC	282	gedr = gpio_reg(&priv->chip, base, GEDR);
c8f925b6	283	while ((pending = readl(gedr))) {
2345b20f	284	gpio = __ffs(pending);
84bead6c	285	mask = BIT(gpio);
84bead6c TG	286	/* Clear before handling so we can't lose an edge */
84bead6c TG	287	writel(mask, gedr);
f0fbe7bc	288	generic_handle_irq(irq_find_mapping(gc->irq.domain,
465f2bd4	289	base + gpio));
732063b9	290	}
8bf02617	291	}
0766d20f	292
20e2aa91	293	chip->irq_eoi(data);
8bf02617 AD	294	}
8bf02617 AD	295
f89a768f	296	static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
f5f93117 MW	297	{
	298	void __iomem *reg;
	299	unsigned base;
	300
f89a768f	301	for (base = 0; base < priv->chip.ngpio; base += 32) {
f5f93117	302	/* Clear the rising-edge detect register */
f89a768f	303	reg = gpio_reg(&priv->chip, base, GRER);
f5f93117 MW	304	writel(0, reg);
f5f93117 MW	305	/* Clear the falling-edge detect register */
f89a768f	306	reg = gpio_reg(&priv->chip, base, GFER);
f5f93117 MW	307	writel(0, reg);
f5f93117 MW	308	/* Clear the edge detect status register */
f89a768f	309	reg = gpio_reg(&priv->chip, base, GEDR);
f5f93117 MW	310	writel(~0, reg);
	311	}
	312	}
	313
fbc2a294	314	static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
7812803a	315	{
84a34575	316	int err = pm_schedule_suspend(dev, 500);
84a34575	317	return err ?: -EBUSY;
7812803a KCA	318	}
7812803a KCA	319
f89a768f DC	320	static const struct dev_pm_ops intel_gpio_pm_ops = {
f89a768f DC	321	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
7812803a KCA	322	};
7812803a KCA	323
f89a768f	324	static int intel_gpio_probe(struct pci_dev *pdev,
64c8cbc1	325	const struct pci_device_id *id)
8bf02617	326	{
64c8cbc1	327	void __iomem *base;
f89a768f	328	struct intel_mid_gpio *priv;
8bf02617	329	u32 gpio_base;
2519f9ab	330	u32 irq_base;
d6a2b7ba	331	int retval;
f89a768f DC	332	struct intel_mid_gpio_ddata *ddata =
f89a768f DC	333	(struct intel_mid_gpio_ddata *)id->driver_data;
8bf02617	334
786e07ec	335	retval = pcim_enable_device(pdev);
8bf02617	336	if (retval)
8302c741	337	return retval;
8bf02617	338
786e07ec	339	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	340	if (retval) {
786e07ec AS	341	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	342	return retval;
8bf02617	343	}
64c8cbc1	344
786e07ec AS	345	base = pcim_iomap_table(pdev)[1];
786e07ec AS	346
64c8cbc1 AS	347	irq_base = readl(base);
	348	gpio_base = readl(sizeof(u32) + base);
	349
8bf02617	350	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	351	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	352
f89a768f	353	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
75f8f5af	354	if (!priv)
786e07ec	355	return -ENOMEM;
b3e35af2	356
f89a768f DC	357	priv->reg_base = pcim_iomap_table(pdev)[0];
f89a768f DC	358	priv->chip.label = dev_name(&pdev->dev);
58383c78	359	priv->chip.parent = &pdev->dev;
f89a768f DC	360	priv->chip.request = intel_gpio_request;
	361	priv->chip.direction_input = intel_gpio_direction_input;
	362	priv->chip.direction_output = intel_gpio_direction_output;
	363	priv->chip.get = intel_gpio_get;
	364	priv->chip.set = intel_gpio_set;
f89a768f DC	365	priv->chip.base = gpio_base;
f89a768f DC	366	priv->chip.ngpio = ddata->ngpio;
9fb1f39e	367	priv->chip.can_sleep = false;
f89a768f DC	368	priv->pdev = pdev;
	369
	370	spin_lock_init(&priv->lock);
	371
f89a768f	372	pci_set_drvdata(pdev, priv);
dd3b204a	373	retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
8bf02617	374	if (retval) {
8aca119f	375	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	376	return retval;
8bf02617	377	}
f5f93117	378
3f7dbfd8 LW	379	retval = gpiochip_irqchip_add(&priv->chip,
	380	&intel_mid_irqchip,
	381	irq_base,
	382	handle_simple_irq,
	383	IRQ_TYPE_NONE);
	384	if (retval) {
	385	dev_err(&pdev->dev,
	386	"could not connect irqchip to gpiochip\n");
	387	return retval;
	388	}
	389
f89a768f	390	intel_mid_irq_init_hw(priv);
f5f93117	391
3f7dbfd8 LW	392	gpiochip_set_chained_irqchip(&priv->chip,
	393	&intel_mid_irqchip,
	394	pdev->irq,
	395	intel_mid_irq_handler);
8bf02617	396
7812803a KCA	397	pm_runtime_put_noidle(&pdev->dev);
	398	pm_runtime_allow(&pdev->dev);
	399
8302c741	400	return 0;
8bf02617 AD	401	}
8bf02617 AD	402
f89a768f DC	403	static struct pci_driver intel_gpio_driver = {
	404	.name = "intel_mid_gpio",
	405	.id_table = intel_gpio_ids,
	406	.probe = intel_gpio_probe,
7812803a	407	.driver = {
f89a768f	408	.pm = &intel_gpio_pm_ops,
7812803a	409	},
8bf02617 AD	410	};
8bf02617 AD	411
5261bee8	412	builtin_pci_driver(intel_gpio_driver);