[linux-2.6-block.git] / drivers / gpio / gpio-ich.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 */

#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/ioport.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
	GPO_BLINK
};

static const u8 ichx_regs[4][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
	{0x18, 0x18, 0x18},	/* BLINK offset */
};

static const u8 ichx_reglen[3] = {
	0x30, 0x10, 0x10,
};

static const u8 avoton_regs[4][3] = {
	{0x00, 0x80, 0x00},
	{0x04, 0x84, 0x00},
	{0x08, 0x88, 0x00},
};

static const u8 avoton_reglen[3] = {
	0x10, 0x10, 0x00,
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* chipset registers */
	const u8 (*regs)[3];
	const u8 *reglen;

	/* GPO_BLINK is available on this chipset */
	bool have_blink;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned int offset);
	int (*get)(struct gpio_chip *chip, unsigned int offset);

	/*
	 * Some chipsets don't let reading output values on GPIO_LVL register
	 * this option allows driver caching written output values
	 */
	bool use_outlvl_cache;
};

static struct {
	spinlock_t lock;
	struct device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Management IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
	u8 use_gpio;		/* Which GPIO groups are usable */
	int outlvl_cache[3];	/* cached output values */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");

static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr];
	else
		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
				 ichx_priv.gpio_base);

	if (val)
		data |= BIT(bit);
	else
		data &= ~BIT(bit);
	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);
	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		ichx_priv.outlvl_cache[reg_nr] = data;

	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			ichx_priv.gpio_base);

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return (verify && data != tmp) ? -EPERM : 0;
}

static int ichx_read_bit(int reg, unsigned int nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr] | data;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return !!(data & BIT(bit));
}

static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
{
	return !!(ichx_priv.use_gpio & BIT(nr / 32));
}

static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
{
	if (ichx_read_bit(GPIO_IO_SEL, nr))
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
{
	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
					int val)
{
	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
	if (nr < 32 && ichx_priv.desc->have_blink)
		ichx_write_bit(GPO_BLINK, nr, 0, 0);

	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
{
	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
{
	unsigned long flags;
	u32 data;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return !!((data >> 16) & BIT(nr));
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
{
	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
		return 0;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->parent = ichx_priv.dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->get_direction = ichx_gpio_get_direction;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = false;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Avoton */
static struct ichx_desc avoton_desc = {
	/* Avoton has only 59 GPIOs, but we assume the first set of register
	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
	 */
	.ngpio = 60,
	.regs = avoton_regs,
	.reglen = avoton_reglen,
	.use_outlvl_cache = true,
};

static int ichx_gpio_request_regions(struct device *dev,
	struct resource *res_base, const char *name, u8 use_gpio)
{
	int i;

	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & BIT(i)))
			continue;
		if (!devm_request_region(dev,
				res_base->start + ichx_priv.desc->regs[0][i],
				ichx_priv.desc->reglen[i], name))
			return -EBUSY;
	}
	return 0;
}

static int ichx_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct lpc_ich_info *ich_info = dev_get_platdata(dev);
	struct resource *res_base, *res_pm;
	int err;

	if (!ich_info)
		return -ENODEV;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	case AVOTON_GPIO:
		ichx_priv.desc = &avoton_desc;
		break;
	default:
		return -ENODEV;
	}

	ichx_priv.dev = dev;
	spin_lock_init(&ichx_priv.lock);

	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	err = ichx_gpio_request_regions(dev, res_base, pdev->name,
					ich_info->use_gpio);
	if (err)
		return err;

	ichx_priv.gpio_base = res_base;
	ichx_priv.use_gpio = ich_info->use_gpio;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
				 pdev->name)) {
		dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL);
	if (err) {
		dev_err(dev, "Failed to register GPIOs\n");
		return err;
	}

	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
		 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
7ed0cf0a	1	// SPDX-License-Identifier: GPL-2.0+
6ed9f9c4	2	/*
3b923189	3	* Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
6ed9f9c4 PT	4	*
6ed9f9c4 PT	5	* Copyright (C) 2010 Extreme Engineering Solutions.
6ed9f9c4 PT	6	*/
6ed9f9c4 PT	7
488f270c AS	8	#include <linux/bitops.h>
488f270c AS	9	#include <linux/gpio/driver.h>
8a06b08e	10	#include <linux/ioport.h>
488f270c	11	#include <linux/mfd/lpc_ich.h>
6ed9f9c4	12	#include <linux/module.h>
6ed9f9c4	13	#include <linux/platform_device.h>
6ed9f9c4 PT	14
	15	#define DRV_NAME "gpio_ich"
	16
	17	/*
	18	* GPIO register offsets in GPIO I/O space.
	19	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	20	* LVLx registers. Logic in the read/write functions takes a register and
	21	* an absolute bit number and determines the proper register offset and bit
	22	* number in that register. For example, to read the value of GPIO bit 50
	23	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	24	* bit 18 (50%32).
	25	*/
	26	enum GPIO_REG {
	27	GPIO_USE_SEL = 0,
	28	GPIO_IO_SEL,
	29	GPIO_LVL,
7f6569f5	30	GPO_BLINK
6ed9f9c4 PT	31	};
6ed9f9c4 PT	32
7f6569f5	33	static const u8 ichx_regs[4][3] = {
6ed9f9c4 PT	34	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	35	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	36	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
7f6569f5	37	{0x18, 0x18, 0x18}, /* BLINK offset */
6ed9f9c4 PT	38	};
6ed9f9c4 PT	39
4f600ada JD	40	static const u8 ichx_reglen[3] = {
	41	0x30, 0x10, 0x10,
	42	};
	43
3b923189 VD	44	static const u8 avoton_regs[4][3] = {
	45	{0x00, 0x80, 0x00},
	46	{0x04, 0x84, 0x00},
	47	{0x08, 0x88, 0x00},
	48	};
	49
	50	static const u8 avoton_reglen[3] = {
	51	0x10, 0x10, 0x00,
	52	};
	53
6ed9f9c4 PT	54	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	55	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	56
	57	struct ichx_desc {
	58	/* Max GPIO pins the chipset can have */
	59	uint ngpio;
	60
bb62a35b VD	61	/* chipset registers */
	62	const u8 (*regs)[3];
	63	const u8 *reglen;
	64
ba7f74fe VD	65	/* GPO_BLINK is available on this chipset */
	66	bool have_blink;
	67
6ed9f9c4 PT	68	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	69	bool uses_gpe0;
	70
	71	/* USE_SEL is bogus on some chipsets, eg 3100 */
	72	u32 use_sel_ignore[3];
	73
	74	/* Some chipsets have quirks, let these use their own request/get */
ae84f15c AS	75	int (request)(struct gpio_chip chip, unsigned int offset);
ae84f15c AS	76	int (get)(struct gpio_chip chip, unsigned int offset);
e6540f33 VD	77
	78	/*
	79	* Some chipsets don't let reading output values on GPIO_LVL register
	80	* this option allows driver caching written output values
	81	*/
	82	bool use_outlvl_cache;
6ed9f9c4 PT	83	};
	84
	85	static struct {
	86	spinlock_t lock;
ff4709b4	87	struct device *dev;
6ed9f9c4 PT	88	struct gpio_chip chip;
6ed9f9c4 PT	89	struct resource gpio_base; / GPIO IO base */
9b6d5690	90	struct resource pm_base; / Power Management IO base */
6ed9f9c4 PT	91	struct ichx_desc desc; / Pointer to chipset-specific description */
6ed9f9c4 PT	92	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
4f600ada	93	u8 use_gpio; /* Which GPIO groups are usable */
e6540f33	94	int outlvl_cache[3]; /* cached output values */
6ed9f9c4 PT	95	} ichx_priv;
	96
	97	static int modparam_gpiobase = -1; /* dynamic */
	98	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
5f6f2b9f	99	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
6ed9f9c4	100
ae84f15c	101	static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
6ed9f9c4 PT	102	{
	103	unsigned long flags;
	104	u32 data, tmp;
	105	int reg_nr = nr / 32;
	106	int bit = nr & 0x1f;
6ed9f9c4 PT	107
	108	spin_lock_irqsave(&ichx_priv.lock, flags);
	109
e6540f33 VD	110	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	111	data = ichx_priv.outlvl_cache[reg_nr];
	112	else
	113	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
	114	ichx_priv.gpio_base);
	115
6ed9f9c4	116	if (val)
7a8fd1f5	117	data \|= BIT(bit);
6ed9f9c4	118	else
7a8fd1f5	119	data &= ~BIT(bit);
bb62a35b VD	120	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	121	ichx_priv.gpio_base);
e6540f33 VD	122	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	123	ichx_priv.outlvl_cache[reg_nr] = data;
	124
bb62a35b VD	125	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	126	ichx_priv.gpio_base);
6ed9f9c4 PT	127
	128	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	129
c5aaa316	130	return (verify && data != tmp) ? -EPERM : 0;
6ed9f9c4 PT	131	}
6ed9f9c4 PT	132
ae84f15c	133	static int ichx_read_bit(int reg, unsigned int nr)
6ed9f9c4 PT	134	{
	135	unsigned long flags;
	136	u32 data;
	137	int reg_nr = nr / 32;
	138	int bit = nr & 0x1f;
	139
	140	spin_lock_irqsave(&ichx_priv.lock, flags);
	141
bb62a35b VD	142	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	143	ichx_priv.gpio_base);
6ed9f9c4	144
e6540f33 VD	145	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	146	data = ichx_priv.outlvl_cache[reg_nr] \| data;
	147
6ed9f9c4 PT	148	spin_unlock_irqrestore(&ichx_priv.lock, flags);
6ed9f9c4 PT	149
7a8fd1f5	150	return !!(data & BIT(bit));
6ed9f9c4 PT	151	}
6ed9f9c4 PT	152
ae84f15c	153	static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
4f600ada	154	{
7a8fd1f5	155	return !!(ichx_priv.use_gpio & BIT(nr / 32));
4f600ada JD	156	}
4f600ada JD	157
ae84f15c	158	static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
62e08f25	159	{
e42615ec MV	160	if (ichx_read_bit(GPIO_IO_SEL, nr))
	161	return GPIO_LINE_DIRECTION_IN;
	162
	163	return GPIO_LINE_DIRECTION_OUT;
62e08f25 AS	164	}
62e08f25 AS	165
ae84f15c	166	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
6ed9f9c4 PT	167	{
	168	/*
	169	* Try setting pin as an input and verify it worked since many pins
	170	* are output-only.
	171	*/
c5aaa316	172	return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
6ed9f9c4 PT	173	}
6ed9f9c4 PT	174
ae84f15c	175	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
6ed9f9c4 PT	176	int val)
6ed9f9c4 PT	177	{
7f6569f5	178	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
ba7f74fe	179	if (nr < 32 && ichx_priv.desc->have_blink)
7f6569f5 VD	180	ichx_write_bit(GPO_BLINK, nr, 0, 0);
7f6569f5 VD	181
6ed9f9c4 PT	182	/* Set GPIO output value. */
	183	ichx_write_bit(GPIO_LVL, nr, val, 0);
	184
	185	/*
	186	* Try setting pin as an output and verify it worked since many pins
	187	* are input-only.
	188	*/
c5aaa316	189	return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
6ed9f9c4 PT	190	}
6ed9f9c4 PT	191
ae84f15c	192	static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
6ed9f9c4 PT	193	{
	194	return ichx_read_bit(GPIO_LVL, nr);
	195	}
	196
ae84f15c	197	static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
6ed9f9c4 PT	198	{
	199	unsigned long flags;
	200	u32 data;
	201
	202	/*
	203	* GPI 0 - 15 need to be read from the power management registers on
	204	* a ICH6/3100 bridge.
	205	*/
	206	if (nr < 16) {
	207	if (!ichx_priv.pm_base)
	208	return -ENXIO;
	209
	210	spin_lock_irqsave(&ichx_priv.lock, flags);
	211
	212	/* GPI 0 - 15 are latched, write 1 to clear*/
7a8fd1f5	213	ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
6ed9f9c4 PT	214	data = ICHX_READ(0, ichx_priv.pm_base);
	215
	216	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	217
7a8fd1f5	218	return !!((data >> 16) & BIT(nr));
6ed9f9c4 PT	219	} else {
	220	return ichx_gpio_get(chip, nr);
	221	}
	222	}
	223
ae84f15c	224	static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
6ed9f9c4	225	{
25f27db4 JD	226	if (!ichx_gpio_check_available(chip, nr))
	227	return -ENXIO;
	228
6ed9f9c4 PT	229	/*
	230	* Note we assume the BIOS properly set a bridge's USE value. Some
	231	* chips (eg Intel 3100) have bogus USE values though, so first see if
	232	* the chipset's USE value can be trusted for this specific bit.
	233	* If it can't be trusted, assume that the pin can be used as a GPIO.
	234	*/
7a8fd1f5	235	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
2ab3a749	236	return 0;
6ed9f9c4 PT	237
	238	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
	239	}
	240
ae84f15c	241	static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
6ed9f9c4 PT	242	{
	243	/*
	244	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	245	* bridge as they are controlled by USE register bits 0 and 1. See
	246	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	247	* additional info.
	248	*/
	249	if (nr == 16 \|\| nr == 17)
	250	nr -= 16;
	251
	252	return ichx_gpio_request(chip, nr);
	253	}
	254
ae84f15c	255	static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
6ed9f9c4 PT	256	{
	257	ichx_write_bit(GPIO_LVL, nr, val, 0);
	258	}
	259
3836309d	260	static void ichx_gpiolib_setup(struct gpio_chip *chip)
6ed9f9c4 PT	261	{
	262	chip->owner = THIS_MODULE;
	263	chip->label = DRV_NAME;
ff4709b4	264	chip->parent = ichx_priv.dev;
6ed9f9c4 PT	265
	266	/* Allow chip-specific overrides of request()/get() */
	267	chip->request = ichx_priv.desc->request ?
	268	ichx_priv.desc->request : ichx_gpio_request;
	269	chip->get = ichx_priv.desc->get ?
	270	ichx_priv.desc->get : ichx_gpio_get;
	271
	272	chip->set = ichx_gpio_set;
62e08f25	273	chip->get_direction = ichx_gpio_get_direction;
6ed9f9c4 PT	274	chip->direction_input = ichx_gpio_direction_input;
	275	chip->direction_output = ichx_gpio_direction_output;
	276	chip->base = modparam_gpiobase;
	277	chip->ngpio = ichx_priv.desc->ngpio;
9fb1f39e	278	chip->can_sleep = false;
6ed9f9c4 PT	279	chip->dbg_show = NULL;
	280	}
	281
	282	/* ICH6-based, 631xesb-based */
	283	static struct ichx_desc ich6_desc = {
	284	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	285	.request = ich6_gpio_request,
	286	.get = ich6_gpio_get,
	287
	288	/* GPIO 0-15 are read in the GPE0_STS PM register */
	289	.uses_gpe0 = true,
	290
	291	.ngpio = 50,
ba7f74fe	292	.have_blink = true,
a7008ee1 VD	293	.regs = ichx_regs,
a7008ee1 VD	294	.reglen = ichx_reglen,
6ed9f9c4 PT	295	};
	296
	297	/* Intel 3100 */
	298	static struct ichx_desc i3100_desc = {
	299	/*
	300	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	301	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
	302	* Datasheet for more info.
	303	*/
	304	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
	305
	306	/* The 3100 needs fixups for GPIO 0 - 17 */
	307	.request = ich6_gpio_request,
	308	.get = ich6_gpio_get,
	309
	310	/* GPIO 0-15 are read in the GPE0_STS PM register */
	311	.uses_gpe0 = true,
	312
	313	.ngpio = 50,
a7008ee1 VD	314	.regs = ichx_regs,
a7008ee1 VD	315	.reglen = ichx_reglen,
6ed9f9c4 PT	316	};
	317
	318	/* ICH7 and ICH8-based */
	319	static struct ichx_desc ich7_desc = {
	320	.ngpio = 50,
ba7f74fe	321	.have_blink = true,
bb62a35b VD	322	.regs = ichx_regs,
bb62a35b VD	323	.reglen = ichx_reglen,
6ed9f9c4 PT	324	};
	325
	326	/* ICH9-based */
	327	static struct ichx_desc ich9_desc = {
	328	.ngpio = 61,
ba7f74fe	329	.have_blink = true,
bb62a35b VD	330	.regs = ichx_regs,
bb62a35b VD	331	.reglen = ichx_reglen,
6ed9f9c4 PT	332	};
	333
	334	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
	335	static struct ichx_desc ich10_cons_desc = {
	336	.ngpio = 61,
ba7f74fe	337	.have_blink = true,
bb62a35b VD	338	.regs = ichx_regs,
bb62a35b VD	339	.reglen = ichx_reglen,
6ed9f9c4 PT	340	};
	341	static struct ichx_desc ich10_corp_desc = {
	342	.ngpio = 72,
ba7f74fe	343	.have_blink = true,
bb62a35b VD	344	.regs = ichx_regs,
bb62a35b VD	345	.reglen = ichx_reglen,
6ed9f9c4 PT	346	};
	347
	348	/* Intel 5 series, 6 series, 3400 series, and C200 series */
	349	static struct ichx_desc intel5_desc = {
	350	.ngpio = 76,
bb62a35b VD	351	.regs = ichx_regs,
bb62a35b VD	352	.reglen = ichx_reglen,
6ed9f9c4 PT	353	};
6ed9f9c4 PT	354
3b923189 VD	355	/* Avoton */
	356	static struct ichx_desc avoton_desc = {
	357	/* Avoton has only 59 GPIOs, but we assume the first set of register
	358	* (Core) has 32 instead of 31 to keep gpio-ich compliance
	359	*/
	360	.ngpio = 60,
	361	.regs = avoton_regs,
	362	.reglen = avoton_reglen,
	363	.use_outlvl_cache = true,
	364	};
	365
8a06b08e WBG	366	static int ichx_gpio_request_regions(struct device *dev,
8a06b08e WBG	367	struct resource res_base, const char name, u8 use_gpio)
4f600ada JD	368	{
	369	int i;
	370
	371	if (!res_base \|\| !res_base->start \|\| !res_base->end)
	372	return -ENODEV;
	373
bb62a35b	374	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
7a8fd1f5	375	if (!(use_gpio & BIT(i)))
4f600ada	376	continue;
8a06b08e	377	if (!devm_request_region(dev,
bb62a35b VD	378	res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	379	ichx_priv.desc->reglen[i], name))
8a06b08e	380	return -EBUSY;
4f600ada JD	381	}
4f600ada JD	382	return 0;
4f600ada JD	383	}
4f600ada JD	384
3836309d	385	static int ichx_gpio_probe(struct platform_device *pdev)
6ed9f9c4	386	{
ff4709b4 AS	387	struct device *dev = &pdev->dev;
ff4709b4 AS	388	struct lpc_ich_info *ich_info = dev_get_platdata(dev);
6ed9f9c4 PT	389	struct resource res_base, res_pm;
6ed9f9c4 PT	390	int err;
6ed9f9c4 PT	391
	392	if (!ich_info)
	393	return -ENODEV;
	394
6ed9f9c4 PT	395	switch (ich_info->gpio_version) {
	396	case ICH_I3100_GPIO:
	397	ichx_priv.desc = &i3100_desc;
	398	break;
	399	case ICH_V5_GPIO:
	400	ichx_priv.desc = &intel5_desc;
	401	break;
	402	case ICH_V6_GPIO:
	403	ichx_priv.desc = &ich6_desc;
	404	break;
	405	case ICH_V7_GPIO:
	406	ichx_priv.desc = &ich7_desc;
	407	break;
	408	case ICH_V9_GPIO:
	409	ichx_priv.desc = &ich9_desc;
	410	break;
	411	case ICH_V10CORP_GPIO:
	412	ichx_priv.desc = &ich10_corp_desc;
	413	break;
	414	case ICH_V10CONS_GPIO:
	415	ichx_priv.desc = &ich10_cons_desc;
	416	break;
3b923189 VD	417	case AVOTON_GPIO:
	418	ichx_priv.desc = &avoton_desc;
	419	break;
6ed9f9c4 PT	420	default:
	421	return -ENODEV;
	422	}
	423
ff4709b4	424	ichx_priv.dev = dev;
d39a948f	425	spin_lock_init(&ichx_priv.lock);
ff4709b4	426
6ed9f9c4	427	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
ff4709b4 AS	428	err = ichx_gpio_request_regions(dev, res_base, pdev->name,
ff4709b4 AS	429	ich_info->use_gpio);
4f600ada JD	430	if (err)
4f600ada JD	431	return err;
6ed9f9c4 PT	432
6ed9f9c4 PT	433	ichx_priv.gpio_base = res_base;
ff4709b4	434	ichx_priv.use_gpio = ich_info->use_gpio;
6ed9f9c4 PT	435
	436	/*
	437	* If necessary, determine the I/O address of ACPI/power management
5f6f2b9f	438	* registers which are needed to read the GPE0 register for GPI pins
6ed9f9c4 PT	439	* 0 - 15 on some chipsets.
	440	*/
	441	if (!ichx_priv.desc->uses_gpe0)
	442	goto init;
	443
	444	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	445	if (!res_pm) {
c086bea5	446	dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
6ed9f9c4 PT	447	goto init;
	448	}
	449
ff4709b4 AS	450	if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
ff4709b4 AS	451	pdev->name)) {
c086bea5	452	dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
6ed9f9c4 PT	453	goto init;
	454	}
	455
	456	ichx_priv.pm_base = res_pm;
	457
	458	init:
	459	ichx_gpiolib_setup(&ichx_priv.chip);
56b16a9a	460	err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL);
6ed9f9c4	461	if (err) {
c086bea5	462	dev_err(dev, "Failed to register GPIOs\n");
8a06b08e	463	return err;
6ed9f9c4 PT	464	}
6ed9f9c4 PT	465
c086bea5 AS	466	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
c086bea5 AS	467	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
6ed9f9c4 PT	468
6ed9f9c4 PT	469	return 0;
6ed9f9c4 PT	470	}
6ed9f9c4 PT	471
6ed9f9c4 PT	472	static struct platform_driver ichx_gpio_driver = {
6ed9f9c4 PT	473	.driver = {
6ed9f9c4 PT	474	.name = DRV_NAME,
	475	},
	476	.probe = ichx_gpio_probe,
6ed9f9c4 PT	477	};
	478
	479	module_platform_driver(ichx_gpio_driver);
	480
	481	MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
	482	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
	483	MODULE_LICENSE("GPL");
	484	MODULE_ALIAS("platform:"DRV_NAME);