[linux-2.6-block.git] / drivers / gpio / gpio-ich.c

/*
 * Intel ICH6-10, Series 5 and 6 GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mfd/lpc_ich.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
	GPO_BLINK
};

static const u8 ichx_regs[4][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
	{0x18, 0x18, 0x18},	/* BLINK offset */
};

static const u8 ichx_reglen[3] = {
	0x30, 0x10, 0x10,
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* chipset registers */
	const u8 (*regs)[3];
	const u8 *reglen;

	/* GPO_BLINK is available on this chipset */
	bool have_blink;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned offset);
	int (*get)(struct gpio_chip *chip, unsigned offset);

	/*
	 * Some chipsets don't let reading output values on GPIO_LVL register
	 * this option allows driver caching written output values
	 */
	bool use_outlvl_cache;
};

static struct {
	spinlock_t lock;
	struct platform_device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Mangagment IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
	u8 use_gpio;		/* Which GPIO groups are usable */
	int outlvl_cache[3];	/* cached output values */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
			   "which is the default.");

static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;
	int ret = 0;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr];
	else
		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
				 ichx_priv.gpio_base);

	if (val)
		data |= 1 << bit;
	else
		data &= ~(1 << bit);
	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);
	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		ichx_priv.outlvl_cache[reg_nr] = data;

	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			ichx_priv.gpio_base);
	if (verify && data != tmp)
		ret = -EPERM;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return ret;
}

static int ichx_read_bit(int reg, unsigned nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr] | data;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return data & (1 << bit) ? 1 : 0;
}

static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
{
	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
					int val)
{
	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
	if (nr < 32 && ichx_priv.desc->have_blink)
		ichx_write_bit(GPO_BLINK, nr, 0, 0);

	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	unsigned long flags;
	u32 data;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return (data >> 16) & (1 << nr) ? 1 : 0;
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
		return 0;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->dev = &ichx_priv.dev->dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = false;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.have_blink = true,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

static int ichx_gpio_request_regions(struct resource *res_base,
						const char *name, u8 use_gpio)
{
	int i;

	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		if (!request_region(
				res_base->start + ichx_priv.desc->regs[0][i],
				ichx_priv.desc->reglen[i], name))
			goto request_err;
	}
	return 0;

request_err:
	/* Clean up: release already requested regions, if any */
	for (i--; i >= 0; i--) {
		if (!(use_gpio & (1 << i)))
			continue;
		release_region(res_base->start + ichx_priv.desc->regs[0][i],
			       ichx_priv.desc->reglen[i]);
	}
	return -EBUSY;
}

static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		release_region(res_base->start + ichx_priv.desc->regs[0][i],
			       ichx_priv.desc->reglen[i]);
	}
}

static int ichx_gpio_probe(struct platform_device *pdev)
{
	struct resource *res_base, *res_pm;
	int err;
	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);

	if (!ich_info)
		return -ENODEV;

	ichx_priv.dev = pdev;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	default:
		return -ENODEV;
	}

	spin_lock_init(&ichx_priv.lock);
	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	ichx_priv.use_gpio = ich_info->use_gpio;
	err = ichx_gpio_request_regions(res_base, pdev->name,
					ichx_priv.use_gpio);
	if (err)
		return err;

	ichx_priv.gpio_base = res_base;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!request_region(res_pm->start, resource_size(res_pm),
			pdev->name)) {
		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = gpiochip_add(&ichx_priv.chip);
	if (err) {
		pr_err("Failed to register GPIOs\n");
		goto add_err;
	}

	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);

	return 0;

add_err:
	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));
	return err;
}

static int ichx_gpio_remove(struct platform_device *pdev)
{
	int err;

	err = gpiochip_remove(&ichx_priv.chip);
	if (err) {
		dev_err(&pdev->dev, "%s failed, %d\n",
				"gpiochip_remove()", err);
		return err;
	}

	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
	.remove		= ichx_gpio_remove,
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
6ed9f9c4 PT	1	/*
	2	* Intel ICH6-10, Series 5 and 6 GPIO driver
	3	*
	4	* Copyright (C) 2010 Extreme Engineering Solutions.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
	23	#include <linux/module.h>
	24	#include <linux/pci.h>
	25	#include <linux/gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/mfd/lpc_ich.h>
	28
	29	#define DRV_NAME "gpio_ich"
	30
	31	/*
	32	* GPIO register offsets in GPIO I/O space.
	33	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	34	* LVLx registers. Logic in the read/write functions takes a register and
	35	* an absolute bit number and determines the proper register offset and bit
	36	* number in that register. For example, to read the value of GPIO bit 50
	37	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	38	* bit 18 (50%32).
	39	*/
	40	enum GPIO_REG {
	41	GPIO_USE_SEL = 0,
	42	GPIO_IO_SEL,
	43	GPIO_LVL,
7f6569f5	44	GPO_BLINK
6ed9f9c4 PT	45	};
6ed9f9c4 PT	46
7f6569f5	47	static const u8 ichx_regs[4][3] = {
6ed9f9c4 PT	48	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	49	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	50	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
7f6569f5	51	{0x18, 0x18, 0x18}, /* BLINK offset */
6ed9f9c4 PT	52	};
6ed9f9c4 PT	53
4f600ada JD	54	static const u8 ichx_reglen[3] = {
	55	0x30, 0x10, 0x10,
	56	};
	57
6ed9f9c4 PT	58	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	59	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	60
	61	struct ichx_desc {
	62	/* Max GPIO pins the chipset can have */
	63	uint ngpio;
	64
bb62a35b VD	65	/* chipset registers */
	66	const u8 (*regs)[3];
	67	const u8 *reglen;
	68
ba7f74fe VD	69	/* GPO_BLINK is available on this chipset */
	70	bool have_blink;
	71
6ed9f9c4 PT	72	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	73	bool uses_gpe0;
	74
	75	/* USE_SEL is bogus on some chipsets, eg 3100 */
	76	u32 use_sel_ignore[3];
	77
	78	/* Some chipsets have quirks, let these use their own request/get */
	79	int (request)(struct gpio_chip chip, unsigned offset);
	80	int (get)(struct gpio_chip chip, unsigned offset);
e6540f33 VD	81
	82	/*
	83	* Some chipsets don't let reading output values on GPIO_LVL register
	84	* this option allows driver caching written output values
	85	*/
	86	bool use_outlvl_cache;
6ed9f9c4 PT	87	};
	88
	89	static struct {
	90	spinlock_t lock;
	91	struct platform_device *dev;
	92	struct gpio_chip chip;
	93	struct resource gpio_base; / GPIO IO base */
	94	struct resource pm_base; / Power Mangagment IO base */
	95	struct ichx_desc desc; / Pointer to chipset-specific description */
	96	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
4f600ada	97	u8 use_gpio; /* Which GPIO groups are usable */
e6540f33	98	int outlvl_cache[3]; /* cached output values */
6ed9f9c4 PT	99	} ichx_priv;
	100
	101	static int modparam_gpiobase = -1; /* dynamic */
	102	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
	103	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
	104	"which is the default.");
	105
	106	static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
	107	{
	108	unsigned long flags;
	109	u32 data, tmp;
	110	int reg_nr = nr / 32;
	111	int bit = nr & 0x1f;
	112	int ret = 0;
	113
	114	spin_lock_irqsave(&ichx_priv.lock, flags);
	115
e6540f33 VD	116	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	117	data = ichx_priv.outlvl_cache[reg_nr];
	118	else
	119	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
	120	ichx_priv.gpio_base);
	121
6ed9f9c4 PT	122	if (val)
	123	data \|= 1 << bit;
	124	else
	125	data &= ~(1 << bit);
bb62a35b VD	126	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	127	ichx_priv.gpio_base);
e6540f33 VD	128	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	129	ichx_priv.outlvl_cache[reg_nr] = data;
	130
bb62a35b VD	131	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	132	ichx_priv.gpio_base);
6ed9f9c4 PT	133	if (verify && data != tmp)
	134	ret = -EPERM;
	135
	136	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	137
	138	return ret;
	139	}
	140
	141	static int ichx_read_bit(int reg, unsigned nr)
	142	{
	143	unsigned long flags;
	144	u32 data;
	145	int reg_nr = nr / 32;
	146	int bit = nr & 0x1f;
	147
	148	spin_lock_irqsave(&ichx_priv.lock, flags);
	149
bb62a35b VD	150	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	151	ichx_priv.gpio_base);
6ed9f9c4	152
e6540f33 VD	153	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	154	data = ichx_priv.outlvl_cache[reg_nr] \| data;
	155
6ed9f9c4 PT	156	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	157
	158	return data & (1 << bit) ? 1 : 0;
	159	}
	160
e97f9b52	161	static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
4f600ada	162	{
61d793bb	163	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
4f600ada JD	164	}
4f600ada JD	165
6ed9f9c4 PT	166	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	167	{
	168	/*
	169	* Try setting pin as an input and verify it worked since many pins
	170	* are output-only.
	171	*/
	172	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
	173	return -EINVAL;
	174
	175	return 0;
	176	}
	177
	178	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	179	int val)
	180	{
7f6569f5	181	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
ba7f74fe	182	if (nr < 32 && ichx_priv.desc->have_blink)
7f6569f5 VD	183	ichx_write_bit(GPO_BLINK, nr, 0, 0);
7f6569f5 VD	184
6ed9f9c4 PT	185	/* Set GPIO output value. */
	186	ichx_write_bit(GPIO_LVL, nr, val, 0);
	187
	188	/*
	189	* Try setting pin as an output and verify it worked since many pins
	190	* are input-only.
	191	*/
	192	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
	193	return -EINVAL;
	194
	195	return 0;
	196	}
	197
	198	static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
	199	{
	200	return ichx_read_bit(GPIO_LVL, nr);
	201	}
	202
	203	static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
	204	{
	205	unsigned long flags;
	206	u32 data;
	207
	208	/*
	209	* GPI 0 - 15 need to be read from the power management registers on
	210	* a ICH6/3100 bridge.
	211	*/
	212	if (nr < 16) {
	213	if (!ichx_priv.pm_base)
	214	return -ENXIO;
	215
	216	spin_lock_irqsave(&ichx_priv.lock, flags);
	217
	218	/* GPI 0 - 15 are latched, write 1 to clear*/
	219	ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
	220	data = ICHX_READ(0, ichx_priv.pm_base);
	221
	222	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	223
	224	return (data >> 16) & (1 << nr) ? 1 : 0;
	225	} else {
	226	return ichx_gpio_get(chip, nr);
	227	}
	228	}
	229
	230	static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
	231	{
25f27db4 JD	232	if (!ichx_gpio_check_available(chip, nr))
	233	return -ENXIO;
	234
6ed9f9c4 PT	235	/*
	236	* Note we assume the BIOS properly set a bridge's USE value. Some
	237	* chips (eg Intel 3100) have bogus USE values though, so first see if
	238	* the chipset's USE value can be trusted for this specific bit.
	239	* If it can't be trusted, assume that the pin can be used as a GPIO.
	240	*/
	241	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
2ab3a749	242	return 0;
6ed9f9c4 PT	243
	244	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
	245	}
	246
	247	static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
	248	{
	249	/*
	250	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	251	* bridge as they are controlled by USE register bits 0 and 1. See
	252	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	253	* additional info.
	254	*/
	255	if (nr == 16 \|\| nr == 17)
	256	nr -= 16;
	257
	258	return ichx_gpio_request(chip, nr);
	259	}
	260
	261	static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
	262	{
	263	ichx_write_bit(GPIO_LVL, nr, val, 0);
	264	}
	265
3836309d	266	static void ichx_gpiolib_setup(struct gpio_chip *chip)
6ed9f9c4 PT	267	{
	268	chip->owner = THIS_MODULE;
	269	chip->label = DRV_NAME;
	270	chip->dev = &ichx_priv.dev->dev;
	271
	272	/* Allow chip-specific overrides of request()/get() */
	273	chip->request = ichx_priv.desc->request ?
	274	ichx_priv.desc->request : ichx_gpio_request;
	275	chip->get = ichx_priv.desc->get ?
	276	ichx_priv.desc->get : ichx_gpio_get;
	277
	278	chip->set = ichx_gpio_set;
	279	chip->direction_input = ichx_gpio_direction_input;
	280	chip->direction_output = ichx_gpio_direction_output;
	281	chip->base = modparam_gpiobase;
	282	chip->ngpio = ichx_priv.desc->ngpio;
9fb1f39e	283	chip->can_sleep = false;
6ed9f9c4 PT	284	chip->dbg_show = NULL;
	285	}
	286
	287	/* ICH6-based, 631xesb-based */
	288	static struct ichx_desc ich6_desc = {
	289	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	290	.request = ich6_gpio_request,
	291	.get = ich6_gpio_get,
	292
	293	/* GPIO 0-15 are read in the GPE0_STS PM register */
	294	.uses_gpe0 = true,
	295
	296	.ngpio = 50,
ba7f74fe	297	.have_blink = true,
6ed9f9c4 PT	298	};
	299
	300	/* Intel 3100 */
	301	static struct ichx_desc i3100_desc = {
	302	/*
	303	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	304	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
	305	* Datasheet for more info.
	306	*/
	307	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
	308
	309	/* The 3100 needs fixups for GPIO 0 - 17 */
	310	.request = ich6_gpio_request,
	311	.get = ich6_gpio_get,
	312
	313	/* GPIO 0-15 are read in the GPE0_STS PM register */
	314	.uses_gpe0 = true,
	315
	316	.ngpio = 50,
	317	};
	318
	319	/* ICH7 and ICH8-based */
	320	static struct ichx_desc ich7_desc = {
	321	.ngpio = 50,
ba7f74fe	322	.have_blink = true,
bb62a35b VD	323	.regs = ichx_regs,
bb62a35b VD	324	.reglen = ichx_reglen,
6ed9f9c4 PT	325	};
	326
	327	/* ICH9-based */
	328	static struct ichx_desc ich9_desc = {
	329	.ngpio = 61,
ba7f74fe	330	.have_blink = true,
bb62a35b VD	331	.regs = ichx_regs,
bb62a35b VD	332	.reglen = ichx_reglen,
6ed9f9c4 PT	333	};
	334
	335	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
	336	static struct ichx_desc ich10_cons_desc = {
	337	.ngpio = 61,
ba7f74fe	338	.have_blink = true,
bb62a35b VD	339	.regs = ichx_regs,
bb62a35b VD	340	.reglen = ichx_reglen,
6ed9f9c4 PT	341	};
	342	static struct ichx_desc ich10_corp_desc = {
	343	.ngpio = 72,
ba7f74fe	344	.have_blink = true,
bb62a35b VD	345	.regs = ichx_regs,
bb62a35b VD	346	.reglen = ichx_reglen,
6ed9f9c4 PT	347	};
	348
	349	/* Intel 5 series, 6 series, 3400 series, and C200 series */
	350	static struct ichx_desc intel5_desc = {
	351	.ngpio = 76,
bb62a35b VD	352	.regs = ichx_regs,
bb62a35b VD	353	.reglen = ichx_reglen,
6ed9f9c4 PT	354	};
6ed9f9c4 PT	355
3836309d	356	static int ichx_gpio_request_regions(struct resource *res_base,
4f600ada JD	357	const char *name, u8 use_gpio)
	358	{
	359	int i;
	360
	361	if (!res_base \|\| !res_base->start \|\| !res_base->end)
	362	return -ENODEV;
	363
bb62a35b	364	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
4f600ada JD	365	if (!(use_gpio & (1 << i)))
4f600ada JD	366	continue;
bb62a35b VD	367	if (!request_region(
	368	res_base->start + ichx_priv.desc->regs[0][i],
	369	ichx_priv.desc->reglen[i], name))
4f600ada JD	370	goto request_err;
	371	}
	372	return 0;
	373
	374	request_err:
	375	/* Clean up: release already requested regions, if any */
	376	for (i--; i >= 0; i--) {
	377	if (!(use_gpio & (1 << i)))
	378	continue;
bb62a35b VD	379	release_region(res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	380	ichx_priv.desc->reglen[i]);
4f600ada JD	381	}
	382	return -EBUSY;
	383	}
	384
	385	static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
	386	{
	387	int i;
	388
bb62a35b	389	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
4f600ada JD	390	if (!(use_gpio & (1 << i)))
4f600ada JD	391	continue;
bb62a35b VD	392	release_region(res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	393	ichx_priv.desc->reglen[i]);
4f600ada JD	394	}
	395	}
	396
3836309d	397	static int ichx_gpio_probe(struct platform_device *pdev)
6ed9f9c4 PT	398	{
	399	struct resource res_base, res_pm;
	400	int err;
e56aee18	401	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
6ed9f9c4 PT	402
	403	if (!ich_info)
	404	return -ENODEV;
	405
	406	ichx_priv.dev = pdev;
	407
	408	switch (ich_info->gpio_version) {
	409	case ICH_I3100_GPIO:
	410	ichx_priv.desc = &i3100_desc;
	411	break;
	412	case ICH_V5_GPIO:
	413	ichx_priv.desc = &intel5_desc;
	414	break;
	415	case ICH_V6_GPIO:
	416	ichx_priv.desc = &ich6_desc;
	417	break;
	418	case ICH_V7_GPIO:
	419	ichx_priv.desc = &ich7_desc;
	420	break;
	421	case ICH_V9_GPIO:
	422	ichx_priv.desc = &ich9_desc;
	423	break;
	424	case ICH_V10CORP_GPIO:
	425	ichx_priv.desc = &ich10_corp_desc;
	426	break;
	427	case ICH_V10CONS_GPIO:
	428	ichx_priv.desc = &ich10_cons_desc;
	429	break;
	430	default:
	431	return -ENODEV;
	432	}
	433
d39a948f	434	spin_lock_init(&ichx_priv.lock);
6ed9f9c4	435	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
4f600ada JD	436	ichx_priv.use_gpio = ich_info->use_gpio;
	437	err = ichx_gpio_request_regions(res_base, pdev->name,
	438	ichx_priv.use_gpio);
	439	if (err)
	440	return err;
6ed9f9c4 PT	441
	442	ichx_priv.gpio_base = res_base;
	443
	444	/*
	445	* If necessary, determine the I/O address of ACPI/power management
	446	* registers which are needed to read the the GPE0 register for GPI pins
	447	* 0 - 15 on some chipsets.
	448	*/
	449	if (!ichx_priv.desc->uses_gpe0)
	450	goto init;
	451
	452	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	453	if (!res_pm) {
	454	pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
	455	goto init;
	456	}
	457
	458	if (!request_region(res_pm->start, resource_size(res_pm),
	459	pdev->name)) {
	460	pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
	461	goto init;
	462	}
	463
	464	ichx_priv.pm_base = res_pm;
	465
	466	init:
	467	ichx_gpiolib_setup(&ichx_priv.chip);
	468	err = gpiochip_add(&ichx_priv.chip);
	469	if (err) {
	470	pr_err("Failed to register GPIOs\n");
	471	goto add_err;
	472	}
	473
	474	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	475	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
	476
	477	return 0;
	478
	479	add_err:
4f600ada	480	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
6ed9f9c4 PT	481	if (ichx_priv.pm_base)
	482	release_region(ichx_priv.pm_base->start,
	483	resource_size(ichx_priv.pm_base));
	484	return err;
	485	}
	486
206210ce	487	static int ichx_gpio_remove(struct platform_device *pdev)
6ed9f9c4 PT	488	{
	489	int err;
	490
	491	err = gpiochip_remove(&ichx_priv.chip);
	492	if (err) {
	493	dev_err(&pdev->dev, "%s failed, %d\n",
	494	"gpiochip_remove()", err);
	495	return err;
	496	}
	497
4f600ada	498	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
6ed9f9c4 PT	499	if (ichx_priv.pm_base)
	500	release_region(ichx_priv.pm_base->start,
	501	resource_size(ichx_priv.pm_base));
	502
	503	return 0;
	504	}
	505
	506	static struct platform_driver ichx_gpio_driver = {
	507	.driver = {
	508	.owner = THIS_MODULE,
	509	.name = DRV_NAME,
	510	},
	511	.probe = ichx_gpio_probe,
8283c4ff	512	.remove = ichx_gpio_remove,
6ed9f9c4 PT	513	};
	514
	515	module_platform_driver(ichx_gpio_driver);
	516
	517	MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
	518	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
	519	MODULE_LICENSE("GPL");
	520	MODULE_ALIAS("platform:"DRV_NAME);