[linux-2.6-block.git] / drivers / gpio / gpio-ich.c

/*
 * Intel ICH6-10, Series 5 and 6 GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mfd/lpc_ich.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
	GPO_BLINK
};

static const u8 ichx_regs[4][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
	{0x18, 0x18, 0x18},	/* BLINK offset */
};

static const u8 ichx_reglen[3] = {
	0x30, 0x10, 0x10,
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* chipset registers */
	const u8 (*regs)[3];
	const u8 *reglen;

	/* GPO_BLINK is available on this chipset */
	bool have_blink;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned offset);
	int (*get)(struct gpio_chip *chip, unsigned offset);
};

static struct {
	spinlock_t lock;
	struct platform_device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Mangagment IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
	u8 use_gpio;		/* Which GPIO groups are usable */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
			   "which is the default.");

static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;
	int ret = 0;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);
	if (val)
		data |= 1 << bit;
	else
		data &= ~(1 << bit);
	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);
	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			ichx_priv.gpio_base);
	if (verify && data != tmp)
		ret = -EPERM;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return ret;
}

static int ichx_read_bit(int reg, unsigned nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return data & (1 << bit) ? 1 : 0;
}

static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
{
	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
					int val)
{
	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
	if (nr < 32 && ichx_priv.desc->have_blink)
		ichx_write_bit(GPO_BLINK, nr, 0, 0);

	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	unsigned long flags;
	u32 data;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return (data >> 16) & (1 << nr) ? 1 : 0;
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
		return 0;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->dev = &ichx_priv.dev->dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = false;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.have_blink = true,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

static int ichx_gpio_request_regions(struct resource *res_base,
						const char *name, u8 use_gpio)
{
	int i;

	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		if (!request_region(
				res_base->start + ichx_priv.desc->regs[0][i],
				ichx_priv.desc->reglen[i], name))
			goto request_err;
	}
	return 0;

request_err:
	/* Clean up: release already requested regions, if any */
	for (i--; i >= 0; i--) {
		if (!(use_gpio & (1 << i)))
			continue;
		release_region(res_base->start + ichx_priv.desc->regs[0][i],
			       ichx_priv.desc->reglen[i]);
	}
	return -EBUSY;
}

static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		release_region(res_base->start + ichx_priv.desc->regs[0][i],
			       ichx_priv.desc->reglen[i]);
	}
}

static int ichx_gpio_probe(struct platform_device *pdev)
{
	struct resource *res_base, *res_pm;
	int err;
	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);

	if (!ich_info)
		return -ENODEV;

	ichx_priv.dev = pdev;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	default:
		return -ENODEV;
	}

	spin_lock_init(&ichx_priv.lock);
	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	ichx_priv.use_gpio = ich_info->use_gpio;
	err = ichx_gpio_request_regions(res_base, pdev->name,
					ichx_priv.use_gpio);
	if (err)
		return err;

	ichx_priv.gpio_base = res_base;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!request_region(res_pm->start, resource_size(res_pm),
			pdev->name)) {
		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = gpiochip_add(&ichx_priv.chip);
	if (err) {
		pr_err("Failed to register GPIOs\n");
		goto add_err;
	}

	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);

	return 0;

add_err:
	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));
	return err;
}

static int ichx_gpio_remove(struct platform_device *pdev)
{
	int err;

	err = gpiochip_remove(&ichx_priv.chip);
	if (err) {
		dev_err(&pdev->dev, "%s failed, %d\n",
				"gpiochip_remove()", err);
		return err;
	}

	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
	.remove		= ichx_gpio_remove,
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
6ed9f9c4 PT	1	/*
	2	* Intel ICH6-10, Series 5 and 6 GPIO driver
	3	*
	4	* Copyright (C) 2010 Extreme Engineering Solutions.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
	23	#include <linux/module.h>
	24	#include <linux/pci.h>
	25	#include <linux/gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/mfd/lpc_ich.h>
	28
	29	#define DRV_NAME "gpio_ich"
	30
	31	/*
	32	* GPIO register offsets in GPIO I/O space.
	33	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	34	* LVLx registers. Logic in the read/write functions takes a register and
	35	* an absolute bit number and determines the proper register offset and bit
	36	* number in that register. For example, to read the value of GPIO bit 50
	37	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	38	* bit 18 (50%32).
	39	*/
	40	enum GPIO_REG {
	41	GPIO_USE_SEL = 0,
	42	GPIO_IO_SEL,
	43	GPIO_LVL,
7f6569f5	44	GPO_BLINK
6ed9f9c4 PT	45	};
6ed9f9c4 PT	46
7f6569f5	47	static const u8 ichx_regs[4][3] = {
6ed9f9c4 PT	48	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	49	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	50	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
7f6569f5	51	{0x18, 0x18, 0x18}, /* BLINK offset */
6ed9f9c4 PT	52	};
6ed9f9c4 PT	53
4f600ada JD	54	static const u8 ichx_reglen[3] = {
	55	0x30, 0x10, 0x10,
	56	};
	57
6ed9f9c4 PT	58	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	59	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	60
	61	struct ichx_desc {
	62	/* Max GPIO pins the chipset can have */
	63	uint ngpio;
	64
bb62a35b VD	65	/* chipset registers */
	66	const u8 (*regs)[3];
	67	const u8 *reglen;
	68
ba7f74fe VD	69	/* GPO_BLINK is available on this chipset */
	70	bool have_blink;
	71
6ed9f9c4 PT	72	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	73	bool uses_gpe0;
	74
	75	/* USE_SEL is bogus on some chipsets, eg 3100 */
	76	u32 use_sel_ignore[3];
	77
	78	/* Some chipsets have quirks, let these use their own request/get */
	79	int (request)(struct gpio_chip chip, unsigned offset);
	80	int (get)(struct gpio_chip chip, unsigned offset);
	81	};
	82
	83	static struct {
	84	spinlock_t lock;
	85	struct platform_device *dev;
	86	struct gpio_chip chip;
	87	struct resource gpio_base; / GPIO IO base */
	88	struct resource pm_base; / Power Mangagment IO base */
	89	struct ichx_desc desc; / Pointer to chipset-specific description */
	90	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
4f600ada	91	u8 use_gpio; /* Which GPIO groups are usable */
6ed9f9c4 PT	92	} ichx_priv;
	93
	94	static int modparam_gpiobase = -1; /* dynamic */
	95	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
	96	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
	97	"which is the default.");
	98
	99	static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
	100	{
	101	unsigned long flags;
	102	u32 data, tmp;
	103	int reg_nr = nr / 32;
	104	int bit = nr & 0x1f;
	105	int ret = 0;
	106
	107	spin_lock_irqsave(&ichx_priv.lock, flags);
	108
bb62a35b VD	109	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	110	ichx_priv.gpio_base);
6ed9f9c4 PT	111	if (val)
	112	data \|= 1 << bit;
	113	else
	114	data &= ~(1 << bit);
bb62a35b VD	115	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
	116	ichx_priv.gpio_base);
	117	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
	118	ichx_priv.gpio_base);
6ed9f9c4 PT	119	if (verify && data != tmp)
	120	ret = -EPERM;
	121
	122	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	123
	124	return ret;
	125	}
	126
	127	static int ichx_read_bit(int reg, unsigned nr)
	128	{
	129	unsigned long flags;
	130	u32 data;
	131	int reg_nr = nr / 32;
	132	int bit = nr & 0x1f;
	133
	134	spin_lock_irqsave(&ichx_priv.lock, flags);
	135
bb62a35b VD	136	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	137	ichx_priv.gpio_base);
6ed9f9c4 PT	138
	139	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	140
	141	return data & (1 << bit) ? 1 : 0;
	142	}
	143
e97f9b52	144	static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
4f600ada	145	{
61d793bb	146	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
4f600ada JD	147	}
4f600ada JD	148
6ed9f9c4 PT	149	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	150	{
	151	/*
	152	* Try setting pin as an input and verify it worked since many pins
	153	* are output-only.
	154	*/
	155	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
	156	return -EINVAL;
	157
	158	return 0;
	159	}
	160
	161	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	162	int val)
	163	{
7f6569f5	164	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
ba7f74fe	165	if (nr < 32 && ichx_priv.desc->have_blink)
7f6569f5 VD	166	ichx_write_bit(GPO_BLINK, nr, 0, 0);
7f6569f5 VD	167
6ed9f9c4 PT	168	/* Set GPIO output value. */
	169	ichx_write_bit(GPIO_LVL, nr, val, 0);
	170
	171	/*
	172	* Try setting pin as an output and verify it worked since many pins
	173	* are input-only.
	174	*/
	175	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
	176	return -EINVAL;
	177
	178	return 0;
	179	}
	180
	181	static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
	182	{
	183	return ichx_read_bit(GPIO_LVL, nr);
	184	}
	185
	186	static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
	187	{
	188	unsigned long flags;
	189	u32 data;
	190
	191	/*
	192	* GPI 0 - 15 need to be read from the power management registers on
	193	* a ICH6/3100 bridge.
	194	*/
	195	if (nr < 16) {
	196	if (!ichx_priv.pm_base)
	197	return -ENXIO;
	198
	199	spin_lock_irqsave(&ichx_priv.lock, flags);
	200
	201	/* GPI 0 - 15 are latched, write 1 to clear*/
	202	ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
	203	data = ICHX_READ(0, ichx_priv.pm_base);
	204
	205	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	206
	207	return (data >> 16) & (1 << nr) ? 1 : 0;
	208	} else {
	209	return ichx_gpio_get(chip, nr);
	210	}
	211	}
	212
	213	static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
	214	{
25f27db4 JD	215	if (!ichx_gpio_check_available(chip, nr))
	216	return -ENXIO;
	217
6ed9f9c4 PT	218	/*
	219	* Note we assume the BIOS properly set a bridge's USE value. Some
	220	* chips (eg Intel 3100) have bogus USE values though, so first see if
	221	* the chipset's USE value can be trusted for this specific bit.
	222	* If it can't be trusted, assume that the pin can be used as a GPIO.
	223	*/
	224	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
2ab3a749	225	return 0;
6ed9f9c4 PT	226
	227	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
	228	}
	229
	230	static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
	231	{
	232	/*
	233	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	234	* bridge as they are controlled by USE register bits 0 and 1. See
	235	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	236	* additional info.
	237	*/
	238	if (nr == 16 \|\| nr == 17)
	239	nr -= 16;
	240
	241	return ichx_gpio_request(chip, nr);
	242	}
	243
	244	static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
	245	{
	246	ichx_write_bit(GPIO_LVL, nr, val, 0);
	247	}
	248
3836309d	249	static void ichx_gpiolib_setup(struct gpio_chip *chip)
6ed9f9c4 PT	250	{
	251	chip->owner = THIS_MODULE;
	252	chip->label = DRV_NAME;
	253	chip->dev = &ichx_priv.dev->dev;
	254
	255	/* Allow chip-specific overrides of request()/get() */
	256	chip->request = ichx_priv.desc->request ?
	257	ichx_priv.desc->request : ichx_gpio_request;
	258	chip->get = ichx_priv.desc->get ?
	259	ichx_priv.desc->get : ichx_gpio_get;
	260
	261	chip->set = ichx_gpio_set;
	262	chip->direction_input = ichx_gpio_direction_input;
	263	chip->direction_output = ichx_gpio_direction_output;
	264	chip->base = modparam_gpiobase;
	265	chip->ngpio = ichx_priv.desc->ngpio;
9fb1f39e	266	chip->can_sleep = false;
6ed9f9c4 PT	267	chip->dbg_show = NULL;
	268	}
	269
	270	/* ICH6-based, 631xesb-based */
	271	static struct ichx_desc ich6_desc = {
	272	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	273	.request = ich6_gpio_request,
	274	.get = ich6_gpio_get,
	275
	276	/* GPIO 0-15 are read in the GPE0_STS PM register */
	277	.uses_gpe0 = true,
	278
	279	.ngpio = 50,
ba7f74fe	280	.have_blink = true,
6ed9f9c4 PT	281	};
	282
	283	/* Intel 3100 */
	284	static struct ichx_desc i3100_desc = {
	285	/*
	286	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	287	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
	288	* Datasheet for more info.
	289	*/
	290	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
	291
	292	/* The 3100 needs fixups for GPIO 0 - 17 */
	293	.request = ich6_gpio_request,
	294	.get = ich6_gpio_get,
	295
	296	/* GPIO 0-15 are read in the GPE0_STS PM register */
	297	.uses_gpe0 = true,
	298
	299	.ngpio = 50,
	300	};
	301
	302	/* ICH7 and ICH8-based */
	303	static struct ichx_desc ich7_desc = {
	304	.ngpio = 50,
ba7f74fe	305	.have_blink = true,
bb62a35b VD	306	.regs = ichx_regs,
bb62a35b VD	307	.reglen = ichx_reglen,
6ed9f9c4 PT	308	};
	309
	310	/* ICH9-based */
	311	static struct ichx_desc ich9_desc = {
	312	.ngpio = 61,
ba7f74fe	313	.have_blink = true,
bb62a35b VD	314	.regs = ichx_regs,
bb62a35b VD	315	.reglen = ichx_reglen,
6ed9f9c4 PT	316	};
	317
	318	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
	319	static struct ichx_desc ich10_cons_desc = {
	320	.ngpio = 61,
ba7f74fe	321	.have_blink = true,
bb62a35b VD	322	.regs = ichx_regs,
bb62a35b VD	323	.reglen = ichx_reglen,
6ed9f9c4 PT	324	};
	325	static struct ichx_desc ich10_corp_desc = {
	326	.ngpio = 72,
ba7f74fe	327	.have_blink = true,
bb62a35b VD	328	.regs = ichx_regs,
bb62a35b VD	329	.reglen = ichx_reglen,
6ed9f9c4 PT	330	};
	331
	332	/* Intel 5 series, 6 series, 3400 series, and C200 series */
	333	static struct ichx_desc intel5_desc = {
	334	.ngpio = 76,
bb62a35b VD	335	.regs = ichx_regs,
bb62a35b VD	336	.reglen = ichx_reglen,
6ed9f9c4 PT	337	};
6ed9f9c4 PT	338
3836309d	339	static int ichx_gpio_request_regions(struct resource *res_base,
4f600ada JD	340	const char *name, u8 use_gpio)
	341	{
	342	int i;
	343
	344	if (!res_base \|\| !res_base->start \|\| !res_base->end)
	345	return -ENODEV;
	346
bb62a35b	347	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
4f600ada JD	348	if (!(use_gpio & (1 << i)))
4f600ada JD	349	continue;
bb62a35b VD	350	if (!request_region(
	351	res_base->start + ichx_priv.desc->regs[0][i],
	352	ichx_priv.desc->reglen[i], name))
4f600ada JD	353	goto request_err;
	354	}
	355	return 0;
	356
	357	request_err:
	358	/* Clean up: release already requested regions, if any */
	359	for (i--; i >= 0; i--) {
	360	if (!(use_gpio & (1 << i)))
	361	continue;
bb62a35b VD	362	release_region(res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	363	ichx_priv.desc->reglen[i]);
4f600ada JD	364	}
	365	return -EBUSY;
	366	}
	367
	368	static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
	369	{
	370	int i;
	371
bb62a35b	372	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
4f600ada JD	373	if (!(use_gpio & (1 << i)))
4f600ada JD	374	continue;
bb62a35b VD	375	release_region(res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	376	ichx_priv.desc->reglen[i]);
4f600ada JD	377	}
	378	}
	379
3836309d	380	static int ichx_gpio_probe(struct platform_device *pdev)
6ed9f9c4 PT	381	{
	382	struct resource res_base, res_pm;
	383	int err;
e56aee18	384	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
6ed9f9c4 PT	385
	386	if (!ich_info)
	387	return -ENODEV;
	388
	389	ichx_priv.dev = pdev;
	390
	391	switch (ich_info->gpio_version) {
	392	case ICH_I3100_GPIO:
	393	ichx_priv.desc = &i3100_desc;
	394	break;
	395	case ICH_V5_GPIO:
	396	ichx_priv.desc = &intel5_desc;
	397	break;
	398	case ICH_V6_GPIO:
	399	ichx_priv.desc = &ich6_desc;
	400	break;
	401	case ICH_V7_GPIO:
	402	ichx_priv.desc = &ich7_desc;
	403	break;
	404	case ICH_V9_GPIO:
	405	ichx_priv.desc = &ich9_desc;
	406	break;
	407	case ICH_V10CORP_GPIO:
	408	ichx_priv.desc = &ich10_corp_desc;
	409	break;
	410	case ICH_V10CONS_GPIO:
	411	ichx_priv.desc = &ich10_cons_desc;
	412	break;
	413	default:
	414	return -ENODEV;
	415	}
	416
d39a948f	417	spin_lock_init(&ichx_priv.lock);
6ed9f9c4	418	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
4f600ada JD	419	ichx_priv.use_gpio = ich_info->use_gpio;
	420	err = ichx_gpio_request_regions(res_base, pdev->name,
	421	ichx_priv.use_gpio);
	422	if (err)
	423	return err;
6ed9f9c4 PT	424
	425	ichx_priv.gpio_base = res_base;
	426
	427	/*
	428	* If necessary, determine the I/O address of ACPI/power management
	429	* registers which are needed to read the the GPE0 register for GPI pins
	430	* 0 - 15 on some chipsets.
	431	*/
	432	if (!ichx_priv.desc->uses_gpe0)
	433	goto init;
	434
	435	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	436	if (!res_pm) {
	437	pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
	438	goto init;
	439	}
	440
	441	if (!request_region(res_pm->start, resource_size(res_pm),
	442	pdev->name)) {
	443	pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
	444	goto init;
	445	}
	446
	447	ichx_priv.pm_base = res_pm;
	448
	449	init:
	450	ichx_gpiolib_setup(&ichx_priv.chip);
	451	err = gpiochip_add(&ichx_priv.chip);
	452	if (err) {
	453	pr_err("Failed to register GPIOs\n");
	454	goto add_err;
	455	}
	456
	457	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	458	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
	459
	460	return 0;
	461
	462	add_err:
4f600ada	463	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
6ed9f9c4 PT	464	if (ichx_priv.pm_base)
	465	release_region(ichx_priv.pm_base->start,
	466	resource_size(ichx_priv.pm_base));
	467	return err;
	468	}
	469
206210ce	470	static int ichx_gpio_remove(struct platform_device *pdev)
6ed9f9c4 PT	471	{
	472	int err;
	473
	474	err = gpiochip_remove(&ichx_priv.chip);
	475	if (err) {
	476	dev_err(&pdev->dev, "%s failed, %d\n",
	477	"gpiochip_remove()", err);
	478	return err;
	479	}
	480
4f600ada	481	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
6ed9f9c4 PT	482	if (ichx_priv.pm_base)
	483	release_region(ichx_priv.pm_base->start,
	484	resource_size(ichx_priv.pm_base));
	485
	486	return 0;
	487	}
	488
	489	static struct platform_driver ichx_gpio_driver = {
	490	.driver = {
	491	.owner = THIS_MODULE,
	492	.name = DRV_NAME,
	493	},
	494	.probe = ichx_gpio_probe,
8283c4ff	495	.remove = ichx_gpio_remove,
6ed9f9c4 PT	496	};
	497
	498	module_platform_driver(ichx_gpio_driver);
	499
	500	MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
	501	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
	502	MODULE_LICENSE("GPL");
	503	MODULE_ALIAS("platform:"DRV_NAME);