[linux-2.6-block.git] / drivers / gpio / gpio-ich.c

/*
 * Intel ICH6-10, Series 5 and 6 GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mfd/lpc_ich.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
};

static const u8 ichx_regs[3][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
};

static const u8 ichx_reglen[3] = {
	0x30, 0x10, 0x10,
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned offset);
	int (*get)(struct gpio_chip *chip, unsigned offset);
};

static struct {
	spinlock_t lock;
	struct platform_device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Mangagment IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
	u8 use_gpio;		/* Which GPIO groups are usable */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
			   "which is the default.");

static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;
	int ret = 0;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	if (val)
		data |= 1 << bit;
	else
		data &= ~(1 << bit);
	ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	if (verify && data != tmp)
		ret = -EPERM;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return ret;
}

static int ichx_read_bit(int reg, unsigned nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return data & (1 << bit) ? 1 : 0;
}

static int ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
{
	return (ichx_priv.use_gpio & (1 << (nr / 32))) ? 0 : -ENXIO;
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	if (!ichx_gpio_check_available(gpio, nr))
		return -ENXIO;

	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
					int val)
{
	if (!ichx_gpio_check_available(gpio, nr))
		return -ENXIO;

	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	unsigned long flags;
	u32 data;

	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return (data >> 16) & (1 << nr) ? 1 : 0;
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
		return 1;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void __devinit ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->dev = &ichx_priv.dev->dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = 0;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
};

static int __devinit ichx_gpio_request_regions(struct resource *res_base,
						const char *name, u8 use_gpio)
{
	int i;

	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		if (!request_region(res_base->start + ichx_regs[0][i],
				    ichx_reglen[i], name))
			goto request_err;
	}
	return 0;

request_err:
	/* Clean up: release already requested regions, if any */
	for (i--; i >= 0; i--) {
		if (!(use_gpio & (1 << i)))
			continue;
		release_region(res_base->start + ichx_regs[0][i],
			       ichx_reglen[i]);
	}
	return -EBUSY;
}

static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		release_region(res_base->start + ichx_regs[0][i],
			       ichx_reglen[i]);
	}
}

static int __devinit ichx_gpio_probe(struct platform_device *pdev)
{
	struct resource *res_base, *res_pm;
	int err;
	struct lpc_ich_info *ich_info = pdev->dev.platform_data;

	if (!ich_info)
		return -ENODEV;

	ichx_priv.dev = pdev;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	default:
		return -ENODEV;
	}

	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	ichx_priv.use_gpio = ich_info->use_gpio;
	err = ichx_gpio_request_regions(res_base, pdev->name,
					ichx_priv.use_gpio);
	if (err)
		return err;

	ichx_priv.gpio_base = res_base;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!request_region(res_pm->start, resource_size(res_pm),
			pdev->name)) {
		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = gpiochip_add(&ichx_priv.chip);
	if (err) {
		pr_err("Failed to register GPIOs\n");
		goto add_err;
	}

	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);

	return 0;

add_err:
	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));
	return err;
}

static int __devexit ichx_gpio_remove(struct platform_device *pdev)
{
	int err;

	err = gpiochip_remove(&ichx_priv.chip);
	if (err) {
		dev_err(&pdev->dev, "%s failed, %d\n",
				"gpiochip_remove()", err);
		return err;
	}

	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
	.remove		= ichx_gpio_remove,
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
6ed9f9c4 PT	1	/*
	2	* Intel ICH6-10, Series 5 and 6 GPIO driver
	3	*
	4	* Copyright (C) 2010 Extreme Engineering Solutions.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
	23	#include <linux/module.h>
	24	#include <linux/pci.h>
	25	#include <linux/gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/mfd/lpc_ich.h>
	28
	29	#define DRV_NAME "gpio_ich"
	30
	31	/*
	32	* GPIO register offsets in GPIO I/O space.
	33	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	34	* LVLx registers. Logic in the read/write functions takes a register and
	35	* an absolute bit number and determines the proper register offset and bit
	36	* number in that register. For example, to read the value of GPIO bit 50
	37	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	38	* bit 18 (50%32).
	39	*/
	40	enum GPIO_REG {
	41	GPIO_USE_SEL = 0,
	42	GPIO_IO_SEL,
	43	GPIO_LVL,
	44	};
	45
	46	static const u8 ichx_regs[3][3] = {
	47	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	48	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	49	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
	50	};
	51
4f600ada JD	52	static const u8 ichx_reglen[3] = {
	53	0x30, 0x10, 0x10,
	54	};
	55
6ed9f9c4 PT	56	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	57	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	58
	59	struct ichx_desc {
	60	/* Max GPIO pins the chipset can have */
	61	uint ngpio;
	62
	63	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	64	bool uses_gpe0;
	65
	66	/* USE_SEL is bogus on some chipsets, eg 3100 */
	67	u32 use_sel_ignore[3];
	68
	69	/* Some chipsets have quirks, let these use their own request/get */
	70	int (request)(struct gpio_chip chip, unsigned offset);
	71	int (get)(struct gpio_chip chip, unsigned offset);
	72	};
	73
	74	static struct {
	75	spinlock_t lock;
	76	struct platform_device *dev;
	77	struct gpio_chip chip;
	78	struct resource gpio_base; / GPIO IO base */
	79	struct resource pm_base; / Power Mangagment IO base */
	80	struct ichx_desc desc; / Pointer to chipset-specific description */
	81	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
4f600ada	82	u8 use_gpio; /* Which GPIO groups are usable */
6ed9f9c4 PT	83	} ichx_priv;
	84
	85	static int modparam_gpiobase = -1; /* dynamic */
	86	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
	87	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
	88	"which is the default.");
	89
	90	static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
	91	{
	92	unsigned long flags;
	93	u32 data, tmp;
	94	int reg_nr = nr / 32;
	95	int bit = nr & 0x1f;
	96	int ret = 0;
	97
	98	spin_lock_irqsave(&ichx_priv.lock, flags);
	99
	100	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	101	if (val)
	102	data \|= 1 << bit;
	103	else
	104	data &= ~(1 << bit);
	105	ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	106	tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	107	if (verify && data != tmp)
	108	ret = -EPERM;
	109
	110	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	111
	112	return ret;
	113	}
	114
	115	static int ichx_read_bit(int reg, unsigned nr)
	116	{
	117	unsigned long flags;
	118	u32 data;
	119	int reg_nr = nr / 32;
	120	int bit = nr & 0x1f;
	121
	122	spin_lock_irqsave(&ichx_priv.lock, flags);
	123
	124	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	125
	126	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	127
	128	return data & (1 << bit) ? 1 : 0;
	129	}
	130
4f600ada JD	131	static int ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
	132	{
	133	return (ichx_priv.use_gpio & (1 << (nr / 32))) ? 0 : -ENXIO;
	134	}
	135
6ed9f9c4 PT	136	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
6ed9f9c4 PT	137	{
4f600ada JD	138	if (!ichx_gpio_check_available(gpio, nr))
	139	return -ENXIO;
	140
6ed9f9c4 PT	141	/*
	142	* Try setting pin as an input and verify it worked since many pins
	143	* are output-only.
	144	*/
	145	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
	146	return -EINVAL;
	147
	148	return 0;
	149	}
	150
	151	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	152	int val)
	153	{
4f600ada JD	154	if (!ichx_gpio_check_available(gpio, nr))
	155	return -ENXIO;
	156
6ed9f9c4 PT	157	/* Set GPIO output value. */
	158	ichx_write_bit(GPIO_LVL, nr, val, 0);
	159
	160	/*
	161	* Try setting pin as an output and verify it worked since many pins
	162	* are input-only.
	163	*/
	164	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
	165	return -EINVAL;
	166
	167	return 0;
	168	}
	169
	170	static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
	171	{
4f600ada JD	172	if (!ichx_gpio_check_available(chip, nr))
	173	return -ENXIO;
	174
6ed9f9c4 PT	175	return ichx_read_bit(GPIO_LVL, nr);
	176	}
	177
	178	static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
	179	{
	180	unsigned long flags;
	181	u32 data;
	182
4f600ada JD	183	if (!ichx_gpio_check_available(chip, nr))
	184	return -ENXIO;
	185
6ed9f9c4 PT	186	/*
	187	* GPI 0 - 15 need to be read from the power management registers on
	188	* a ICH6/3100 bridge.
	189	*/
	190	if (nr < 16) {
	191	if (!ichx_priv.pm_base)
	192	return -ENXIO;
	193
	194	spin_lock_irqsave(&ichx_priv.lock, flags);
	195
	196	/* GPI 0 - 15 are latched, write 1 to clear*/
	197	ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
	198	data = ICHX_READ(0, ichx_priv.pm_base);
	199
	200	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	201
	202	return (data >> 16) & (1 << nr) ? 1 : 0;
	203	} else {
	204	return ichx_gpio_get(chip, nr);
	205	}
	206	}
	207
	208	static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
	209	{
	210	/*
	211	* Note we assume the BIOS properly set a bridge's USE value. Some
	212	* chips (eg Intel 3100) have bogus USE values though, so first see if
	213	* the chipset's USE value can be trusted for this specific bit.
	214	* If it can't be trusted, assume that the pin can be used as a GPIO.
	215	*/
	216	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
	217	return 1;
	218
	219	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
	220	}
	221
	222	static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
	223	{
	224	/*
	225	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	226	* bridge as they are controlled by USE register bits 0 and 1. See
	227	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	228	* additional info.
	229	*/
	230	if (nr == 16 \|\| nr == 17)
	231	nr -= 16;
	232
	233	return ichx_gpio_request(chip, nr);
	234	}
	235
	236	static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
	237	{
	238	ichx_write_bit(GPIO_LVL, nr, val, 0);
	239	}
	240
	241	static void __devinit ichx_gpiolib_setup(struct gpio_chip *chip)
	242	{
	243	chip->owner = THIS_MODULE;
	244	chip->label = DRV_NAME;
	245	chip->dev = &ichx_priv.dev->dev;
	246
	247	/* Allow chip-specific overrides of request()/get() */
	248	chip->request = ichx_priv.desc->request ?
	249	ichx_priv.desc->request : ichx_gpio_request;
250	chip->get = ichx_priv.desc->get ?
251	ichx_priv.desc->get : ichx_gpio_get;
252
253	chip->set = ichx_gpio_set;
254	chip->direction_input = ichx_gpio_direction_input;
255	chip->direction_output = ichx_gpio_direction_output;
256	chip->base = modparam_gpiobase;
257	chip->ngpio = ichx_priv.desc->ngpio;
258	chip->can_sleep = 0;
259	chip->dbg_show = NULL;
260	}
261
262	/* ICH6-based, 631xesb-based */
263	static struct ichx_desc ich6_desc = {
264	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
265	.request = ich6_gpio_request,
266	.get = ich6_gpio_get,
267
268	/* GPIO 0-15 are read in the GPE0_STS PM register */
269	.uses_gpe0 = true,
270
271	.ngpio = 50,
272	};
273
274	/* Intel 3100 */
275	static struct ichx_desc i3100_desc = {
276	/*
277	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
278	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
279	* Datasheet for more info.
280	*/
281	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
282
283	/* The 3100 needs fixups for GPIO 0 - 17 */
284	.request = ich6_gpio_request,
285	.get = ich6_gpio_get,
286
287	/* GPIO 0-15 are read in the GPE0_STS PM register */
288	.uses_gpe0 = true,
289
290	.ngpio = 50,
291	};
292
293	/* ICH7 and ICH8-based */
294	static struct ichx_desc ich7_desc = {
295	.ngpio = 50,
296	};
297
298	/* ICH9-based */
299	static struct ichx_desc ich9_desc = {
300	.ngpio = 61,
301	};
302
303	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
304	static struct ichx_desc ich10_cons_desc = {
305	.ngpio = 61,
306	};
307	static struct ichx_desc ich10_corp_desc = {
308	.ngpio = 72,
309	};
310
311	/* Intel 5 series, 6 series, 3400 series, and C200 series */
312	static struct ichx_desc intel5_desc = {
313	.ngpio = 76,
314	};
315
4f600ada JD	316	static int __devinit ichx_gpio_request_regions(struct resource *res_base,
	317	const char *name, u8 use_gpio)
	318	{
	319	int i;
	320
	321	if (!res_base \|\| !res_base->start \|\| !res_base->end)
	322	return -ENODEV;
	323
	324	for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
	325	if (!(use_gpio & (1 << i)))
	326	continue;
	327	if (!request_region(res_base->start + ichx_regs[0][i],
	328	ichx_reglen[i], name))
	329	goto request_err;
	330	}
	331	return 0;
	332
	333	request_err:
	334	/* Clean up: release already requested regions, if any */
	335	for (i--; i >= 0; i--) {
	336	if (!(use_gpio & (1 << i)))
	337	continue;
	338	release_region(res_base->start + ichx_regs[0][i],
	339	ichx_reglen[i]);
	340	}
	341	return -EBUSY;
	342	}
	343
	344	static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
	345	{
	346	int i;
	347
	348	for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
	349	if (!(use_gpio & (1 << i)))
	350	continue;
	351	release_region(res_base->start + ichx_regs[0][i],
	352	ichx_reglen[i]);
	353	}
	354	}
	355
6ed9f9c4 PT	356	static int __devinit ichx_gpio_probe(struct platform_device *pdev)
	357	{
	358	struct resource res_base, res_pm;
	359	int err;
	360	struct lpc_ich_info *ich_info = pdev->dev.platform_data;
	361
	362	if (!ich_info)
	363	return -ENODEV;
	364
	365	ichx_priv.dev = pdev;
	366
	367	switch (ich_info->gpio_version) {
	368	case ICH_I3100_GPIO:
	369	ichx_priv.desc = &i3100_desc;
	370	break;
	371	case ICH_V5_GPIO:
	372	ichx_priv.desc = &intel5_desc;
	373	break;
	374	case ICH_V6_GPIO:
	375	ichx_priv.desc = &ich6_desc;
	376	break;
	377	case ICH_V7_GPIO:
	378	ichx_priv.desc = &ich7_desc;
	379	break;
	380	case ICH_V9_GPIO:
	381	ichx_priv.desc = &ich9_desc;
	382	break;
	383	case ICH_V10CORP_GPIO:
	384	ichx_priv.desc = &ich10_corp_desc;
	385	break;
	386	case ICH_V10CONS_GPIO:
	387	ichx_priv.desc = &ich10_cons_desc;
	388	break;
	389	default:
	390	return -ENODEV;
	391	}
	392
	393	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
4f600ada JD	394	ichx_priv.use_gpio = ich_info->use_gpio;
	395	err = ichx_gpio_request_regions(res_base, pdev->name,
	396	ichx_priv.use_gpio);
	397	if (err)
	398	return err;
6ed9f9c4 PT	399
	400	ichx_priv.gpio_base = res_base;
	401
	402	/*
	403	* If necessary, determine the I/O address of ACPI/power management
	404	* registers which are needed to read the the GPE0 register for GPI pins
	405	* 0 - 15 on some chipsets.
	406	*/
	407	if (!ichx_priv.desc->uses_gpe0)
	408	goto init;
	409
	410	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	411	if (!res_pm) {
	412	pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
	413	goto init;
	414	}
	415
	416	if (!request_region(res_pm->start, resource_size(res_pm),
	417	pdev->name)) {
	418	pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
	419	goto init;
	420	}
	421
	422	ichx_priv.pm_base = res_pm;
	423
	424	init:
	425	ichx_gpiolib_setup(&ichx_priv.chip);
	426	err = gpiochip_add(&ichx_priv.chip);
	427	if (err) {
	428	pr_err("Failed to register GPIOs\n");
	429	goto add_err;
	430	}
	431
	432	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	433	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
	434
	435	return 0;
	436
	437	add_err:
4f600ada	438	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
6ed9f9c4 PT	439	if (ichx_priv.pm_base)
	440	release_region(ichx_priv.pm_base->start,
	441	resource_size(ichx_priv.pm_base));
	442	return err;
	443	}
	444
	445	static int __devexit ichx_gpio_remove(struct platform_device *pdev)
	446	{
	447	int err;
	448
	449	err = gpiochip_remove(&ichx_priv.chip);
	450	if (err) {
	451	dev_err(&pdev->dev, "%s failed, %d\n",
	452	"gpiochip_remove()", err);
	453	return err;
	454	}
	455
4f600ada	456	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
6ed9f9c4 PT	457	if (ichx_priv.pm_base)
	458	release_region(ichx_priv.pm_base->start,
	459	resource_size(ichx_priv.pm_base));
	460
	461	return 0;
	462	}
	463
	464	static struct platform_driver ichx_gpio_driver = {
	465	.driver = {
	466	.owner = THIS_MODULE,
	467	.name = DRV_NAME,
	468	},
	469	.probe = ichx_gpio_probe,
8283c4ff	470	.remove = ichx_gpio_remove,
6ed9f9c4 PT	471	};
	472
	473	module_platform_driver(ichx_gpio_driver);
	474
	475	MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
	476	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
	477	MODULE_LICENSE("GPL");
	478	MODULE_ALIAS("platform:"DRV_NAME);