[linux-2.6-block.git] / drivers / gpio / gpio-ich.c

/*
 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/bitops.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
	GPO_BLINK
};

static const u8 ichx_regs[4][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
	{0x18, 0x18, 0x18},	/* BLINK offset */
};

static const u8 ichx_reglen[3] = {
	0x30, 0x10, 0x10,
};

static const u8 avoton_regs[4][3] = {
	{0x00, 0x80, 0x00},
	{0x04, 0x84, 0x00},
	{0x08, 0x88, 0x00},
};

static const u8 avoton_reglen[3] = {
	0x10, 0x10, 0x00,
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* chipset registers */
	const u8 (*regs)[3];
	const u8 *reglen;

	/* GPO_BLINK is available on this chipset */
	bool have_blink;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned offset);
	int (*get)(struct gpio_chip *chip, unsigned offset);

	/*
	 * Some chipsets don't let reading output values on GPIO_LVL register
	 * this option allows driver caching written output values
	 */
	bool use_outlvl_cache;
};

static struct {
	spinlock_t lock;
	struct platform_device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Mangagment IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
	u8 use_gpio;		/* Which GPIO groups are usable */
	int outlvl_cache[3];	/* cached output values */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
			   "which is the default.");

static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;
	int ret = 0;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr];
	else
		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
				 ichx_priv.gpio_base);

	if (val)
		data |= BIT(bit);
	else
		data &= ~BIT(bit);
	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);
	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		ichx_priv.outlvl_cache[reg_nr] = data;

	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			ichx_priv.gpio_base);
	if (verify && data != tmp)
		ret = -EPERM;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return ret;
}

static int ichx_read_bit(int reg, unsigned nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr] | data;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return !!(data & BIT(bit));
}

static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
{
	return !!(ichx_priv.use_gpio & BIT(nr / 32));
}

static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
{
	return ichx_read_bit(GPIO_IO_SEL, nr);
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
					int val)
{
	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
	if (nr < 32 && ichx_priv.desc->have_blink)
		ichx_write_bit(GPO_BLINK, nr, 0, 0);

	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	unsigned long flags;
	u32 data;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return !!((data >> 16) & BIT(nr));
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
		return 0;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->parent = &ichx_priv.dev->dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->get_direction = ichx_gpio_get_direction;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = false;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Avoton */
static struct ichx_desc avoton_desc = {
	/* Avoton has only 59 GPIOs, but we assume the first set of register
	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
	 */
	.ngpio = 60,
	.regs = avoton_regs,
	.reglen = avoton_reglen,
	.use_outlvl_cache = true,
};

static int ichx_gpio_request_regions(struct device *dev,
	struct resource *res_base, const char *name, u8 use_gpio)
{
	int i;

	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & BIT(i)))
			continue;
		if (!devm_request_region(dev,
				res_base->start + ichx_priv.desc->regs[0][i],
				ichx_priv.desc->reglen[i], name))
			return -EBUSY;
	}
	return 0;
}

static int ichx_gpio_probe(struct platform_device *pdev)
{
	struct resource *res_base, *res_pm;
	int err;
	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);

	if (!ich_info)
		return -ENODEV;

	ichx_priv.dev = pdev;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	case AVOTON_GPIO:
		ichx_priv.desc = &avoton_desc;
		break;
	default:
		return -ENODEV;
	}

	spin_lock_init(&ichx_priv.lock);
	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	ichx_priv.use_gpio = ich_info->use_gpio;
	err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
					ichx_priv.use_gpio);
	if (err)
		return err;

	ichx_priv.gpio_base = res_base;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!devm_request_region(&pdev->dev, res_pm->start,
			resource_size(res_pm), pdev->name)) {
		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = gpiochip_add_data(&ichx_priv.chip, NULL);
	if (err) {
		pr_err("Failed to register GPIOs\n");
		return err;
	}

	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);

	return 0;
}

static int ichx_gpio_remove(struct platform_device *pdev)
{
	gpiochip_remove(&ichx_priv.chip);

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
	.remove		= ichx_gpio_remove,
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
6ed9f9c4	1	/*
3b923189	2	* Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
6ed9f9c4 PT	3	*
	4	* Copyright (C) 2010 Extreme Engineering Solutions.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
8a06b08e	23	#include <linux/ioport.h>
6ed9f9c4 PT	24	#include <linux/module.h>
6ed9f9c4 PT	25	#include <linux/pci.h>
3f4290d4	26	#include <linux/gpio/driver.h>
6ed9f9c4 PT	27	#include <linux/platform_device.h>
6ed9f9c4 PT	28	#include <linux/mfd/lpc_ich.h>
7a8fd1f5	29	#include <linux/bitops.h>
6ed9f9c4 PT	30
	31	#define DRV_NAME "gpio_ich"
	32
	33	/*
	34	* GPIO register offsets in GPIO I/O space.
	35	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	36	* LVLx registers. Logic in the read/write functions takes a register and
	37	* an absolute bit number and determines the proper register offset and bit
	38	* number in that register. For example, to read the value of GPIO bit 50
	39	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	40	* bit 18 (50%32).
	41	*/
	42	enum GPIO_REG {
	43	GPIO_USE_SEL = 0,
	44	GPIO_IO_SEL,
	45	GPIO_LVL,
7f6569f5	46	GPO_BLINK
6ed9f9c4 PT	47	};
6ed9f9c4 PT	48
7f6569f5	49	static const u8 ichx_regs[4][3] = {
6ed9f9c4 PT	50	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	51	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	52	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
7f6569f5	53	{0x18, 0x18, 0x18}, /* BLINK offset */
6ed9f9c4 PT	54	};
6ed9f9c4 PT	55
4f600ada JD	56	static const u8 ichx_reglen[3] = {
	57	0x30, 0x10, 0x10,
	58	};
	59
3b923189 VD	60	static const u8 avoton_regs[4][3] = {
	61	{0x00, 0x80, 0x00},
	62	{0x04, 0x84, 0x00},
	63	{0x08, 0x88, 0x00},
	64	};
	65
	66	static const u8 avoton_reglen[3] = {
	67	0x10, 0x10, 0x00,
	68	};
	69
6ed9f9c4 PT	70	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	71	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	72
	73	struct ichx_desc {
	74	/* Max GPIO pins the chipset can have */
	75	uint ngpio;
	76
bb62a35b VD	77	/* chipset registers */
	78	const u8 (*regs)[3];
	79	const u8 *reglen;
	80
ba7f74fe VD	81	/* GPO_BLINK is available on this chipset */
	82	bool have_blink;
	83
6ed9f9c4 PT	84	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	85	bool uses_gpe0;
	86
	87	/* USE_SEL is bogus on some chipsets, eg 3100 */
	88	u32 use_sel_ignore[3];
	89
	90	/* Some chipsets have quirks, let these use their own request/get */
	91	int (request)(struct gpio_chip chip, unsigned offset);
	92	int (get)(struct gpio_chip chip, unsigned offset);
e6540f33 VD	93
	94	/*
	95	* Some chipsets don't let reading output values on GPIO_LVL register
	96	* this option allows driver caching written output values
	97	*/
	98	bool use_outlvl_cache;
6ed9f9c4 PT	99	};
	100
	101	static struct {
	102	spinlock_t lock;
	103	struct platform_device *dev;
	104	struct gpio_chip chip;
	105	struct resource gpio_base; / GPIO IO base */
	106	struct resource pm_base; / Power Mangagment IO base */
	107	struct ichx_desc desc; / Pointer to chipset-specific description */
	108	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
4f600ada	109	u8 use_gpio; /* Which GPIO groups are usable */
e6540f33	110	int outlvl_cache[3]; /* cached output values */
6ed9f9c4 PT	111	} ichx_priv;
	112
	113	static int modparam_gpiobase = -1; /* dynamic */
	114	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
	115	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
	116	"which is the default.");
	117
	118	static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
	119	{
	120	unsigned long flags;
	121	u32 data, tmp;
	122	int reg_nr = nr / 32;
	123	int bit = nr & 0x1f;
	124	int ret = 0;
	125
	126	spin_lock_irqsave(&ichx_priv.lock, flags);
	127
e6540f33 VD	128	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	129	data = ichx_priv.outlvl_cache[reg_nr];
	130	else
	131	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
	132	ichx_priv.gpio_base);
	133
6ed9f9c4	134	if (val)
7a8fd1f5	135	data \|= BIT(bit);
6ed9f9c4	136	else
7a8fd1f5	137	data &= ~BIT(bit);
bb62a35b VD	138	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	139	ichx_priv.gpio_base);
e6540f33 VD	140	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	141	ichx_priv.outlvl_cache[reg_nr] = data;
	142
bb62a35b VD	143	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	144	ichx_priv.gpio_base);
6ed9f9c4 PT	145	if (verify && data != tmp)
	146	ret = -EPERM;
	147
	148	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	149
	150	return ret;
	151	}
	152
	153	static int ichx_read_bit(int reg, unsigned nr)
	154	{
	155	unsigned long flags;
	156	u32 data;
	157	int reg_nr = nr / 32;
	158	int bit = nr & 0x1f;
	159
	160	spin_lock_irqsave(&ichx_priv.lock, flags);
	161
bb62a35b VD	162	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	163	ichx_priv.gpio_base);
6ed9f9c4	164
e6540f33 VD	165	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	166	data = ichx_priv.outlvl_cache[reg_nr] \| data;
	167
6ed9f9c4 PT	168	spin_unlock_irqrestore(&ichx_priv.lock, flags);
6ed9f9c4 PT	169
7a8fd1f5	170	return !!(data & BIT(bit));
6ed9f9c4 PT	171	}
6ed9f9c4 PT	172
e97f9b52	173	static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
4f600ada	174	{
7a8fd1f5	175	return !!(ichx_priv.use_gpio & BIT(nr / 32));
4f600ada JD	176	}
4f600ada JD	177
62e08f25 AS	178	static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
62e08f25 AS	179	{
3f4290d4	180	return ichx_read_bit(GPIO_IO_SEL, nr);
62e08f25 AS	181	}
62e08f25 AS	182
6ed9f9c4 PT	183	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	184	{
	185	/*
	186	* Try setting pin as an input and verify it worked since many pins
	187	* are output-only.
	188	*/
	189	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
	190	return -EINVAL;
	191
	192	return 0;
	193	}
	194
	195	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	196	int val)
	197	{
7f6569f5	198	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
ba7f74fe	199	if (nr < 32 && ichx_priv.desc->have_blink)
7f6569f5 VD	200	ichx_write_bit(GPO_BLINK, nr, 0, 0);
7f6569f5 VD	201
6ed9f9c4 PT	202	/* Set GPIO output value. */
	203	ichx_write_bit(GPIO_LVL, nr, val, 0);
	204
	205	/*
	206	* Try setting pin as an output and verify it worked since many pins
	207	* are input-only.
	208	*/
	209	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
	210	return -EINVAL;
	211
	212	return 0;
	213	}
	214
	215	static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
	216	{
	217	return ichx_read_bit(GPIO_LVL, nr);
	218	}
	219
	220	static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
	221	{
	222	unsigned long flags;
	223	u32 data;
	224
	225	/*
	226	* GPI 0 - 15 need to be read from the power management registers on
	227	* a ICH6/3100 bridge.
	228	*/
	229	if (nr < 16) {
	230	if (!ichx_priv.pm_base)
	231	return -ENXIO;
	232
	233	spin_lock_irqsave(&ichx_priv.lock, flags);
	234
	235	/* GPI 0 - 15 are latched, write 1 to clear*/
7a8fd1f5	236	ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
6ed9f9c4 PT	237	data = ICHX_READ(0, ichx_priv.pm_base);
	238
	239	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	240
7a8fd1f5	241	return !!((data >> 16) & BIT(nr));
6ed9f9c4 PT	242	} else {
	243	return ichx_gpio_get(chip, nr);
	244	}
	245	}
	246
	247	static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
	248	{
25f27db4 JD	249	if (!ichx_gpio_check_available(chip, nr))
	250	return -ENXIO;
	251
6ed9f9c4 PT	252	/*
	253	* Note we assume the BIOS properly set a bridge's USE value. Some
	254	* chips (eg Intel 3100) have bogus USE values though, so first see if
	255	* the chipset's USE value can be trusted for this specific bit.
	256	* If it can't be trusted, assume that the pin can be used as a GPIO.
	257	*/
7a8fd1f5	258	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
2ab3a749	259	return 0;
6ed9f9c4 PT	260
	261	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
	262	}
	263
	264	static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
	265	{
	266	/*
	267	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	268	* bridge as they are controlled by USE register bits 0 and 1. See
	269	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	270	* additional info.
	271	*/
	272	if (nr == 16 \|\| nr == 17)
	273	nr -= 16;
	274
	275	return ichx_gpio_request(chip, nr);
	276	}
	277
	278	static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
	279	{
	280	ichx_write_bit(GPIO_LVL, nr, val, 0);
	281	}
	282
3836309d	283	static void ichx_gpiolib_setup(struct gpio_chip *chip)
6ed9f9c4 PT	284	{
	285	chip->owner = THIS_MODULE;
	286	chip->label = DRV_NAME;
58383c78	287	chip->parent = &ichx_priv.dev->dev;
6ed9f9c4 PT	288
	289	/* Allow chip-specific overrides of request()/get() */
	290	chip->request = ichx_priv.desc->request ?
	291	ichx_priv.desc->request : ichx_gpio_request;
	292	chip->get = ichx_priv.desc->get ?
	293	ichx_priv.desc->get : ichx_gpio_get;
	294
	295	chip->set = ichx_gpio_set;
62e08f25	296	chip->get_direction = ichx_gpio_get_direction;
6ed9f9c4 PT	297	chip->direction_input = ichx_gpio_direction_input;
	298	chip->direction_output = ichx_gpio_direction_output;
	299	chip->base = modparam_gpiobase;
	300	chip->ngpio = ichx_priv.desc->ngpio;
9fb1f39e	301	chip->can_sleep = false;
6ed9f9c4 PT	302	chip->dbg_show = NULL;
	303	}
	304
	305	/* ICH6-based, 631xesb-based */
	306	static struct ichx_desc ich6_desc = {
	307	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	308	.request = ich6_gpio_request,
	309	.get = ich6_gpio_get,
	310
	311	/* GPIO 0-15 are read in the GPE0_STS PM register */
	312	.uses_gpe0 = true,
	313
	314	.ngpio = 50,
ba7f74fe	315	.have_blink = true,
a7008ee1 VD	316	.regs = ichx_regs,
a7008ee1 VD	317	.reglen = ichx_reglen,
6ed9f9c4 PT	318	};
	319
	320	/* Intel 3100 */
	321	static struct ichx_desc i3100_desc = {
	322	/*
	323	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	324	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
	325	* Datasheet for more info.
	326	*/
	327	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
	328
	329	/* The 3100 needs fixups for GPIO 0 - 17 */
	330	.request = ich6_gpio_request,
	331	.get = ich6_gpio_get,
	332
	333	/* GPIO 0-15 are read in the GPE0_STS PM register */
	334	.uses_gpe0 = true,
	335
	336	.ngpio = 50,
a7008ee1 VD	337	.regs = ichx_regs,
a7008ee1 VD	338	.reglen = ichx_reglen,
6ed9f9c4 PT	339	};
	340
	341	/* ICH7 and ICH8-based */
	342	static struct ichx_desc ich7_desc = {
	343	.ngpio = 50,
ba7f74fe	344	.have_blink = true,
bb62a35b VD	345	.regs = ichx_regs,
bb62a35b VD	346	.reglen = ichx_reglen,
6ed9f9c4 PT	347	};
	348
	349	/* ICH9-based */
	350	static struct ichx_desc ich9_desc = {
	351	.ngpio = 61,
ba7f74fe	352	.have_blink = true,
bb62a35b VD	353	.regs = ichx_regs,
bb62a35b VD	354	.reglen = ichx_reglen,
6ed9f9c4 PT	355	};
	356
	357	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
	358	static struct ichx_desc ich10_cons_desc = {
	359	.ngpio = 61,
ba7f74fe	360	.have_blink = true,
bb62a35b VD	361	.regs = ichx_regs,
bb62a35b VD	362	.reglen = ichx_reglen,
6ed9f9c4 PT	363	};
	364	static struct ichx_desc ich10_corp_desc = {
	365	.ngpio = 72,
ba7f74fe	366	.have_blink = true,
bb62a35b VD	367	.regs = ichx_regs,
bb62a35b VD	368	.reglen = ichx_reglen,
6ed9f9c4 PT	369	};
	370
	371	/* Intel 5 series, 6 series, 3400 series, and C200 series */
	372	static struct ichx_desc intel5_desc = {
	373	.ngpio = 76,
bb62a35b VD	374	.regs = ichx_regs,
bb62a35b VD	375	.reglen = ichx_reglen,
6ed9f9c4 PT	376	};
6ed9f9c4 PT	377
3b923189 VD	378	/* Avoton */
	379	static struct ichx_desc avoton_desc = {
	380	/* Avoton has only 59 GPIOs, but we assume the first set of register
	381	* (Core) has 32 instead of 31 to keep gpio-ich compliance
	382	*/
	383	.ngpio = 60,
	384	.regs = avoton_regs,
	385	.reglen = avoton_reglen,
	386	.use_outlvl_cache = true,
	387	};
	388
8a06b08e WBG	389	static int ichx_gpio_request_regions(struct device *dev,
8a06b08e WBG	390	struct resource res_base, const char name, u8 use_gpio)
4f600ada JD	391	{
	392	int i;
	393
	394	if (!res_base \|\| !res_base->start \|\| !res_base->end)
	395	return -ENODEV;
	396
bb62a35b	397	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
7a8fd1f5	398	if (!(use_gpio & BIT(i)))
4f600ada	399	continue;
8a06b08e	400	if (!devm_request_region(dev,
bb62a35b VD	401	res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	402	ichx_priv.desc->reglen[i], name))
8a06b08e	403	return -EBUSY;
4f600ada JD	404	}
4f600ada JD	405	return 0;
4f600ada JD	406	}
4f600ada JD	407
3836309d	408	static int ichx_gpio_probe(struct platform_device *pdev)
6ed9f9c4 PT	409	{
	410	struct resource res_base, res_pm;
	411	int err;
e56aee18	412	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
6ed9f9c4 PT	413
	414	if (!ich_info)
	415	return -ENODEV;
	416
	417	ichx_priv.dev = pdev;
	418
	419	switch (ich_info->gpio_version) {
	420	case ICH_I3100_GPIO:
	421	ichx_priv.desc = &i3100_desc;
	422	break;
	423	case ICH_V5_GPIO:
	424	ichx_priv.desc = &intel5_desc;
	425	break;
	426	case ICH_V6_GPIO:
	427	ichx_priv.desc = &ich6_desc;
	428	break;
	429	case ICH_V7_GPIO:
	430	ichx_priv.desc = &ich7_desc;
	431	break;
	432	case ICH_V9_GPIO:
	433	ichx_priv.desc = &ich9_desc;
	434	break;
	435	case ICH_V10CORP_GPIO:
	436	ichx_priv.desc = &ich10_corp_desc;
	437	break;
	438	case ICH_V10CONS_GPIO:
	439	ichx_priv.desc = &ich10_cons_desc;
	440	break;
3b923189 VD	441	case AVOTON_GPIO:
	442	ichx_priv.desc = &avoton_desc;
	443	break;
6ed9f9c4 PT	444	default:
	445	return -ENODEV;
	446	}
	447
d39a948f	448	spin_lock_init(&ichx_priv.lock);
6ed9f9c4	449	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
4f600ada	450	ichx_priv.use_gpio = ich_info->use_gpio;
8a06b08e	451	err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
4f600ada JD	452	ichx_priv.use_gpio);
	453	if (err)
	454	return err;
6ed9f9c4 PT	455
	456	ichx_priv.gpio_base = res_base;
	457
	458	/*
	459	* If necessary, determine the I/O address of ACPI/power management
	460	* registers which are needed to read the the GPE0 register for GPI pins
	461	* 0 - 15 on some chipsets.
	462	*/
	463	if (!ichx_priv.desc->uses_gpe0)
	464	goto init;
	465
	466	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	467	if (!res_pm) {
	468	pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
	469	goto init;
	470	}
	471
8a06b08e WBG	472	if (!devm_request_region(&pdev->dev, res_pm->start,
8a06b08e WBG	473	resource_size(res_pm), pdev->name)) {
6ed9f9c4 PT	474	pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
	475	goto init;
	476	}
	477
	478	ichx_priv.pm_base = res_pm;
	479
	480	init:
	481	ichx_gpiolib_setup(&ichx_priv.chip);
4eab22e7	482	err = gpiochip_add_data(&ichx_priv.chip, NULL);
6ed9f9c4 PT	483	if (err) {
6ed9f9c4 PT	484	pr_err("Failed to register GPIOs\n");
8a06b08e	485	return err;
6ed9f9c4 PT	486	}
	487
	488	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	489	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
	490
	491	return 0;
6ed9f9c4 PT	492	}
6ed9f9c4 PT	493
206210ce	494	static int ichx_gpio_remove(struct platform_device *pdev)
6ed9f9c4	495	{
9f5132ae	496	gpiochip_remove(&ichx_priv.chip);
6ed9f9c4	497
6ed9f9c4 PT	498	return 0;
	499	}
	500
	501	static struct platform_driver ichx_gpio_driver = {
	502	.driver = {
6ed9f9c4 PT	503	.name = DRV_NAME,
	504	},
	505	.probe = ichx_gpio_probe,
8283c4ff	506	.remove = ichx_gpio_remove,
6ed9f9c4 PT	507	};
	508
	509	module_platform_driver(ichx_gpio_driver);
	510
	511	MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
	512	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
	513	MODULE_LICENSE("GPL");
	514	MODULE_ALIAS("platform:"DRV_NAME);