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7ed0cf0a | 1 | // SPDX-License-Identifier: GPL-2.0+ |
6ed9f9c4 | 2 | /* |
3b923189 | 3 | * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver |
6ed9f9c4 PT |
4 | * |
5 | * Copyright (C) 2010 Extreme Engineering Solutions. | |
6ed9f9c4 PT |
6 | */ |
7 | ||
6ed9f9c4 | 8 | |
488f270c AS |
9 | #include <linux/bitops.h> |
10 | #include <linux/gpio/driver.h> | |
8a06b08e | 11 | #include <linux/ioport.h> |
488f270c | 12 | #include <linux/mfd/lpc_ich.h> |
6ed9f9c4 PT |
13 | #include <linux/module.h> |
14 | #include <linux/pci.h> | |
6ed9f9c4 | 15 | #include <linux/platform_device.h> |
6ed9f9c4 PT |
16 | |
17 | #define DRV_NAME "gpio_ich" | |
18 | ||
19 | /* | |
20 | * GPIO register offsets in GPIO I/O space. | |
21 | * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and | |
22 | * LVLx registers. Logic in the read/write functions takes a register and | |
23 | * an absolute bit number and determines the proper register offset and bit | |
24 | * number in that register. For example, to read the value of GPIO bit 50 | |
25 | * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], | |
26 | * bit 18 (50%32). | |
27 | */ | |
28 | enum GPIO_REG { | |
29 | GPIO_USE_SEL = 0, | |
30 | GPIO_IO_SEL, | |
31 | GPIO_LVL, | |
7f6569f5 | 32 | GPO_BLINK |
6ed9f9c4 PT |
33 | }; |
34 | ||
7f6569f5 | 35 | static const u8 ichx_regs[4][3] = { |
6ed9f9c4 PT |
36 | {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ |
37 | {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ | |
38 | {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ | |
7f6569f5 | 39 | {0x18, 0x18, 0x18}, /* BLINK offset */ |
6ed9f9c4 PT |
40 | }; |
41 | ||
4f600ada JD |
42 | static const u8 ichx_reglen[3] = { |
43 | 0x30, 0x10, 0x10, | |
44 | }; | |
45 | ||
3b923189 VD |
46 | static const u8 avoton_regs[4][3] = { |
47 | {0x00, 0x80, 0x00}, | |
48 | {0x04, 0x84, 0x00}, | |
49 | {0x08, 0x88, 0x00}, | |
50 | }; | |
51 | ||
52 | static const u8 avoton_reglen[3] = { | |
53 | 0x10, 0x10, 0x00, | |
54 | }; | |
55 | ||
6ed9f9c4 PT |
56 | #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) |
57 | #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) | |
58 | ||
59 | struct ichx_desc { | |
60 | /* Max GPIO pins the chipset can have */ | |
61 | uint ngpio; | |
62 | ||
bb62a35b VD |
63 | /* chipset registers */ |
64 | const u8 (*regs)[3]; | |
65 | const u8 *reglen; | |
66 | ||
ba7f74fe VD |
67 | /* GPO_BLINK is available on this chipset */ |
68 | bool have_blink; | |
69 | ||
6ed9f9c4 PT |
70 | /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ |
71 | bool uses_gpe0; | |
72 | ||
73 | /* USE_SEL is bogus on some chipsets, eg 3100 */ | |
74 | u32 use_sel_ignore[3]; | |
75 | ||
76 | /* Some chipsets have quirks, let these use their own request/get */ | |
77 | int (*request)(struct gpio_chip *chip, unsigned offset); | |
78 | int (*get)(struct gpio_chip *chip, unsigned offset); | |
e6540f33 VD |
79 | |
80 | /* | |
81 | * Some chipsets don't let reading output values on GPIO_LVL register | |
82 | * this option allows driver caching written output values | |
83 | */ | |
84 | bool use_outlvl_cache; | |
6ed9f9c4 PT |
85 | }; |
86 | ||
87 | static struct { | |
88 | spinlock_t lock; | |
ff4709b4 | 89 | struct device *dev; |
6ed9f9c4 PT |
90 | struct gpio_chip chip; |
91 | struct resource *gpio_base; /* GPIO IO base */ | |
92 | struct resource *pm_base; /* Power Mangagment IO base */ | |
93 | struct ichx_desc *desc; /* Pointer to chipset-specific description */ | |
94 | u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ | |
4f600ada | 95 | u8 use_gpio; /* Which GPIO groups are usable */ |
e6540f33 | 96 | int outlvl_cache[3]; /* cached output values */ |
6ed9f9c4 PT |
97 | } ichx_priv; |
98 | ||
99 | static int modparam_gpiobase = -1; /* dynamic */ | |
100 | module_param_named(gpiobase, modparam_gpiobase, int, 0444); | |
5f6f2b9f | 101 | MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default."); |
6ed9f9c4 PT |
102 | |
103 | static int ichx_write_bit(int reg, unsigned nr, int val, int verify) | |
104 | { | |
105 | unsigned long flags; | |
106 | u32 data, tmp; | |
107 | int reg_nr = nr / 32; | |
108 | int bit = nr & 0x1f; | |
6ed9f9c4 PT |
109 | |
110 | spin_lock_irqsave(&ichx_priv.lock, flags); | |
111 | ||
e6540f33 VD |
112 | if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) |
113 | data = ichx_priv.outlvl_cache[reg_nr]; | |
114 | else | |
115 | data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], | |
116 | ichx_priv.gpio_base); | |
117 | ||
6ed9f9c4 | 118 | if (val) |
7a8fd1f5 | 119 | data |= BIT(bit); |
6ed9f9c4 | 120 | else |
7a8fd1f5 | 121 | data &= ~BIT(bit); |
bb62a35b VD |
122 | ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], |
123 | ichx_priv.gpio_base); | |
e6540f33 VD |
124 | if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) |
125 | ichx_priv.outlvl_cache[reg_nr] = data; | |
126 | ||
bb62a35b VD |
127 | tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], |
128 | ichx_priv.gpio_base); | |
6ed9f9c4 PT |
129 | |
130 | spin_unlock_irqrestore(&ichx_priv.lock, flags); | |
131 | ||
c5aaa316 | 132 | return (verify && data != tmp) ? -EPERM : 0; |
6ed9f9c4 PT |
133 | } |
134 | ||
135 | static int ichx_read_bit(int reg, unsigned nr) | |
136 | { | |
137 | unsigned long flags; | |
138 | u32 data; | |
139 | int reg_nr = nr / 32; | |
140 | int bit = nr & 0x1f; | |
141 | ||
142 | spin_lock_irqsave(&ichx_priv.lock, flags); | |
143 | ||
bb62a35b VD |
144 | data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], |
145 | ichx_priv.gpio_base); | |
6ed9f9c4 | 146 | |
e6540f33 VD |
147 | if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) |
148 | data = ichx_priv.outlvl_cache[reg_nr] | data; | |
149 | ||
6ed9f9c4 PT |
150 | spin_unlock_irqrestore(&ichx_priv.lock, flags); |
151 | ||
7a8fd1f5 | 152 | return !!(data & BIT(bit)); |
6ed9f9c4 PT |
153 | } |
154 | ||
e97f9b52 | 155 | static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) |
4f600ada | 156 | { |
7a8fd1f5 | 157 | return !!(ichx_priv.use_gpio & BIT(nr / 32)); |
4f600ada JD |
158 | } |
159 | ||
62e08f25 AS |
160 | static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) |
161 | { | |
3f4290d4 | 162 | return ichx_read_bit(GPIO_IO_SEL, nr); |
62e08f25 AS |
163 | } |
164 | ||
6ed9f9c4 PT |
165 | static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) |
166 | { | |
167 | /* | |
168 | * Try setting pin as an input and verify it worked since many pins | |
169 | * are output-only. | |
170 | */ | |
c5aaa316 | 171 | return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1); |
6ed9f9c4 PT |
172 | } |
173 | ||
174 | static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, | |
175 | int val) | |
176 | { | |
7f6569f5 | 177 | /* Disable blink hardware which is available for GPIOs from 0 to 31. */ |
ba7f74fe | 178 | if (nr < 32 && ichx_priv.desc->have_blink) |
7f6569f5 VD |
179 | ichx_write_bit(GPO_BLINK, nr, 0, 0); |
180 | ||
6ed9f9c4 PT |
181 | /* Set GPIO output value. */ |
182 | ichx_write_bit(GPIO_LVL, nr, val, 0); | |
183 | ||
184 | /* | |
185 | * Try setting pin as an output and verify it worked since many pins | |
186 | * are input-only. | |
187 | */ | |
c5aaa316 | 188 | return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1); |
6ed9f9c4 PT |
189 | } |
190 | ||
191 | static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) | |
192 | { | |
193 | return ichx_read_bit(GPIO_LVL, nr); | |
194 | } | |
195 | ||
196 | static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) | |
197 | { | |
198 | unsigned long flags; | |
199 | u32 data; | |
200 | ||
201 | /* | |
202 | * GPI 0 - 15 need to be read from the power management registers on | |
203 | * a ICH6/3100 bridge. | |
204 | */ | |
205 | if (nr < 16) { | |
206 | if (!ichx_priv.pm_base) | |
207 | return -ENXIO; | |
208 | ||
209 | spin_lock_irqsave(&ichx_priv.lock, flags); | |
210 | ||
211 | /* GPI 0 - 15 are latched, write 1 to clear*/ | |
7a8fd1f5 | 212 | ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); |
6ed9f9c4 PT |
213 | data = ICHX_READ(0, ichx_priv.pm_base); |
214 | ||
215 | spin_unlock_irqrestore(&ichx_priv.lock, flags); | |
216 | ||
7a8fd1f5 | 217 | return !!((data >> 16) & BIT(nr)); |
6ed9f9c4 PT |
218 | } else { |
219 | return ichx_gpio_get(chip, nr); | |
220 | } | |
221 | } | |
222 | ||
223 | static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) | |
224 | { | |
25f27db4 JD |
225 | if (!ichx_gpio_check_available(chip, nr)) |
226 | return -ENXIO; | |
227 | ||
6ed9f9c4 PT |
228 | /* |
229 | * Note we assume the BIOS properly set a bridge's USE value. Some | |
230 | * chips (eg Intel 3100) have bogus USE values though, so first see if | |
231 | * the chipset's USE value can be trusted for this specific bit. | |
232 | * If it can't be trusted, assume that the pin can be used as a GPIO. | |
233 | */ | |
7a8fd1f5 | 234 | if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) |
2ab3a749 | 235 | return 0; |
6ed9f9c4 PT |
236 | |
237 | return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; | |
238 | } | |
239 | ||
240 | static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) | |
241 | { | |
242 | /* | |
243 | * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 | |
244 | * bridge as they are controlled by USE register bits 0 and 1. See | |
245 | * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for | |
246 | * additional info. | |
247 | */ | |
248 | if (nr == 16 || nr == 17) | |
249 | nr -= 16; | |
250 | ||
251 | return ichx_gpio_request(chip, nr); | |
252 | } | |
253 | ||
254 | static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) | |
255 | { | |
256 | ichx_write_bit(GPIO_LVL, nr, val, 0); | |
257 | } | |
258 | ||
3836309d | 259 | static void ichx_gpiolib_setup(struct gpio_chip *chip) |
6ed9f9c4 PT |
260 | { |
261 | chip->owner = THIS_MODULE; | |
262 | chip->label = DRV_NAME; | |
ff4709b4 | 263 | chip->parent = ichx_priv.dev; |
6ed9f9c4 PT |
264 | |
265 | /* Allow chip-specific overrides of request()/get() */ | |
266 | chip->request = ichx_priv.desc->request ? | |
267 | ichx_priv.desc->request : ichx_gpio_request; | |
268 | chip->get = ichx_priv.desc->get ? | |
269 | ichx_priv.desc->get : ichx_gpio_get; | |
270 | ||
271 | chip->set = ichx_gpio_set; | |
62e08f25 | 272 | chip->get_direction = ichx_gpio_get_direction; |
6ed9f9c4 PT |
273 | chip->direction_input = ichx_gpio_direction_input; |
274 | chip->direction_output = ichx_gpio_direction_output; | |
275 | chip->base = modparam_gpiobase; | |
276 | chip->ngpio = ichx_priv.desc->ngpio; | |
9fb1f39e | 277 | chip->can_sleep = false; |
6ed9f9c4 PT |
278 | chip->dbg_show = NULL; |
279 | } | |
280 | ||
281 | /* ICH6-based, 631xesb-based */ | |
282 | static struct ichx_desc ich6_desc = { | |
283 | /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ | |
284 | .request = ich6_gpio_request, | |
285 | .get = ich6_gpio_get, | |
286 | ||
287 | /* GPIO 0-15 are read in the GPE0_STS PM register */ | |
288 | .uses_gpe0 = true, | |
289 | ||
290 | .ngpio = 50, | |
ba7f74fe | 291 | .have_blink = true, |
a7008ee1 VD |
292 | .regs = ichx_regs, |
293 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
294 | }; |
295 | ||
296 | /* Intel 3100 */ | |
297 | static struct ichx_desc i3100_desc = { | |
298 | /* | |
299 | * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on | |
300 | * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 | |
301 | * Datasheet for more info. | |
302 | */ | |
303 | .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, | |
304 | ||
305 | /* The 3100 needs fixups for GPIO 0 - 17 */ | |
306 | .request = ich6_gpio_request, | |
307 | .get = ich6_gpio_get, | |
308 | ||
309 | /* GPIO 0-15 are read in the GPE0_STS PM register */ | |
310 | .uses_gpe0 = true, | |
311 | ||
312 | .ngpio = 50, | |
a7008ee1 VD |
313 | .regs = ichx_regs, |
314 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
315 | }; |
316 | ||
317 | /* ICH7 and ICH8-based */ | |
318 | static struct ichx_desc ich7_desc = { | |
319 | .ngpio = 50, | |
ba7f74fe | 320 | .have_blink = true, |
bb62a35b VD |
321 | .regs = ichx_regs, |
322 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
323 | }; |
324 | ||
325 | /* ICH9-based */ | |
326 | static struct ichx_desc ich9_desc = { | |
327 | .ngpio = 61, | |
ba7f74fe | 328 | .have_blink = true, |
bb62a35b VD |
329 | .regs = ichx_regs, |
330 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
331 | }; |
332 | ||
333 | /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ | |
334 | static struct ichx_desc ich10_cons_desc = { | |
335 | .ngpio = 61, | |
ba7f74fe | 336 | .have_blink = true, |
bb62a35b VD |
337 | .regs = ichx_regs, |
338 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
339 | }; |
340 | static struct ichx_desc ich10_corp_desc = { | |
341 | .ngpio = 72, | |
ba7f74fe | 342 | .have_blink = true, |
bb62a35b VD |
343 | .regs = ichx_regs, |
344 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
345 | }; |
346 | ||
347 | /* Intel 5 series, 6 series, 3400 series, and C200 series */ | |
348 | static struct ichx_desc intel5_desc = { | |
349 | .ngpio = 76, | |
bb62a35b VD |
350 | .regs = ichx_regs, |
351 | .reglen = ichx_reglen, | |
6ed9f9c4 PT |
352 | }; |
353 | ||
3b923189 VD |
354 | /* Avoton */ |
355 | static struct ichx_desc avoton_desc = { | |
356 | /* Avoton has only 59 GPIOs, but we assume the first set of register | |
357 | * (Core) has 32 instead of 31 to keep gpio-ich compliance | |
358 | */ | |
359 | .ngpio = 60, | |
360 | .regs = avoton_regs, | |
361 | .reglen = avoton_reglen, | |
362 | .use_outlvl_cache = true, | |
363 | }; | |
364 | ||
8a06b08e WBG |
365 | static int ichx_gpio_request_regions(struct device *dev, |
366 | struct resource *res_base, const char *name, u8 use_gpio) | |
4f600ada JD |
367 | { |
368 | int i; | |
369 | ||
370 | if (!res_base || !res_base->start || !res_base->end) | |
371 | return -ENODEV; | |
372 | ||
bb62a35b | 373 | for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { |
7a8fd1f5 | 374 | if (!(use_gpio & BIT(i))) |
4f600ada | 375 | continue; |
8a06b08e | 376 | if (!devm_request_region(dev, |
bb62a35b VD |
377 | res_base->start + ichx_priv.desc->regs[0][i], |
378 | ichx_priv.desc->reglen[i], name)) | |
8a06b08e | 379 | return -EBUSY; |
4f600ada JD |
380 | } |
381 | return 0; | |
4f600ada JD |
382 | } |
383 | ||
3836309d | 384 | static int ichx_gpio_probe(struct platform_device *pdev) |
6ed9f9c4 | 385 | { |
ff4709b4 AS |
386 | struct device *dev = &pdev->dev; |
387 | struct lpc_ich_info *ich_info = dev_get_platdata(dev); | |
6ed9f9c4 PT |
388 | struct resource *res_base, *res_pm; |
389 | int err; | |
6ed9f9c4 PT |
390 | |
391 | if (!ich_info) | |
392 | return -ENODEV; | |
393 | ||
6ed9f9c4 PT |
394 | switch (ich_info->gpio_version) { |
395 | case ICH_I3100_GPIO: | |
396 | ichx_priv.desc = &i3100_desc; | |
397 | break; | |
398 | case ICH_V5_GPIO: | |
399 | ichx_priv.desc = &intel5_desc; | |
400 | break; | |
401 | case ICH_V6_GPIO: | |
402 | ichx_priv.desc = &ich6_desc; | |
403 | break; | |
404 | case ICH_V7_GPIO: | |
405 | ichx_priv.desc = &ich7_desc; | |
406 | break; | |
407 | case ICH_V9_GPIO: | |
408 | ichx_priv.desc = &ich9_desc; | |
409 | break; | |
410 | case ICH_V10CORP_GPIO: | |
411 | ichx_priv.desc = &ich10_corp_desc; | |
412 | break; | |
413 | case ICH_V10CONS_GPIO: | |
414 | ichx_priv.desc = &ich10_cons_desc; | |
415 | break; | |
3b923189 VD |
416 | case AVOTON_GPIO: |
417 | ichx_priv.desc = &avoton_desc; | |
418 | break; | |
6ed9f9c4 PT |
419 | default: |
420 | return -ENODEV; | |
421 | } | |
422 | ||
ff4709b4 | 423 | ichx_priv.dev = dev; |
d39a948f | 424 | spin_lock_init(&ichx_priv.lock); |
ff4709b4 | 425 | |
6ed9f9c4 | 426 | res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); |
ff4709b4 AS |
427 | err = ichx_gpio_request_regions(dev, res_base, pdev->name, |
428 | ich_info->use_gpio); | |
4f600ada JD |
429 | if (err) |
430 | return err; | |
6ed9f9c4 PT |
431 | |
432 | ichx_priv.gpio_base = res_base; | |
ff4709b4 | 433 | ichx_priv.use_gpio = ich_info->use_gpio; |
6ed9f9c4 PT |
434 | |
435 | /* | |
436 | * If necessary, determine the I/O address of ACPI/power management | |
5f6f2b9f | 437 | * registers which are needed to read the GPE0 register for GPI pins |
6ed9f9c4 PT |
438 | * 0 - 15 on some chipsets. |
439 | */ | |
440 | if (!ichx_priv.desc->uses_gpe0) | |
441 | goto init; | |
442 | ||
443 | res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); | |
444 | if (!res_pm) { | |
c086bea5 | 445 | dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); |
6ed9f9c4 PT |
446 | goto init; |
447 | } | |
448 | ||
ff4709b4 AS |
449 | if (!devm_request_region(dev, res_pm->start, resource_size(res_pm), |
450 | pdev->name)) { | |
c086bea5 | 451 | dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n"); |
6ed9f9c4 PT |
452 | goto init; |
453 | } | |
454 | ||
455 | ichx_priv.pm_base = res_pm; | |
456 | ||
457 | init: | |
458 | ichx_gpiolib_setup(&ichx_priv.chip); | |
4eab22e7 | 459 | err = gpiochip_add_data(&ichx_priv.chip, NULL); |
6ed9f9c4 | 460 | if (err) { |
c086bea5 | 461 | dev_err(dev, "Failed to register GPIOs\n"); |
8a06b08e | 462 | return err; |
6ed9f9c4 PT |
463 | } |
464 | ||
c086bea5 AS |
465 | dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base, |
466 | ichx_priv.chip.base + ichx_priv.chip.ngpio - 1); | |
6ed9f9c4 PT |
467 | |
468 | return 0; | |
6ed9f9c4 PT |
469 | } |
470 | ||
206210ce | 471 | static int ichx_gpio_remove(struct platform_device *pdev) |
6ed9f9c4 | 472 | { |
9f5132ae | 473 | gpiochip_remove(&ichx_priv.chip); |
6ed9f9c4 | 474 | |
6ed9f9c4 PT |
475 | return 0; |
476 | } | |
477 | ||
478 | static struct platform_driver ichx_gpio_driver = { | |
479 | .driver = { | |
6ed9f9c4 PT |
480 | .name = DRV_NAME, |
481 | }, | |
482 | .probe = ichx_gpio_probe, | |
8283c4ff | 483 | .remove = ichx_gpio_remove, |
6ed9f9c4 PT |
484 | }; |
485 | ||
486 | module_platform_driver(ichx_gpio_driver); | |
487 | ||
488 | MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); | |
489 | MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); | |
490 | MODULE_LICENSE("GPL"); | |
491 | MODULE_ALIAS("platform:"DRV_NAME); |