[linux-2.6-block.git] / drivers / gpio / gpio-htc-egpio.c

/*
 * Support for the GPIO/IRQ expander chips present on several HTC phones.
 * These are implemented in CPLD chips present on the board.
 *
 * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
 *
 * This file may be distributed under the terms of the GNU GPL license.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_data/gpio-htc-egpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/gpio/driver.h>

struct egpio_chip {
	int              reg_start;
	int              cached_values;
	unsigned long    is_out;
	struct device    *dev;
	struct gpio_chip chip;
};

struct egpio_info {
	spinlock_t        lock;

	/* iomem info */
	void __iomem      *base_addr;
	int               bus_shift;	/* byte shift */
	int               reg_shift;	/* bit shift */
	int               reg_mask;

	/* irq info */
	int               ack_register;
	int               ack_write;
	u16               irqs_enabled;
	uint              irq_start;
	int               nirqs;
	uint              chained_irq;

	/* egpio info */
	struct egpio_chip *chip;
	int               nchips;
};

static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
{
	writew(value, ei->base_addr + (reg << ei->bus_shift));
}

static inline u16 egpio_readw(struct egpio_info *ei, int reg)
{
	return readw(ei->base_addr + (reg << ei->bus_shift));
}

/*
 * IRQs
 */

static inline void ack_irqs(struct egpio_info *ei)
{
	egpio_writew(ei->ack_write, ei, ei->ack_register);
	pr_debug("EGPIO ack - write %x to base+%x\n",
			ei->ack_write, ei->ack_register << ei->bus_shift);
}

static void egpio_ack(struct irq_data *data)
{
}

/* There does not appear to be a way to proactively mask interrupts
 * on the egpio chip itself.  So, we simply ignore interrupts that
 * aren't desired. */
static void egpio_mask(struct irq_data *data)
{
	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
	pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
}

static void egpio_unmask(struct irq_data *data)
{
	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
	pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
}

static struct irq_chip egpio_muxed_chip = {
	.name		= "htc-egpio",
	.irq_ack	= egpio_ack,
	.irq_mask	= egpio_mask,
	.irq_unmask	= egpio_unmask,
};

static void egpio_handler(struct irq_desc *desc)
{
	struct egpio_info *ei = irq_desc_get_handler_data(desc);
	int irqpin;

	/* Read current pins. */
	unsigned long readval = egpio_readw(ei, ei->ack_register);
	pr_debug("IRQ reg: %x\n", (unsigned int)readval);
	/* Ack/unmask interrupts. */
	ack_irqs(ei);
	/* Process all set pins. */
	readval &= ei->irqs_enabled;
	for_each_set_bit(irqpin, &readval, ei->nirqs) {
		/* Run irq handler */
		pr_debug("got IRQ %d\n", irqpin);
		generic_handle_irq(ei->irq_start + irqpin);
	}
}

int htc_egpio_get_wakeup_irq(struct device *dev)
{
	struct egpio_info *ei = dev_get_drvdata(dev);

	/* Read current pins. */
	u16 readval = egpio_readw(ei, ei->ack_register);
	/* Ack/unmask interrupts. */
	ack_irqs(ei);
	/* Return first set pin. */
	readval &= ei->irqs_enabled;
	return ei->irq_start + ffs(readval) - 1;
}
EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);

static inline int egpio_pos(struct egpio_info *ei, int bit)
{
	return bit >> ei->reg_shift;
}

static inline int egpio_bit(struct egpio_info *ei, int bit)
{
	return 1 << (bit & ((1 << ei->reg_shift)-1));
}

/*
 * Input pins
 */

static int egpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct egpio_chip *egpio;
	struct egpio_info *ei;
	unsigned           bit;
	int                reg;
	int                value;

	pr_debug("egpio_get_value(%d)\n", chip->base + offset);

	egpio = gpiochip_get_data(chip);
	ei    = dev_get_drvdata(egpio->dev);
	bit   = egpio_bit(ei, offset);
	reg   = egpio->reg_start + egpio_pos(ei, offset);

	if (test_bit(offset, &egpio->is_out)) {
		return !!(egpio->cached_values & (1 << offset));
	} else {
		value = egpio_readw(ei, reg);
		pr_debug("readw(%p + %x) = %x\n",
			 ei->base_addr, reg << ei->bus_shift, value);
		return !!(value & bit);
	}
}

static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct egpio_chip *egpio;

	egpio = gpiochip_get_data(chip);
	return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
}


/*
 * Output pins
 */

static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	unsigned long     flag;
	struct egpio_chip *egpio;
	struct egpio_info *ei;
	int               pos;
	int               reg;
	int               shift;

	pr_debug("egpio_set(%s, %d(%d), %d)\n",
			chip->label, offset, offset+chip->base, value);

	egpio = gpiochip_get_data(chip);
	ei    = dev_get_drvdata(egpio->dev);
	pos   = egpio_pos(ei, offset);
	reg   = egpio->reg_start + pos;
	shift = pos << ei->reg_shift;

	pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
			reg, (egpio->cached_values >> shift) & ei->reg_mask);

	spin_lock_irqsave(&ei->lock, flag);
	if (value)
		egpio->cached_values |= (1 << offset);
	else
		egpio->cached_values &= ~(1 << offset);
	egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
	spin_unlock_irqrestore(&ei->lock, flag);
}

static int egpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct egpio_chip *egpio;

	egpio = gpiochip_get_data(chip);
	if (test_bit(offset, &egpio->is_out)) {
		egpio_set(chip, offset, value);
		return 0;
	} else {
		return -EINVAL;
	}
}

static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	struct egpio_chip *egpio;

	egpio = gpiochip_get_data(chip);

	return !test_bit(offset, &egpio->is_out);
}

static void egpio_write_cache(struct egpio_info *ei)
{
	int               i;
	struct egpio_chip *egpio;
	int               shift;

	for (i = 0; i < ei->nchips; i++) {
		egpio = &(ei->chip[i]);
		if (!egpio->is_out)
			continue;

		for (shift = 0; shift < egpio->chip.ngpio;
				shift += (1<<ei->reg_shift)) {

			int reg = egpio->reg_start + egpio_pos(ei, shift);

			if (!((egpio->is_out >> shift) & ei->reg_mask))
				continue;

			pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
				(egpio->cached_values >> shift) & ei->reg_mask,
				egpio_readw(ei, reg));

			egpio_writew((egpio->cached_values >> shift)
					& ei->reg_mask, ei, reg);
		}
	}
}


/*
 * Setup
 */

static int __init egpio_probe(struct platform_device *pdev)
{
	struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct resource   *res;
	struct egpio_info *ei;
	struct gpio_chip  *chip;
	unsigned int      irq, irq_end;
	int               i;
	int               ret;

	/* Initialize ei data structure. */
	ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
	if (!ei)
		return -ENOMEM;

	spin_lock_init(&ei->lock);

	/* Find chained irq */
	ret = -EINVAL;
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (res)
		ei->chained_irq = res->start;

	/* Map egpio chip into virtual address space. */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		goto fail;
	ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start,
					     resource_size(res));
	if (!ei->base_addr)
		goto fail;
	pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);

	if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
		goto fail;
	ei->bus_shift = fls(pdata->bus_width - 1) - 3;
	pr_debug("bus_shift = %d\n", ei->bus_shift);

	if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
		goto fail;
	ei->reg_shift = fls(pdata->reg_width - 1);
	pr_debug("reg_shift = %d\n", ei->reg_shift);

	ei->reg_mask = (1 << pdata->reg_width) - 1;

	platform_set_drvdata(pdev, ei);

	ei->nchips = pdata->num_chips;
	ei->chip = devm_kcalloc(&pdev->dev,
				ei->nchips, sizeof(struct egpio_chip),
				GFP_KERNEL);
	if (!ei->chip) {
		ret = -ENOMEM;
		goto fail;
	}
	for (i = 0; i < ei->nchips; i++) {
		ei->chip[i].reg_start = pdata->chip[i].reg_start;
		ei->chip[i].cached_values = pdata->chip[i].initial_values;
		ei->chip[i].is_out = pdata->chip[i].direction;
		ei->chip[i].dev = &(pdev->dev);
		chip = &(ei->chip[i].chip);
		chip->label = devm_kasprintf(&pdev->dev, GFP_KERNEL,
					     "htc-egpio-%d",
					     i);
		if (!chip->label) {
			ret = -ENOMEM;
			goto fail;
		}
		chip->parent          = &pdev->dev;
		chip->owner           = THIS_MODULE;
		chip->get             = egpio_get;
		chip->set             = egpio_set;
		chip->direction_input = egpio_direction_input;
		chip->direction_output = egpio_direction_output;
		chip->get_direction   = egpio_get_direction;
		chip->base            = pdata->chip[i].gpio_base;
		chip->ngpio           = pdata->chip[i].num_gpios;

		gpiochip_add_data(chip, &ei->chip[i]);
	}

	/* Set initial pin values */
	egpio_write_cache(ei);

	ei->irq_start = pdata->irq_base;
	ei->nirqs = pdata->num_irqs;
	ei->ack_register = pdata->ack_register;

	if (ei->chained_irq) {
		/* Setup irq handlers */
		ei->ack_write = 0xFFFF;
		if (pdata->invert_acks)
			ei->ack_write = 0;
		irq_end = ei->irq_start + ei->nirqs;
		for (irq = ei->irq_start; irq < irq_end; irq++) {
			irq_set_chip_and_handler(irq, &egpio_muxed_chip,
						 handle_simple_irq);
			irq_set_chip_data(irq, ei);
			irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
		}
		irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
		irq_set_chained_handler_and_data(ei->chained_irq,
						 egpio_handler, ei);
		ack_irqs(ei);

		device_init_wakeup(&pdev->dev, 1);
	}

	return 0;

fail:
	printk(KERN_ERR "EGPIO failed to setup\n");
	return ret;
}

#ifdef CONFIG_PM
static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct egpio_info *ei = platform_get_drvdata(pdev);

	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
		enable_irq_wake(ei->chained_irq);
	return 0;
}

static int egpio_resume(struct platform_device *pdev)
{
	struct egpio_info *ei = platform_get_drvdata(pdev);

	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
		disable_irq_wake(ei->chained_irq);

	/* Update registers from the cache, in case
	   the CPLD was powered off during suspend */
	egpio_write_cache(ei);
	return 0;
}
#else
#define egpio_suspend NULL
#define egpio_resume NULL
#endif


static struct platform_driver egpio_driver = {
	.driver = {
		.name = "htc-egpio",
		.suppress_bind_attrs = true,
	},
	.suspend      = egpio_suspend,
	.resume       = egpio_resume,
};

static int __init egpio_init(void)
{
	return platform_driver_probe(&egpio_driver, egpio_probe);
}
/* start early for dependencies */
subsys_initcall(egpio_init);
Commit	Line	Data
a1635b8f PZ	1	/*
	2	* Support for the GPIO/IRQ expander chips present on several HTC phones.
	3	* These are implemented in CPLD chips present on the board.
	4	*
	5	* Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
	6	* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
	7	*
	8	* This file may be distributed under the terms of the GNU GPL license.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/errno.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/io.h>
	16	#include <linux/spinlock.h>
3c6e8d05	17	#include <linux/platform_data/gpio-htc-egpio.h>
a1635b8f	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
43bbf94c	20	#include <linux/init.h>
f63109f0	21	#include <linux/gpio/driver.h>
a1635b8f PZ	22
	23	struct egpio_chip {
	24	int reg_start;
	25	int cached_values;
	26	unsigned long is_out;
	27	struct device *dev;
	28	struct gpio_chip chip;
	29	};
	30
	31	struct egpio_info {
	32	spinlock_t lock;
	33
	34	/* iomem info */
	35	void __iomem *base_addr;
	36	int bus_shift; /* byte shift */
	37	int reg_shift; /* bit shift */
	38	int reg_mask;
	39
	40	/* irq info */
	41	int ack_register;
	42	int ack_write;
	43	u16 irqs_enabled;
	44	uint irq_start;
	45	int nirqs;
	46	uint chained_irq;
	47
	48	/* egpio info */
	49	struct egpio_chip *chip;
	50	int nchips;
	51	};
	52
	53	static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
	54	{
	55	writew(value, ei->base_addr + (reg << ei->bus_shift));
	56	}
	57
	58	static inline u16 egpio_readw(struct egpio_info *ei, int reg)
	59	{
	60	return readw(ei->base_addr + (reg << ei->bus_shift));
	61	}
	62
	63	/*
	64	* IRQs
	65	*/
	66
	67	static inline void ack_irqs(struct egpio_info *ei)
	68	{
	69	egpio_writew(ei->ack_write, ei, ei->ack_register);
	70	pr_debug("EGPIO ack - write %x to base+%x\n",
	71	ei->ack_write, ei->ack_register << ei->bus_shift);
	72	}
	73
949b9dec	74	static void egpio_ack(struct irq_data *data)
a1635b8f PZ	75	{
	76	}
	77
	78	/* There does not appear to be a way to proactively mask interrupts
	79	* on the egpio chip itself. So, we simply ignore interrupts that
	80	* aren't desired. */
949b9dec	81	static void egpio_mask(struct irq_data *data)
a1635b8f	82	{
949b9dec MB	83	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	84	ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
	85	pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
a1635b8f	86	}
949b9dec MB	87
949b9dec MB	88	static void egpio_unmask(struct irq_data *data)
a1635b8f	89	{
949b9dec MB	90	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
	91	ei->irqs_enabled \|= 1 << (data->irq - ei->irq_start);
	92	pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
a1635b8f PZ	93	}
	94
	95	static struct irq_chip egpio_muxed_chip = {
949b9dec MB	96	.name = "htc-egpio",
	97	.irq_ack = egpio_ack,
	98	.irq_mask = egpio_mask,
	99	.irq_unmask = egpio_unmask,
a1635b8f PZ	100	};
a1635b8f PZ	101
bd0b9ac4	102	static void egpio_handler(struct irq_desc *desc)
a1635b8f	103	{
77eda966	104	struct egpio_info *ei = irq_desc_get_handler_data(desc);
a1635b8f PZ	105	int irqpin;
	106
	107	/* Read current pins. */
	108	unsigned long readval = egpio_readw(ei, ei->ack_register);
	109	pr_debug("IRQ reg: %x\n", (unsigned int)readval);
	110	/* Ack/unmask interrupts. */
	111	ack_irqs(ei);
	112	/* Process all set pins. */
	113	readval &= ei->irqs_enabled;
984b3f57	114	for_each_set_bit(irqpin, &readval, ei->nirqs) {
a1635b8f PZ	115	/* Run irq handler */
a1635b8f PZ	116	pr_debug("got IRQ %d\n", irqpin);
77eda966	117	generic_handle_irq(ei->irq_start + irqpin);
a1635b8f PZ	118	}
	119	}
	120
	121	int htc_egpio_get_wakeup_irq(struct device *dev)
	122	{
	123	struct egpio_info *ei = dev_get_drvdata(dev);
	124
	125	/* Read current pins. */
	126	u16 readval = egpio_readw(ei, ei->ack_register);
	127	/* Ack/unmask interrupts. */
	128	ack_irqs(ei);
	129	/* Return first set pin. */
	130	readval &= ei->irqs_enabled;
	131	return ei->irq_start + ffs(readval) - 1;
	132	}
	133	EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
	134
	135	static inline int egpio_pos(struct egpio_info *ei, int bit)
	136	{
	137	return bit >> ei->reg_shift;
	138	}
	139
	140	static inline int egpio_bit(struct egpio_info *ei, int bit)
	141	{
	142	return 1 << (bit & ((1 << ei->reg_shift)-1));
	143	}
	144
	145	/*
	146	* Input pins
	147	*/
	148
	149	static int egpio_get(struct gpio_chip *chip, unsigned offset)
	150	{
	151	struct egpio_chip *egpio;
	152	struct egpio_info *ei;
	153	unsigned bit;
	154	int reg;
	155	int value;
	156
	157	pr_debug("egpio_get_value(%d)\n", chip->base + offset);
	158
8d5f095f	159	egpio = gpiochip_get_data(chip);
a1635b8f PZ	160	ei = dev_get_drvdata(egpio->dev);
	161	bit = egpio_bit(ei, offset);
	162	reg = egpio->reg_start + egpio_pos(ei, offset);
	163
24b35ed9 LW	164	if (test_bit(offset, &egpio->is_out)) {
	165	return !!(egpio->cached_values & (1 << offset));
	166	} else {
	167	value = egpio_readw(ei, reg);
	168	pr_debug("readw(%p + %x) = %x\n",
	169	ei->base_addr, reg << ei->bus_shift, value);
	170	return !!(value & bit);
	171	}
a1635b8f PZ	172	}
	173
	174	static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
	175	{
	176	struct egpio_chip *egpio;
	177
8d5f095f	178	egpio = gpiochip_get_data(chip);
a1635b8f PZ	179	return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
	180	}
	181
	182
	183	/*
	184	* Output pins
	185	*/
	186
	187	static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
	188	{
	189	unsigned long flag;
	190	struct egpio_chip *egpio;
	191	struct egpio_info *ei;
a1635b8f PZ	192	int pos;
	193	int reg;
	194	int shift;
	195
	196	pr_debug("egpio_set(%s, %d(%d), %d)\n",
	197	chip->label, offset, offset+chip->base, value);
	198
8d5f095f	199	egpio = gpiochip_get_data(chip);
a1635b8f	200	ei = dev_get_drvdata(egpio->dev);
a1635b8f PZ	201	pos = egpio_pos(ei, offset);
	202	reg = egpio->reg_start + pos;
	203	shift = pos << ei->reg_shift;
	204
	205	pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
	206	reg, (egpio->cached_values >> shift) & ei->reg_mask);
	207
	208	spin_lock_irqsave(&ei->lock, flag);
	209	if (value)
	210	egpio->cached_values \|= (1 << offset);
	211	else
	212	egpio->cached_values &= ~(1 << offset);
	213	egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
	214	spin_unlock_irqrestore(&ei->lock, flag);
	215	}
	216
	217	static int egpio_direction_output(struct gpio_chip *chip,
	218	unsigned offset, int value)
	219	{
	220	struct egpio_chip *egpio;
	221
8d5f095f	222	egpio = gpiochip_get_data(chip);
a1635b8f PZ	223	if (test_bit(offset, &egpio->is_out)) {
	224	egpio_set(chip, offset, value);
	225	return 0;
	226	} else {
	227	return -EINVAL;
	228	}
	229	}
	230
9298539c LW	231	static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
	232	{
	233	struct egpio_chip *egpio;
	234
	235	egpio = gpiochip_get_data(chip);
	236
	237	return !test_bit(offset, &egpio->is_out);
	238	}
	239
a1635b8f PZ	240	static void egpio_write_cache(struct egpio_info *ei)
	241	{
	242	int i;
	243	struct egpio_chip *egpio;
	244	int shift;
	245
	246	for (i = 0; i < ei->nchips; i++) {
	247	egpio = &(ei->chip[i]);
	248	if (!egpio->is_out)
	249	continue;
	250
	251	for (shift = 0; shift < egpio->chip.ngpio;
	252	shift += (1<<ei->reg_shift)) {
	253
	254	int reg = egpio->reg_start + egpio_pos(ei, shift);
	255
	256	if (!((egpio->is_out >> shift) & ei->reg_mask))
	257	continue;
	258
	259	pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
	260	(egpio->cached_values >> shift) & ei->reg_mask,
	261	egpio_readw(ei, reg));
	262
	263	egpio_writew((egpio->cached_values >> shift)
	264	& ei->reg_mask, ei, reg);
	265	}
	266	}
	267	}
	268
	269
	270	/*
	271	* Setup
	272	*/
	273
	274	static int __init egpio_probe(struct platform_device *pdev)
	275	{
334a41ce	276	struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
a1635b8f PZ	277	struct resource *res;
	278	struct egpio_info *ei;
	279	struct gpio_chip *chip;
	280	unsigned int irq, irq_end;
	281	int i;
	282	int ret;
	283
	284	/* Initialize ei data structure. */
58645b36	285	ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
a1635b8f PZ	286	if (!ei)
	287	return -ENOMEM;
	288
	289	spin_lock_init(&ei->lock);
	290
	291	/* Find chained irq */
	292	ret = -EINVAL;
	293	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	294	if (res)
	295	ei->chained_irq = res->start;
	296
	297	/* Map egpio chip into virtual address space. */
	298	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	299	if (!res)
	300	goto fail;
3f9850f2 WY	301	ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start,
3f9850f2 WY	302	resource_size(res));
a1635b8f PZ	303	if (!ei->base_addr)
a1635b8f PZ	304	goto fail;
504f97f8	305	pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);
a1635b8f PZ	306
	307	if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
	308	goto fail;
	309	ei->bus_shift = fls(pdata->bus_width - 1) - 3;
	310	pr_debug("bus_shift = %d\n", ei->bus_shift);
	311
	312	if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
	313	goto fail;
	314	ei->reg_shift = fls(pdata->reg_width - 1);
	315	pr_debug("reg_shift = %d\n", ei->reg_shift);
	316
	317	ei->reg_mask = (1 << pdata->reg_width) - 1;
	318
	319	platform_set_drvdata(pdev, ei);
	320
	321	ei->nchips = pdata->num_chips;
a86854d0 KC	322	ei->chip = devm_kcalloc(&pdev->dev,
a86854d0 KC	323	ei->nchips, sizeof(struct egpio_chip),
58645b36	324	GFP_KERNEL);
720fd66d	325	if (!ei->chip) {
a1635b8f PZ	326	ret = -ENOMEM;
	327	goto fail;
	328	}
	329	for (i = 0; i < ei->nchips; i++) {
	330	ei->chip[i].reg_start = pdata->chip[i].reg_start;
	331	ei->chip[i].cached_values = pdata->chip[i].initial_values;
	332	ei->chip[i].is_out = pdata->chip[i].direction;
	333	ei->chip[i].dev = &(pdev->dev);
	334	chip = &(ei->chip[i].chip);
212d7069 LW	335	chip->label = devm_kasprintf(&pdev->dev, GFP_KERNEL,
	336	"htc-egpio-%d",
	337	i);
	338	if (!chip->label) {
	339	ret = -ENOMEM;
	340	goto fail;
	341	}
58383c78	342	chip->parent = &pdev->dev;
d8f388d8	343	chip->owner = THIS_MODULE;
a1635b8f PZ	344	chip->get = egpio_get;
	345	chip->set = egpio_set;
	346	chip->direction_input = egpio_direction_input;
	347	chip->direction_output = egpio_direction_output;
9298539c	348	chip->get_direction = egpio_get_direction;
a1635b8f PZ	349	chip->base = pdata->chip[i].gpio_base;
	350	chip->ngpio = pdata->chip[i].num_gpios;
	351
8d5f095f	352	gpiochip_add_data(chip, &ei->chip[i]);
a1635b8f PZ	353	}
	354
	355	/* Set initial pin values */
	356	egpio_write_cache(ei);
	357
	358	ei->irq_start = pdata->irq_base;
	359	ei->nirqs = pdata->num_irqs;
	360	ei->ack_register = pdata->ack_register;
	361
	362	if (ei->chained_irq) {
	363	/* Setup irq handlers */
	364	ei->ack_write = 0xFFFF;
	365	if (pdata->invert_acks)
	366	ei->ack_write = 0;
	367	irq_end = ei->irq_start + ei->nirqs;
	368	for (irq = ei->irq_start; irq < irq_end; irq++) {
d6f7ce9f TG	369	irq_set_chip_and_handler(irq, &egpio_muxed_chip,
d6f7ce9f TG	370	handle_simple_irq);
d5bb1221	371	irq_set_chip_data(irq, ei);
9bd09f34	372	irq_clear_status_flags(irq, IRQ_NOREQUEST \| IRQ_NOPROBE);
a1635b8f	373	}
d5bb1221	374	irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
073f7f99 TG	375	irq_set_chained_handler_and_data(ei->chained_irq,
073f7f99 TG	376	egpio_handler, ei);
a1635b8f PZ	377	ack_irqs(ei);
	378
	379	device_init_wakeup(&pdev->dev, 1);
	380	}
	381
	382	return 0;
	383
	384	fail:
	385	printk(KERN_ERR "EGPIO failed to setup\n");
a1635b8f PZ	386	return ret;
	387	}
	388
a1635b8f PZ	389	#ifdef CONFIG_PM
	390	static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
	391	{
	392	struct egpio_info *ei = platform_get_drvdata(pdev);
	393
	394	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
	395	enable_irq_wake(ei->chained_irq);
	396	return 0;
	397	}
	398
	399	static int egpio_resume(struct platform_device *pdev)
	400	{
	401	struct egpio_info *ei = platform_get_drvdata(pdev);
	402
	403	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
	404	disable_irq_wake(ei->chained_irq);
	405
	406	/* Update registers from the cache, in case
	407	the CPLD was powered off during suspend */
	408	egpio_write_cache(ei);
	409	return 0;
	410	}
	411	#else
	412	#define egpio_suspend NULL
	413	#define egpio_resume NULL
	414	#endif
	415
	416
	417	static struct platform_driver egpio_driver = {
	418	.driver = {
	419	.name = "htc-egpio",
43bbf94c	420	.suppress_bind_attrs = true,
a1635b8f	421	},
a1635b8f PZ	422	.suspend = egpio_suspend,
	423	.resume = egpio_resume,
	424	};
	425
	426	static int __init egpio_init(void)
	427	{
	428	return platform_driver_probe(&egpio_driver, egpio_probe);
	429	}
a1635b8f PZ	430	/* start early for dependencies */
a1635b8f PZ	431	subsys_initcall(egpio_init);