[linux-2.6-block.git] / drivers / gpio / gpio-hlwd.c

// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2008-2009 The GameCube Linux Team
// Copyright (C) 2008,2009 Albert Herranz
// Copyright (C) 2017-2018 Jonathan Neuschäfer
//
// Nintendo Wii (Hollywood) GPIO driver

#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/slab.h>

/*
 * Register names and offsets courtesy of WiiBrew:
 * https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
 *
 * Note that for most registers, there are two versions:
 * - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
 *   always give access to all GPIO lines
 * - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
 *   firewall (AHBPROT) in the Hollywood chipset has been configured to allow
 *   such access.
 *
 * The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
 * register: A one bit configures the line for access via the HW_GPIOB_*
 * registers, a zero bit indicates access via HW_GPIO_*. This driver uses
 * HW_GPIOB_*.
 */
#define HW_GPIOB_OUT		0x00
#define HW_GPIOB_DIR		0x04
#define HW_GPIOB_IN		0x08
#define HW_GPIOB_INTLVL		0x0c
#define HW_GPIOB_INTFLAG	0x10
#define HW_GPIOB_INTMASK	0x14
#define HW_GPIOB_INMIR		0x18
#define HW_GPIO_ENABLE		0x1c
#define HW_GPIO_OUT		0x20
#define HW_GPIO_DIR		0x24
#define HW_GPIO_IN		0x28
#define HW_GPIO_INTLVL		0x2c
#define HW_GPIO_INTFLAG		0x30
#define HW_GPIO_INTMASK		0x34
#define HW_GPIO_INMIR		0x38
#define HW_GPIO_OWNER		0x3c

struct hlwd_gpio {
	struct gpio_chip gpioc;
	struct irq_chip irqc;
	void __iomem *regs;
	int irq;
	u32 edge_emulation;
	u32 rising_edge, falling_edge;
};

static void hlwd_gpio_irqhandler(struct irq_desc *desc)
{
	struct hlwd_gpio *hlwd =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned long flags;
	unsigned long pending;
	int hwirq;
	u32 emulated_pending;

	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
	pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);

	/* Treat interrupts due to edge trigger emulation separately */
	emulated_pending = hlwd->edge_emulation & pending;
	pending &= ~emulated_pending;
	if (emulated_pending) {
		u32 level, rising, falling;

		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
		rising = level & emulated_pending;
		falling = ~level & emulated_pending;

		/* Invert the levels */
		iowrite32be(level ^ emulated_pending,
			    hlwd->regs + HW_GPIOB_INTLVL);

		/* Ack all emulated-edge interrupts */
		iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);

		/* Signal interrupts only on the correct edge */
		rising &= hlwd->rising_edge;
		falling &= hlwd->falling_edge;

		/* Mark emulated interrupts as pending */
		pending |= rising | falling;
	}
	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);

	chained_irq_enter(chip, desc);

	for_each_set_bit(hwirq, &pending, 32) {
		int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);

		generic_handle_irq(irq);
	}

	chained_irq_exit(chip, desc);
}

static void hlwd_gpio_irq_ack(struct irq_data *data)
{
	struct hlwd_gpio *hlwd =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));

	iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
}

static void hlwd_gpio_irq_mask(struct irq_data *data)
{
	struct hlwd_gpio *hlwd =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));
	unsigned long flags;
	u32 mask;

	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
	mask &= ~BIT(data->hwirq);
	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
}

static void hlwd_gpio_irq_unmask(struct irq_data *data)
{
	struct hlwd_gpio *hlwd =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));
	unsigned long flags;
	u32 mask;

	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
	mask |= BIT(data->hwirq);
	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
}

static void hlwd_gpio_irq_enable(struct irq_data *data)
{
	hlwd_gpio_irq_ack(data);
	hlwd_gpio_irq_unmask(data);
}

static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
					  unsigned int flow_type)
{
	u32 level, state;

	/* Set the trigger level to the inactive level */
	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
	state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
	level &= ~BIT(hwirq);
	level |= state ^ BIT(hwirq);
	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);

	hlwd->edge_emulation |= BIT(hwirq);
	hlwd->rising_edge &= ~BIT(hwirq);
	hlwd->falling_edge &= ~BIT(hwirq);
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		hlwd->rising_edge |= BIT(hwirq);
	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		hlwd->falling_edge |= BIT(hwirq);
}

static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
	struct hlwd_gpio *hlwd =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));
	unsigned long flags;
	u32 level;

	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);

	hlwd->edge_emulation &= ~BIT(data->hwirq);

	switch (flow_type) {
	case IRQ_TYPE_LEVEL_HIGH:
		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
		level |= BIT(data->hwirq);
		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
		level &= ~BIT(data->hwirq);
		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
		break;
	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_EDGE_BOTH:
		hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
		break;
	default:
		spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
		return -EINVAL;
	}

	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
	return 0;
}

static int hlwd_gpio_probe(struct platform_device *pdev)
{
	struct hlwd_gpio *hlwd;
	u32 ngpios;
	int res;

	hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
	if (!hlwd)
		return -ENOMEM;

	hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(hlwd->regs))
		return PTR_ERR(hlwd->regs);

	/*
	 * Claim all GPIOs using the OWNER register. This will not work on
	 * systems where the AHBPROT memory firewall hasn't been configured to
	 * permit PPC access to HW_GPIO_*.
	 *
	 * Note that this has to happen before bgpio_init reads the
	 * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
	 * values.
	 */
	iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);

	res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
			hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
			NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
			BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	if (res < 0) {
		dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
		return res;
	}

	res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
	if (res)
		ngpios = 32;
	hlwd->gpioc.ngpio = ngpios;

	/* Mask and ack all interrupts */
	iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
	iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);

	/*
	 * If this GPIO controller is not marked as an interrupt controller in
	 * the DT, skip interrupt support.
	 */
	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
		struct gpio_irq_chip *girq;

		hlwd->irq = platform_get_irq(pdev, 0);
		if (hlwd->irq < 0) {
			dev_info(&pdev->dev, "platform_get_irq returned %d\n",
				 hlwd->irq);
			return hlwd->irq;
		}

		hlwd->irqc.name = dev_name(&pdev->dev);
		hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
		hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
		hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
		hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;

		girq = &hlwd->gpioc.irq;
		girq->chip = &hlwd->irqc;
		girq->parent_handler = hlwd_gpio_irqhandler;
		girq->num_parents = 1;
		girq->parents = devm_kcalloc(&pdev->dev, 1,
					     sizeof(*girq->parents),
					     GFP_KERNEL);
		if (!girq->parents)
			return -ENOMEM;
		girq->parents[0] = hlwd->irq;
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_level_irq;
	}

	return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
}

static const struct of_device_id hlwd_gpio_match[] = {
	{ .compatible = "nintendo,hollywood-gpio", },
	{},
};
MODULE_DEVICE_TABLE(of, hlwd_gpio_match);

static struct platform_driver hlwd_gpio_driver = {
	.driver	= {
		.name		= "gpio-hlwd",
		.of_match_table	= hlwd_gpio_match,
	},
	.probe	= hlwd_gpio_probe,
};
module_platform_driver(hlwd_gpio_driver);

MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
8f55fed3 JN	1	// SPDX-License-Identifier: GPL-2.0+
	2	// Copyright (C) 2008-2009 The GameCube Linux Team
	3	// Copyright (C) 2008,2009 Albert Herranz
	4	// Copyright (C) 2017-2018 Jonathan Neuschäfer
	5	//
	6	// Nintendo Wii (Hollywood) GPIO driver
	7
	8	#include <linux/gpio/driver.h>
	9	#include <linux/io.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
	13	#include <linux/of_platform.h>
	14	#include <linux/slab.h>
	15
	16	/*
	17	* Register names and offsets courtesy of WiiBrew:
	18	* https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
	19	*
	20	* Note that for most registers, there are two versions:
	21	* - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
	22	* always give access to all GPIO lines
	23	* - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
	24	* firewall (AHBPROT) in the Hollywood chipset has been configured to allow
	25	* such access.
	26	*
	27	* The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
	28	* register: A one bit configures the line for access via the HW_GPIOB_*
	29	* registers, a zero bit indicates access via HW_GPIO_*. This driver uses
	30	* HW_GPIOB_*.
	31	*/
	32	#define HW_GPIOB_OUT 0x00
	33	#define HW_GPIOB_DIR 0x04
	34	#define HW_GPIOB_IN 0x08
	35	#define HW_GPIOB_INTLVL 0x0c
	36	#define HW_GPIOB_INTFLAG 0x10
	37	#define HW_GPIOB_INTMASK 0x14
	38	#define HW_GPIOB_INMIR 0x18
	39	#define HW_GPIO_ENABLE 0x1c
	40	#define HW_GPIO_OUT 0x20
	41	#define HW_GPIO_DIR 0x24
	42	#define HW_GPIO_IN 0x28
	43	#define HW_GPIO_INTLVL 0x2c
	44	#define HW_GPIO_INTFLAG 0x30
	45	#define HW_GPIO_INTMASK 0x34
	46	#define HW_GPIO_INMIR 0x38
	47	#define HW_GPIO_OWNER 0x3c
	48
	49	struct hlwd_gpio {
	50	struct gpio_chip gpioc;
588de43c	51	struct irq_chip irqc;
8f55fed3	52	void __iomem *regs;
588de43c	53	int irq;
a7241c1b JN	54	u32 edge_emulation;
a7241c1b JN	55	u32 rising_edge, falling_edge;
8f55fed3 JN	56	};
8f55fed3 JN	57
588de43c JN	58	static void hlwd_gpio_irqhandler(struct irq_desc *desc)
	59	{
	60	struct hlwd_gpio *hlwd =
	61	gpiochip_get_data(irq_desc_get_handler_data(desc));
	62	struct irq_chip *chip = irq_desc_get_chip(desc);
	63	unsigned long flags;
	64	unsigned long pending;
	65	int hwirq;
a7241c1b	66	u32 emulated_pending;
588de43c JN	67
	68	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	69	pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
	70	pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
a7241c1b JN	71
	72	/* Treat interrupts due to edge trigger emulation separately */
	73	emulated_pending = hlwd->edge_emulation & pending;
	74	pending &= ~emulated_pending;
	75	if (emulated_pending) {
	76	u32 level, rising, falling;
	77
	78	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
	79	rising = level & emulated_pending;
	80	falling = ~level & emulated_pending;
	81
	82	/* Invert the levels */
	83	iowrite32be(level ^ emulated_pending,
	84	hlwd->regs + HW_GPIOB_INTLVL);
	85
	86	/* Ack all emulated-edge interrupts */
	87	iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
	88
	89	/* Signal interrupts only on the correct edge */
	90	rising &= hlwd->rising_edge;
	91	falling &= hlwd->falling_edge;
	92
	93	/* Mark emulated interrupts as pending */
	94	pending \|= rising \| falling;
	95	}
588de43c JN	96	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
	97
	98	chained_irq_enter(chip, desc);
	99
	100	for_each_set_bit(hwirq, &pending, 32) {
	101	int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
	102
	103	generic_handle_irq(irq);
	104	}
	105
	106	chained_irq_exit(chip, desc);
	107	}
	108
	109	static void hlwd_gpio_irq_ack(struct irq_data *data)
	110	{
	111	struct hlwd_gpio *hlwd =
	112	gpiochip_get_data(irq_data_get_irq_chip_data(data));
	113
	114	iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
	115	}
	116
	117	static void hlwd_gpio_irq_mask(struct irq_data *data)
	118	{
	119	struct hlwd_gpio *hlwd =
	120	gpiochip_get_data(irq_data_get_irq_chip_data(data));
	121	unsigned long flags;
	122	u32 mask;
	123
	124	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	125	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
	126	mask &= ~BIT(data->hwirq);
	127	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
	128	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
	129	}
	130
	131	static void hlwd_gpio_irq_unmask(struct irq_data *data)
	132	{
	133	struct hlwd_gpio *hlwd =
	134	gpiochip_get_data(irq_data_get_irq_chip_data(data));
	135	unsigned long flags;
	136	u32 mask;
	137
	138	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	139	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
	140	mask \|= BIT(data->hwirq);
	141	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
	142	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
	143	}
	144
	145	static void hlwd_gpio_irq_enable(struct irq_data *data)
	146	{
	147	hlwd_gpio_irq_ack(data);
	148	hlwd_gpio_irq_unmask(data);
	149	}
	150
a7241c1b JN	151	static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
	152	unsigned int flow_type)
	153	{
	154	u32 level, state;
	155
	156	/* Set the trigger level to the inactive level */
	157	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
	158	state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
	159	level &= ~BIT(hwirq);
	160	level \|= state ^ BIT(hwirq);
	161	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
	162
	163	hlwd->edge_emulation \|= BIT(hwirq);
	164	hlwd->rising_edge &= ~BIT(hwirq);
	165	hlwd->falling_edge &= ~BIT(hwirq);
	166	if (flow_type & IRQ_TYPE_EDGE_RISING)
	167	hlwd->rising_edge \|= BIT(hwirq);
	168	if (flow_type & IRQ_TYPE_EDGE_FALLING)
	169	hlwd->falling_edge \|= BIT(hwirq);
	170	}
	171
588de43c JN	172	static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
	173	{
	174	struct hlwd_gpio *hlwd =
	175	gpiochip_get_data(irq_data_get_irq_chip_data(data));
	176	unsigned long flags;
	177	u32 level;
	178
	179	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
	180
a7241c1b JN	181	hlwd->edge_emulation &= ~BIT(data->hwirq);
a7241c1b JN	182
588de43c JN	183	switch (flow_type) {
	184	case IRQ_TYPE_LEVEL_HIGH:
	185	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
	186	level \|= BIT(data->hwirq);
	187	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
	188	break;
	189	case IRQ_TYPE_LEVEL_LOW:
	190	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
	191	level &= ~BIT(data->hwirq);
	192	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
	193	break;
a7241c1b JN	194	case IRQ_TYPE_EDGE_RISING:
	195	case IRQ_TYPE_EDGE_FALLING:
	196	case IRQ_TYPE_EDGE_BOTH:
	197	hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
	198	break;
588de43c JN	199	default:
	200	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
	201	return -EINVAL;
	202	}
	203
	204	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
	205	return 0;
	206	}
	207
8f55fed3 JN	208	static int hlwd_gpio_probe(struct platform_device *pdev)
	209	{
	210	struct hlwd_gpio *hlwd;
8f55fed3 JN	211	u32 ngpios;
	212	int res;
	213
	214	hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
	215	if (!hlwd)
	216	return -ENOMEM;
	217
8f701e1d	218	hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
8f55fed3 JN	219	if (IS_ERR(hlwd->regs))
	220	return PTR_ERR(hlwd->regs);
	221
	222	/*
	223	* Claim all GPIOs using the OWNER register. This will not work on
	224	* systems where the AHBPROT memory firewall hasn't been configured to
	225	* permit PPC access to HW_GPIO_*.
	226	*
	227	* Note that this has to happen before bgpio_init reads the
	228	* HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
	229	* values.
	230	*/
	231	iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
	232
	233	res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
	234	hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
	235	NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
	236	BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	237	if (res < 0) {
	238	dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
	239	return res;
	240	}
	241
	242	res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
	243	if (res)
	244	ngpios = 32;
	245	hlwd->gpioc.ngpio = ngpios;
	246
588de43c JN	247	/* Mask and ack all interrupts */
	248	iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
	249	iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
	250
	251	/*
	252	* If this GPIO controller is not marked as an interrupt controller in
a2ac3eb3	253	* the DT, skip interrupt support.
588de43c	254	*/
a2ac3eb3 LW	255	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
	256	struct gpio_irq_chip *girq;
	257
	258	hlwd->irq = platform_get_irq(pdev, 0);
	259	if (hlwd->irq < 0) {
	260	dev_info(&pdev->dev, "platform_get_irq returned %d\n",
	261	hlwd->irq);
	262	return hlwd->irq;
	263	}
	264
	265	hlwd->irqc.name = dev_name(&pdev->dev);
	266	hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
	267	hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
	268	hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
	269	hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
	270
	271	girq = &hlwd->gpioc.irq;
	272	girq->chip = &hlwd->irqc;
	273	girq->parent_handler = hlwd_gpio_irqhandler;
	274	girq->num_parents = 1;
	275	girq->parents = devm_kcalloc(&pdev->dev, 1,
	276	sizeof(*girq->parents),
	277	GFP_KERNEL);
	278	if (!girq->parents)
	279	return -ENOMEM;
	280	girq->parents[0] = hlwd->irq;
	281	girq->default_type = IRQ_TYPE_NONE;
	282	girq->handler = handle_level_irq;
588de43c JN	283	}
588de43c JN	284
a2ac3eb3	285	return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
8f55fed3 JN	286	}
	287
	288	static const struct of_device_id hlwd_gpio_match[] = {
	289	{ .compatible = "nintendo,hollywood-gpio", },
	290	{},
	291	};
	292	MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
	293
	294	static struct platform_driver hlwd_gpio_driver = {
	295	.driver = {
	296	.name = "gpio-hlwd",
	297	.of_match_table = hlwd_gpio_match,
	298	},
	299	.probe = hlwd_gpio_probe,
	300	};
	301	module_platform_driver(hlwd_gpio_driver);
	302
	303	MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
	304	MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
	305	MODULE_LICENSE("GPL");