[linux-2.6-block.git] / drivers / gpio / gpio-grgpio.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
 *
 * 2013 (c) Aeroflex Gaisler AB
 *
 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
 * IP core library.
 *
 * Full documentation of the GRGPIO core can be found here:
 * http://www.gaisler.com/products/grlib/grip.pdf
 *
 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
 * information on open firmware properties.
 *
 * Contributors: Andreas Larsson <andreas@gaisler.com>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>

#define GRGPIO_MAX_NGPIO 32

#define GRGPIO_DATA		0x00
#define GRGPIO_OUTPUT		0x04
#define GRGPIO_DIR		0x08
#define GRGPIO_IMASK		0x0c
#define GRGPIO_IPOL		0x10
#define GRGPIO_IEDGE		0x14
#define GRGPIO_BYPASS		0x18
#define GRGPIO_IMAP_BASE	0x20

/* Structure for an irq of the core - called an underlying irq */
struct grgpio_uirq {
	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
	u8 uirq; /* Underlying irq of the gpio driver */
};

/*
 * Structure for an irq of a gpio line handed out by this driver. The index is
 * used to map to the corresponding underlying irq.
 */
struct grgpio_lirq {
	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
	u8 irq; /* irq for the gpio line */
};

struct grgpio_priv {
	struct gpio_chip gc;
	void __iomem *regs;
	struct device *dev;

	u32 imask; /* irq mask shadow register */

	/*
	 * The grgpio core can have multiple "underlying" irqs. The gpio lines
	 * can be mapped to any one or none of these underlying irqs
	 * independently of each other. This driver sets up an irq domain and
	 * hands out separate irqs to each gpio line
	 */
	struct irq_domain *domain;

	/*
	 * This array contains information on each underlying irq, each
	 * irq of the grgpio core itself.
	 */
	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];

	/*
	 * This array contains information for each gpio line on the irqs
	 * obtains from this driver. An index value of -1 for a certain gpio
	 * line indicates that the line has no irq. Otherwise the index connects
	 * the irq to the underlying irq by pointing into the uirqs array.
	 */
	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
};

static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
			     int val)
{
	struct gpio_chip *gc = &priv->gc;

	if (val)
		priv->imask |= BIT(offset);
	else
		priv->imask &= ~BIT(offset);
	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
}

static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct grgpio_priv *priv = gpiochip_get_data(gc);

	if (offset >= gc->ngpio)
		return -ENXIO;

	if (priv->lirqs[offset].index < 0)
		return -ENXIO;

	return irq_create_mapping(priv->domain, offset);
}

/* -------------------- IRQ chip functions -------------------- */

static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
	unsigned long flags;
	u32 mask = BIT(d->hwirq);
	u32 ipol;
	u32 iedge;
	u32 pol;
	u32 edge;

	switch (type) {
	case IRQ_TYPE_LEVEL_LOW:
		pol = 0;
		edge = 0;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		pol = mask;
		edge = 0;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		pol = 0;
		edge = mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		pol = mask;
		edge = mask;
		break;
	default:
		return -EINVAL;
	}

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;

	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	return 0;
}

static void grgpio_irq_mask(struct irq_data *d)
{
	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	unsigned long flags;

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	grgpio_set_imask(priv, offset, 0);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
}

static void grgpio_irq_unmask(struct irq_data *d)
{
	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	unsigned long flags;

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	grgpio_set_imask(priv, offset, 1);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
}

static struct irq_chip grgpio_irq_chip = {
	.name			= "grgpio",
	.irq_mask		= grgpio_irq_mask,
	.irq_unmask		= grgpio_irq_unmask,
	.irq_set_type		= grgpio_irq_set_type,
};

static irqreturn_t grgpio_irq_handler(int irq, void *dev)
{
	struct grgpio_priv *priv = dev;
	int ngpio = priv->gc.ngpio;
	unsigned long flags;
	int i;
	int match = 0;

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	/*
	 * For each gpio line, call its interrupt handler if it its underlying
	 * irq matches the current irq that is handled.
	 */
	for (i = 0; i < ngpio; i++) {
		struct grgpio_lirq *lirq = &priv->lirqs[i];

		if (priv->imask & BIT(i) && lirq->index >= 0 &&
		    priv->uirqs[lirq->index].uirq == irq) {
			generic_handle_irq(lirq->irq);
			match = 1;
		}
	}

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	if (!match)
		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);

	return IRQ_HANDLED;
}

/*
 * This function will be called as a consequence of the call to
 * irq_create_mapping in grgpio_to_irq
 */
static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
			  irq_hw_number_t hwirq)
{
	struct grgpio_priv *priv = d->host_data;
	struct grgpio_lirq *lirq;
	struct grgpio_uirq *uirq;
	unsigned long flags;
	int offset = hwirq;
	int ret = 0;

	if (!priv)
		return -EINVAL;

	lirq = &priv->lirqs[offset];
	if (lirq->index < 0)
		return -EINVAL;

	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
		irq, offset);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	/* Request underlying irq if not already requested */
	lirq->irq = irq;
	uirq = &priv->uirqs[lirq->index];
	if (uirq->refcnt == 0) {
		raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
				  dev_name(priv->dev), priv);
		if (ret) {
			dev_err(priv->dev,
				"Could not request underlying irq %d\n",
				uirq->uirq);
			return ret;
		}
		raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
	}
	uirq->refcnt++;

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	/* Setup irq  */
	irq_set_chip_data(irq, priv);
	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
				 handle_simple_irq);
	irq_set_noprobe(irq);

	return ret;
}

static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
	struct grgpio_priv *priv = d->host_data;
	int index;
	struct grgpio_lirq *lirq;
	struct grgpio_uirq *uirq;
	unsigned long flags;
	int ngpio = priv->gc.ngpio;
	int i;

	irq_set_chip_and_handler(irq, NULL, NULL);
	irq_set_chip_data(irq, NULL);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	/* Free underlying irq if last user unmapped */
	index = -1;
	for (i = 0; i < ngpio; i++) {
		lirq = &priv->lirqs[i];
		if (lirq->irq == irq) {
			grgpio_set_imask(priv, i, 0);
			lirq->irq = 0;
			index = lirq->index;
			break;
		}
	}
	WARN_ON(index < 0);

	if (index >= 0) {
		uirq = &priv->uirqs[lirq->index];
		uirq->refcnt--;
		if (uirq->refcnt == 0) {
			raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
			free_irq(uirq->uirq, priv);
			return;
		}
	}

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
}

static const struct irq_domain_ops grgpio_irq_domain_ops = {
	.map	= grgpio_irq_map,
	.unmap	= grgpio_irq_unmap,
};

/* ------------------------------------------------------------ */

static int grgpio_probe(struct platform_device *ofdev)
{
	struct device_node *np = ofdev->dev.of_node;
	void  __iomem *regs;
	struct gpio_chip *gc;
	struct grgpio_priv *priv;
	int err;
	u32 prop;
	s32 *irqmap;
	int size;
	int i;

	priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	regs = devm_platform_ioremap_resource(ofdev, 0);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	gc = &priv->gc;
	err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
			 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
			 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	if (err) {
		dev_err(&ofdev->dev, "bgpio_init() failed\n");
		return err;
	}

	priv->regs = regs;
	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
	priv->dev = &ofdev->dev;

	gc->owner = THIS_MODULE;
	gc->to_irq = grgpio_to_irq;
	gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
	gc->base = -1;

	err = of_property_read_u32(np, "nbits", &prop);
	if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
		gc->ngpio = GRGPIO_MAX_NGPIO;
		dev_dbg(&ofdev->dev,
			"No or invalid nbits property: assume %d\n", gc->ngpio);
	} else {
		gc->ngpio = prop;
	}

	/*
	 * The irqmap contains the index values indicating which underlying irq,
	 * if anyone, is connected to that line
	 */
	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
	if (irqmap) {
		if (size < gc->ngpio) {
			dev_err(&ofdev->dev,
				"irqmap shorter than ngpio (%d < %d)\n",
				size, gc->ngpio);
			return -EINVAL;
		}

		priv->domain = irq_domain_add_linear(np, gc->ngpio,
						     &grgpio_irq_domain_ops,
						     priv);
		if (!priv->domain) {
			dev_err(&ofdev->dev, "Could not add irq domain\n");
			return -EINVAL;
		}

		for (i = 0; i < gc->ngpio; i++) {
			struct grgpio_lirq *lirq;
			int ret;

			lirq = &priv->lirqs[i];
			lirq->index = irqmap[i];

			if (lirq->index < 0)
				continue;

			ret = platform_get_irq(ofdev, lirq->index);
			if (ret <= 0) {
				/*
				 * Continue without irq functionality for that
				 * gpio line
				 */
				continue;
			}
			priv->uirqs[lirq->index].uirq = ret;
		}
	}

	platform_set_drvdata(ofdev, priv);

	err = gpiochip_add_data(gc, priv);
	if (err) {
		dev_err(&ofdev->dev, "Could not add gpiochip\n");
		if (priv->domain)
			irq_domain_remove(priv->domain);
		return err;
	}

	dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
		 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");

	return 0;
}

static void grgpio_remove(struct platform_device *ofdev)
{
	struct grgpio_priv *priv = platform_get_drvdata(ofdev);

	gpiochip_remove(&priv->gc);

	if (priv->domain)
		irq_domain_remove(priv->domain);
}

static const struct of_device_id grgpio_match[] = {
	{.name = "GAISLER_GPIO"},
	{.name = "01_01a"},
	{},
};

MODULE_DEVICE_TABLE(of, grgpio_match);

static struct platform_driver grgpio_driver = {
	.driver = {
		.name = "grgpio",
		.of_match_table = grgpio_match,
	},
	.probe = grgpio_probe,
	.remove_new = grgpio_remove,
};
module_platform_driver(grgpio_driver);

MODULE_AUTHOR("Aeroflex Gaisler AB.");
MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
ddb27f3b AL	2	/*
	3	* Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
	4	*
	5	* 2013 (c) Aeroflex Gaisler AB
	6	*
	7	* This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
	8	* IP core library.
	9	*
	10	* Full documentation of the GRGPIO core can be found here:
	11	* http://www.gaisler.com/products/grlib/grip.pdf
	12	*
	13	* See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
	14	* information on open firmware properties.
	15	*
ddb27f3b AL	16	* Contributors: Andreas Larsson <andreas@gaisler.com>
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
e91d0f05	22	#include <linux/platform_device.h>
ddb27f3b AL	23	#include <linux/spinlock.h>
	24	#include <linux/io.h>
	25	#include <linux/of.h>
00d712a9	26	#include <linux/gpio/driver.h>
ddb27f3b AL	27	#include <linux/slab.h>
ddb27f3b AL	28	#include <linux/err.h>
08ffb222 AL	29	#include <linux/interrupt.h>
	30	#include <linux/irq.h>
	31	#include <linux/irqdomain.h>
5c7b0c4e	32	#include <linux/bitops.h>
ddb27f3b AL	33
	34	#define GRGPIO_MAX_NGPIO 32
	35
	36	#define GRGPIO_DATA 0x00
	37	#define GRGPIO_OUTPUT 0x04
	38	#define GRGPIO_DIR 0x08
	39	#define GRGPIO_IMASK 0x0c
	40	#define GRGPIO_IPOL 0x10
	41	#define GRGPIO_IEDGE 0x14
	42	#define GRGPIO_BYPASS 0x18
	43	#define GRGPIO_IMAP_BASE 0x20
	44
08ffb222 AL	45	/* Structure for an irq of the core - called an underlying irq */
	46	struct grgpio_uirq {
	47	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
	48	u8 uirq; /* Underlying irq of the gpio driver */
	49	};
	50
	51	/*
	52	* Structure for an irq of a gpio line handed out by this driver. The index is
	53	* used to map to the corresponding underlying irq.
	54	*/
	55	struct grgpio_lirq {
	56	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
	57	u8 irq; /* irq for the gpio line */
	58	};
	59
ddb27f3b	60	struct grgpio_priv {
0f4630f3	61	struct gpio_chip gc;
ddb27f3b AL	62	void __iomem *regs;
ddb27f3b AL	63	struct device *dev;
08ffb222 AL	64
	65	u32 imask; /* irq mask shadow register */
	66
	67	/*
	68	* The grgpio core can have multiple "underlying" irqs. The gpio lines
	69	* can be mapped to any one or none of these underlying irqs
	70	* independently of each other. This driver sets up an irq domain and
	71	* hands out separate irqs to each gpio line
	72	*/
	73	struct irq_domain *domain;
	74
	75	/*
	76	* This array contains information on each underlying irq, each
	77	* irq of the grgpio core itself.
	78	*/
	79	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
	80
	81	/*
	82	* This array contains information for each gpio line on the irqs
	83	* obtains from this driver. An index value of -1 for a certain gpio
	84	* line indicates that the line has no irq. Otherwise the index connects
	85	* the irq to the underlying irq by pointing into the uirqs array.
	86	*/
	87	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
ddb27f3b AL	88	};
ddb27f3b AL	89
08ffb222 AL	90	static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
	91	int val)
	92	{
0f4630f3	93	struct gpio_chip *gc = &priv->gc;
08ffb222 AL	94
08ffb222 AL	95	if (val)
5c7b0c4e	96	priv->imask \|= BIT(offset);
08ffb222	97	else
5c7b0c4e	98	priv->imask &= ~BIT(offset);
0f4630f3	99	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
08ffb222 AL	100	}
	101
	102	static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
	103	{
0f4630f3	104	struct grgpio_priv *priv = gpiochip_get_data(gc);
08ffb222	105
d3c2155c	106	if (offset >= gc->ngpio)
08ffb222 AL	107	return -ENXIO;
	108
	109	if (priv->lirqs[offset].index < 0)
	110	return -ENXIO;
	111
	112	return irq_create_mapping(priv->domain, offset);
	113	}
	114
	115	/* -------------------- IRQ chip functions -------------------- */
	116
	117	static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
	118	{
	119	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
	120	unsigned long flags;
	121	u32 mask = BIT(d->hwirq);
	122	u32 ipol;
	123	u32 iedge;
	124	u32 pol;
	125	u32 edge;
	126
	127	switch (type) {
	128	case IRQ_TYPE_LEVEL_LOW:
	129	pol = 0;
	130	edge = 0;
	131	break;
	132	case IRQ_TYPE_LEVEL_HIGH:
	133	pol = mask;
	134	edge = 0;
	135	break;
	136	case IRQ_TYPE_EDGE_FALLING:
	137	pol = 0;
	138	edge = mask;
	139	break;
	140	case IRQ_TYPE_EDGE_RISING:
	141	pol = mask;
	142	edge = mask;
	143	break;
	144	default:
	145	return -EINVAL;
	146	}
	147
3c938cc5	148	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222	149
0f4630f3 LW	150	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
0f4630f3 LW	151	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
08ffb222	152
0f4630f3 LW	153	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol \| pol);
0f4630f3 LW	154	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge \| edge);
08ffb222	155
3c938cc5	156	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	157
	158	return 0;
	159	}
	160
	161	static void grgpio_irq_mask(struct irq_data *d)
	162	{
	163	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
	164	int offset = d->hwirq;
7fa25937 AC	165	unsigned long flags;
7fa25937 AC	166
3c938cc5	167	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222 AL	168
08ffb222 AL	169	grgpio_set_imask(priv, offset, 0);
7fa25937	170
3c938cc5	171	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	172	}
	173
	174	static void grgpio_irq_unmask(struct irq_data *d)
	175	{
	176	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
	177	int offset = d->hwirq;
7fa25937 AC	178	unsigned long flags;
7fa25937 AC	179
3c938cc5	180	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222 AL	181
08ffb222 AL	182	grgpio_set_imask(priv, offset, 1);
7fa25937	183
3c938cc5	184	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	185	}
	186
	187	static struct irq_chip grgpio_irq_chip = {
	188	.name = "grgpio",
	189	.irq_mask = grgpio_irq_mask,
	190	.irq_unmask = grgpio_irq_unmask,
	191	.irq_set_type = grgpio_irq_set_type,
	192	};
	193
	194	static irqreturn_t grgpio_irq_handler(int irq, void *dev)
	195	{
	196	struct grgpio_priv *priv = dev;
0f4630f3	197	int ngpio = priv->gc.ngpio;
08ffb222 AL	198	unsigned long flags;
	199	int i;
	200	int match = 0;
	201
3c938cc5	202	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222 AL	203
	204	/*
	205	* For each gpio line, call its interrupt handler if it its underlying
	206	* irq matches the current irq that is handled.
	207	*/
	208	for (i = 0; i < ngpio; i++) {
	209	struct grgpio_lirq *lirq = &priv->lirqs[i];
	210
	211	if (priv->imask & BIT(i) && lirq->index >= 0 &&
	212	priv->uirqs[lirq->index].uirq == irq) {
	213	generic_handle_irq(lirq->irq);
	214	match = 1;
	215	}
	216	}
	217
3c938cc5	218	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	219
	220	if (!match)
	221	dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
	222
	223	return IRQ_HANDLED;
	224	}
	225
	226	/*
	227	* This function will be called as a consequence of the call to
	228	* irq_create_mapping in grgpio_to_irq
	229	*/
61e3884e SK	230	static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
61e3884e SK	231	irq_hw_number_t hwirq)
08ffb222 AL	232	{
	233	struct grgpio_priv *priv = d->host_data;
	234	struct grgpio_lirq *lirq;
	235	struct grgpio_uirq *uirq;
	236	unsigned long flags;
	237	int offset = hwirq;
	238	int ret = 0;
	239
	240	if (!priv)
	241	return -EINVAL;
	242
	243	lirq = &priv->lirqs[offset];
	244	if (lirq->index < 0)
	245	return -EINVAL;
	246
	247	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
	248	irq, offset);
	249
3c938cc5	250	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222 AL	251
	252	/* Request underlying irq if not already requested */
	253	lirq->irq = irq;
	254	uirq = &priv->uirqs[lirq->index];
	255	if (uirq->refcnt == 0) {
3c938cc5	256	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	257	ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
	258	dev_name(priv->dev), priv);
	259	if (ret) {
	260	dev_err(priv->dev,
	261	"Could not request underlying irq %d\n",
	262	uirq->uirq);
08ffb222 AL	263	return ret;
08ffb222 AL	264	}
3c938cc5	265	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222 AL	266	}
	267	uirq->refcnt++;
	268
3c938cc5	269	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	270
	271	/* Setup irq */
	272	irq_set_chip_data(irq, priv);
	273	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
	274	handle_simple_irq);
08ffb222	275	irq_set_noprobe(irq);
08ffb222 AL	276
	277	return ret;
	278	}
	279
61e3884e	280	static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
08ffb222 AL	281	{
	282	struct grgpio_priv *priv = d->host_data;
	283	int index;
	284	struct grgpio_lirq *lirq;
	285	struct grgpio_uirq *uirq;
	286	unsigned long flags;
0f4630f3	287	int ngpio = priv->gc.ngpio;
08ffb222 AL	288	int i;
08ffb222 AL	289
08ffb222 AL	290	irq_set_chip_and_handler(irq, NULL, NULL);
	291	irq_set_chip_data(irq, NULL);
	292
3c938cc5	293	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
08ffb222 AL	294
	295	/* Free underlying irq if last user unmapped */
	296	index = -1;
	297	for (i = 0; i < ngpio; i++) {
	298	lirq = &priv->lirqs[i];
	299	if (lirq->irq == irq) {
	300	grgpio_set_imask(priv, i, 0);
	301	lirq->irq = 0;
	302	index = lirq->index;
	303	break;
	304	}
	305	}
	306	WARN_ON(index < 0);
	307
	308	if (index >= 0) {
	309	uirq = &priv->uirqs[lirq->index];
	310	uirq->refcnt--;
e36eaf94	311	if (uirq->refcnt == 0) {
3c938cc5	312	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222	313	free_irq(uirq->uirq, priv);
e36eaf94 JJB	314	return;
e36eaf94 JJB	315	}
08ffb222 AL	316	}
08ffb222 AL	317
3c938cc5	318	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
08ffb222 AL	319	}
08ffb222 AL	320
0b354dc4	321	static const struct irq_domain_ops grgpio_irq_domain_ops = {
08ffb222 AL	322	.map = grgpio_irq_map,
	323	.unmap = grgpio_irq_unmap,
	324	};
	325
	326	/* ------------------------------------------------------------ */
	327
ddb27f3b AL	328	static int grgpio_probe(struct platform_device *ofdev)
	329	{
	330	struct device_node *np = ofdev->dev.of_node;
	331	void __iomem *regs;
	332	struct gpio_chip *gc;
ddb27f3b	333	struct grgpio_priv *priv;
ddb27f3b AL	334	int err;
ddb27f3b AL	335	u32 prop;
08ffb222 AL	336	s32 *irqmap;
	337	int size;
	338	int i;
ddb27f3b AL	339
	340	priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
	341	if (!priv)
	342	return -ENOMEM;
	343
01d078aa	344	regs = devm_platform_ioremap_resource(ofdev, 0);
ddb27f3b AL	345	if (IS_ERR(regs))
	346	return PTR_ERR(regs);
	347
0f4630f3 LW	348	gc = &priv->gc;
0f4630f3 LW	349	err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
ddb27f3b AL	350	regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
	351	BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	352	if (err) {
	353	dev_err(&ofdev->dev, "bgpio_init() failed\n");
	354	return err;
	355	}
	356
	357	priv->regs = regs;
0f4630f3	358	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
ddb27f3b AL	359	priv->dev = &ofdev->dev;
ddb27f3b AL	360
ddb27f3b	361	gc->owner = THIS_MODULE;
08ffb222	362	gc->to_irq = grgpio_to_irq;
7eb6ce2f	363	gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
ddb27f3b AL	364	gc->base = -1;
	365
	366	err = of_property_read_u32(np, "nbits", &prop);
	367	if (err \|\| prop <= 0 \|\| prop > GRGPIO_MAX_NGPIO) {
	368	gc->ngpio = GRGPIO_MAX_NGPIO;
	369	dev_dbg(&ofdev->dev,
	370	"No or invalid nbits property: assume %d\n", gc->ngpio);
	371	} else {
	372	gc->ngpio = prop;
	373	}
	374
08ffb222 AL	375	/*
	376	* The irqmap contains the index values indicating which underlying irq,
	377	* if anyone, is connected to that line
	378	*/
	379	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
	380	if (irqmap) {
	381	if (size < gc->ngpio) {
	382	dev_err(&ofdev->dev,
	383	"irqmap shorter than ngpio (%d < %d)\n",
	384	size, gc->ngpio);
	385	return -EINVAL;
	386	}
	387
	388	priv->domain = irq_domain_add_linear(np, gc->ngpio,
	389	&grgpio_irq_domain_ops,
	390	priv);
	391	if (!priv->domain) {
	392	dev_err(&ofdev->dev, "Could not add irq domain\n");
	393	return -EINVAL;
	394	}
	395
	396	for (i = 0; i < gc->ngpio; i++) {
	397	struct grgpio_lirq *lirq;
	398	int ret;
	399
	400	lirq = &priv->lirqs[i];
	401	lirq->index = irqmap[i];
	402
	403	if (lirq->index < 0)
	404	continue;
	405
	406	ret = platform_get_irq(ofdev, lirq->index);
	407	if (ret <= 0) {
	408	/*
	409	* Continue without irq functionality for that
	410	* gpio line
	411	*/
08ffb222 AL	412	continue;
	413	}
	414	priv->uirqs[lirq->index].uirq = ret;
	415	}
	416	}
	417
ddb27f3b AL	418	platform_set_drvdata(ofdev, priv);
ddb27f3b AL	419
0f4630f3	420	err = gpiochip_add_data(gc, priv);
ddb27f3b AL	421	if (err) {
ddb27f3b AL	422	dev_err(&ofdev->dev, "Could not add gpiochip\n");
879828c6 AL	423	if (priv->domain)
879828c6 AL	424	irq_domain_remove(priv->domain);
ddb27f3b AL	425	return err;
	426	}
	427
08ffb222 AL	428	dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
08ffb222 AL	429	priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
ddb27f3b AL	430
	431	return 0;
	432	}
	433
b6c43915	434	static void grgpio_remove(struct platform_device *ofdev)
ddb27f3b AL	435	{
ddb27f3b AL	436	struct grgpio_priv *priv = platform_get_drvdata(ofdev);
08ffb222	437
0f4630f3	438	gpiochip_remove(&priv->gc);
08ffb222 AL	439
	440	if (priv->domain)
	441	irq_domain_remove(priv->domain);
ddb27f3b AL	442	}
ddb27f3b AL	443
f77b6448	444	static const struct of_device_id grgpio_match[] = {
ddb27f3b AL	445	{.name = "GAISLER_GPIO"},
	446	{.name = "01_01a"},
	447	{},
	448	};
	449
	450	MODULE_DEVICE_TABLE(of, grgpio_match);
	451
	452	static struct platform_driver grgpio_driver = {
	453	.driver = {
	454	.name = "grgpio",
ddb27f3b AL	455	.of_match_table = grgpio_match,
	456	},
	457	.probe = grgpio_probe,
b6c43915	458	.remove_new = grgpio_remove,
ddb27f3b AL	459	};
	460	module_platform_driver(grgpio_driver);
	461
	462	MODULE_AUTHOR("Aeroflex Gaisler AB.");
	463	MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
	464	MODULE_LICENSE("GPL");