Commit | Line | Data |
---|---|---|
aeec56e3 | 1 | /* |
c103de24 | 2 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
3 | * |
4 | * Copyright 2008 MontaVista Software, Inc. | |
5 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... | |
13 | * ...`` ```````.. | |
14 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
15 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
16 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
17 | * ````````` | |
18 | ___ | |
19 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
20 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
21 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
22 | `....trivial..'~`.```.``` | |
23 | * ``````` | |
24 | * .```````~~~~`..`.``.``. | |
25 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
26 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
27 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
28 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
29 | * ``.`.``...``` ```.. output pins are also supported.` | |
30 | * ^^ `````.`````````.,``~``~``~~`````` | |
31 | * . ^^ | |
32 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
33 | * .. The expectation is that in at least some cases . ,-~~~-, | |
34 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
35 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
36 | * ..````````......``````````` \o_ | |
37 | * | | |
38 | * ^^ / \ | |
39 | * | |
40 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
41 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
42 | * . the number of GPIOs is determined by the width of ~ | |
43 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
44 | * `.......````.``` | |
45 | */ | |
46 | ||
47 | #include <linux/init.h> | |
280df6b3 | 48 | #include <linux/err.h> |
aeec56e3 AV |
49 | #include <linux/bug.h> |
50 | #include <linux/kernel.h> | |
51 | #include <linux/module.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/compiler.h> | |
54 | #include <linux/types.h> | |
55 | #include <linux/errno.h> | |
56 | #include <linux/log2.h> | |
57 | #include <linux/ioport.h> | |
58 | #include <linux/io.h> | |
59 | #include <linux/gpio.h> | |
60 | #include <linux/slab.h> | |
61 | #include <linux/platform_device.h> | |
62 | #include <linux/mod_devicetable.h> | |
63 | #include <linux/basic_mmio_gpio.h> | |
64 | ||
8467afec | 65 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 66 | { |
fd996235 | 67 | writeb(data, reg); |
aeec56e3 AV |
68 | } |
69 | ||
8467afec | 70 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 71 | { |
fd996235 | 72 | return readb(reg); |
8467afec JI |
73 | } |
74 | ||
75 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
76 | { | |
fd996235 | 77 | writew(data, reg); |
8467afec JI |
78 | } |
79 | ||
80 | static unsigned long bgpio_read16(void __iomem *reg) | |
81 | { | |
fd996235 | 82 | return readw(reg); |
8467afec JI |
83 | } |
84 | ||
85 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
86 | { | |
fd996235 | 87 | writel(data, reg); |
8467afec JI |
88 | } |
89 | ||
90 | static unsigned long bgpio_read32(void __iomem *reg) | |
91 | { | |
fd996235 | 92 | return readl(reg); |
8467afec JI |
93 | } |
94 | ||
aeec56e3 | 95 | #if BITS_PER_LONG >= 64 |
8467afec JI |
96 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
97 | { | |
fd996235 | 98 | writeq(data, reg); |
8467afec JI |
99 | } |
100 | ||
101 | static unsigned long bgpio_read64(void __iomem *reg) | |
102 | { | |
fd996235 | 103 | return readq(reg); |
aeec56e3 | 104 | } |
8467afec | 105 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 | 106 | |
2b78f1e1 AL |
107 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
108 | { | |
109 | iowrite16be(data, reg); | |
110 | } | |
111 | ||
112 | static unsigned long bgpio_read16be(void __iomem *reg) | |
113 | { | |
114 | return ioread16be(reg); | |
115 | } | |
116 | ||
117 | static void bgpio_write32be(void __iomem *reg, unsigned long data) | |
118 | { | |
119 | iowrite32be(data, reg); | |
120 | } | |
121 | ||
122 | static unsigned long bgpio_read32be(void __iomem *reg) | |
123 | { | |
124 | return ioread32be(reg); | |
125 | } | |
126 | ||
aeec56e3 AV |
127 | static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin) |
128 | { | |
8467afec JI |
129 | return 1 << pin; |
130 | } | |
131 | ||
132 | static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc, | |
133 | unsigned int pin) | |
134 | { | |
135 | return 1 << (bgc->bits - 1 - pin); | |
aeec56e3 AV |
136 | } |
137 | ||
b19e7f51 VZ |
138 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
139 | { | |
140 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
141 | unsigned long pinmask = bgc->pin2mask(bgc, gpio); | |
142 | ||
143 | if (bgc->dir & pinmask) | |
144 | return bgc->read_reg(bgc->reg_set) & pinmask; | |
145 | else | |
146 | return bgc->read_reg(bgc->reg_dat) & pinmask; | |
147 | } | |
148 | ||
aeec56e3 AV |
149 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
150 | { | |
151 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
152 | ||
25b35da7 | 153 | return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio)); |
aeec56e3 AV |
154 | } |
155 | ||
91492a44 RV |
156 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
157 | { | |
158 | } | |
159 | ||
aeec56e3 AV |
160 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
161 | { | |
162 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
8467afec | 163 | unsigned long mask = bgc->pin2mask(bgc, gpio); |
aeec56e3 AV |
164 | unsigned long flags; |
165 | ||
aeec56e3 AV |
166 | spin_lock_irqsave(&bgc->lock, flags); |
167 | ||
168 | if (val) | |
169 | bgc->data |= mask; | |
170 | else | |
171 | bgc->data &= ~mask; | |
172 | ||
8467afec | 173 | bgc->write_reg(bgc->reg_dat, bgc->data); |
aeec56e3 AV |
174 | |
175 | spin_unlock_irqrestore(&bgc->lock, flags); | |
176 | } | |
177 | ||
e027d6f9 JI |
178 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
179 | int val) | |
180 | { | |
181 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
182 | unsigned long mask = bgc->pin2mask(bgc, gpio); | |
183 | ||
184 | if (val) | |
185 | bgc->write_reg(bgc->reg_set, mask); | |
186 | else | |
187 | bgc->write_reg(bgc->reg_clr, mask); | |
188 | } | |
189 | ||
dd86a0cc JI |
190 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
191 | { | |
192 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
193 | unsigned long mask = bgc->pin2mask(bgc, gpio); | |
194 | unsigned long flags; | |
195 | ||
196 | spin_lock_irqsave(&bgc->lock, flags); | |
197 | ||
198 | if (val) | |
199 | bgc->data |= mask; | |
200 | else | |
201 | bgc->data &= ~mask; | |
202 | ||
203 | bgc->write_reg(bgc->reg_set, bgc->data); | |
204 | ||
205 | spin_unlock_irqrestore(&bgc->lock, flags); | |
206 | } | |
207 | ||
73c4ceda RI |
208 | static void bgpio_multiple_get_masks(struct bgpio_chip *bgc, |
209 | unsigned long *mask, unsigned long *bits, | |
210 | unsigned long *set_mask, | |
211 | unsigned long *clear_mask) | |
212 | { | |
213 | int i; | |
214 | ||
215 | *set_mask = 0; | |
216 | *clear_mask = 0; | |
217 | ||
218 | for (i = 0; i < bgc->bits; i++) { | |
219 | if (*mask == 0) | |
220 | break; | |
221 | if (__test_and_clear_bit(i, mask)) { | |
222 | if (test_bit(i, bits)) | |
223 | *set_mask |= bgc->pin2mask(bgc, i); | |
224 | else | |
225 | *clear_mask |= bgc->pin2mask(bgc, i); | |
226 | } | |
227 | } | |
228 | } | |
229 | ||
230 | static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc, | |
231 | unsigned long *mask, | |
232 | unsigned long *bits, | |
233 | void __iomem *reg) | |
234 | { | |
235 | unsigned long flags; | |
236 | unsigned long set_mask, clear_mask; | |
237 | ||
238 | spin_lock_irqsave(&bgc->lock, flags); | |
239 | ||
240 | bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask); | |
241 | ||
242 | bgc->data |= set_mask; | |
243 | bgc->data &= ~clear_mask; | |
244 | ||
245 | bgc->write_reg(reg, bgc->data); | |
246 | ||
247 | spin_unlock_irqrestore(&bgc->lock, flags); | |
248 | } | |
249 | ||
250 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
251 | unsigned long *bits) | |
252 | { | |
253 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
254 | ||
255 | bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat); | |
256 | } | |
257 | ||
258 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, | |
259 | unsigned long *bits) | |
260 | { | |
261 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
262 | ||
263 | bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set); | |
264 | } | |
265 | ||
266 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, | |
267 | unsigned long *mask, | |
268 | unsigned long *bits) | |
269 | { | |
270 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
271 | unsigned long set_mask, clear_mask; | |
272 | ||
273 | bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask); | |
274 | ||
275 | if (set_mask) | |
276 | bgc->write_reg(bgc->reg_set, set_mask); | |
277 | if (clear_mask) | |
278 | bgc->write_reg(bgc->reg_clr, clear_mask); | |
279 | } | |
280 | ||
31029116 JI |
281 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
282 | { | |
283 | return 0; | |
284 | } | |
285 | ||
91492a44 RV |
286 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
287 | int val) | |
288 | { | |
289 | return -EINVAL; | |
290 | } | |
291 | ||
31029116 JI |
292 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
293 | int val) | |
294 | { | |
295 | gc->set(gc, gpio, val); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
aeec56e3 AV |
300 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
301 | { | |
31029116 JI |
302 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
303 | unsigned long flags; | |
304 | ||
305 | spin_lock_irqsave(&bgc->lock, flags); | |
306 | ||
307 | bgc->dir &= ~bgc->pin2mask(bgc, gpio); | |
308 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
309 | ||
310 | spin_unlock_irqrestore(&bgc->lock, flags); | |
311 | ||
aeec56e3 AV |
312 | return 0; |
313 | } | |
314 | ||
db3b0fcc PZ |
315 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
316 | { | |
317 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
318 | ||
319 | return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ? | |
320 | GPIOF_DIR_OUT : GPIOF_DIR_IN; | |
321 | } | |
322 | ||
aeec56e3 AV |
323 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
324 | { | |
31029116 JI |
325 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
326 | unsigned long flags; | |
327 | ||
328 | gc->set(gc, gpio, val); | |
329 | ||
330 | spin_lock_irqsave(&bgc->lock, flags); | |
331 | ||
332 | bgc->dir |= bgc->pin2mask(bgc, gpio); | |
333 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
334 | ||
335 | spin_unlock_irqrestore(&bgc->lock, flags); | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) | |
341 | { | |
342 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
343 | unsigned long flags; | |
344 | ||
345 | spin_lock_irqsave(&bgc->lock, flags); | |
346 | ||
347 | bgc->dir |= bgc->pin2mask(bgc, gpio); | |
348 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
349 | ||
350 | spin_unlock_irqrestore(&bgc->lock, flags); | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) | |
356 | { | |
357 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
358 | unsigned long flags; | |
359 | ||
e027d6f9 JI |
360 | gc->set(gc, gpio, val); |
361 | ||
31029116 JI |
362 | spin_lock_irqsave(&bgc->lock, flags); |
363 | ||
364 | bgc->dir &= ~bgc->pin2mask(bgc, gpio); | |
365 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
366 | ||
367 | spin_unlock_irqrestore(&bgc->lock, flags); | |
368 | ||
aeec56e3 AV |
369 | return 0; |
370 | } | |
371 | ||
db3b0fcc PZ |
372 | static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio) |
373 | { | |
374 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
375 | ||
376 | return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ? | |
377 | GPIOF_DIR_IN : GPIOF_DIR_OUT; | |
378 | } | |
379 | ||
280df6b3 JI |
380 | static int bgpio_setup_accessors(struct device *dev, |
381 | struct bgpio_chip *bgc, | |
2b78f1e1 AL |
382 | bool bit_be, |
383 | bool byte_be) | |
aeec56e3 | 384 | { |
8467afec JI |
385 | |
386 | switch (bgc->bits) { | |
387 | case 8: | |
388 | bgc->read_reg = bgpio_read8; | |
389 | bgc->write_reg = bgpio_write8; | |
390 | break; | |
391 | case 16: | |
2b78f1e1 AL |
392 | if (byte_be) { |
393 | bgc->read_reg = bgpio_read16be; | |
394 | bgc->write_reg = bgpio_write16be; | |
395 | } else { | |
396 | bgc->read_reg = bgpio_read16; | |
397 | bgc->write_reg = bgpio_write16; | |
398 | } | |
8467afec JI |
399 | break; |
400 | case 32: | |
2b78f1e1 AL |
401 | if (byte_be) { |
402 | bgc->read_reg = bgpio_read32be; | |
403 | bgc->write_reg = bgpio_write32be; | |
404 | } else { | |
405 | bgc->read_reg = bgpio_read32; | |
406 | bgc->write_reg = bgpio_write32; | |
407 | } | |
8467afec JI |
408 | break; |
409 | #if BITS_PER_LONG >= 64 | |
410 | case 64: | |
2b78f1e1 AL |
411 | if (byte_be) { |
412 | dev_err(dev, | |
413 | "64 bit big endian byte order unsupported\n"); | |
414 | return -EINVAL; | |
415 | } else { | |
416 | bgc->read_reg = bgpio_read64; | |
417 | bgc->write_reg = bgpio_write64; | |
418 | } | |
8467afec JI |
419 | break; |
420 | #endif /* BITS_PER_LONG >= 64 */ | |
421 | default: | |
280df6b3 | 422 | dev_err(dev, "unsupported data width %u bits\n", bgc->bits); |
8467afec JI |
423 | return -EINVAL; |
424 | } | |
425 | ||
2b78f1e1 | 426 | bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask; |
8467afec JI |
427 | |
428 | return 0; | |
429 | } | |
430 | ||
e027d6f9 JI |
431 | /* |
432 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 433 | * three supported configurations: |
e027d6f9 | 434 | * |
dd86a0cc | 435 | * - single input/output register resource (named "dat"). |
e027d6f9 | 436 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
437 | * - single output register resource and single input resource ("set" and |
438 | * dat"). | |
e027d6f9 JI |
439 | * |
440 | * For the single output register, this drives a 1 by setting a bit and a zero | |
441 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
442 | * in the set register and clears it by setting a bit in the clear register. | |
443 | * The configuration is detected by which resources are present. | |
31029116 JI |
444 | * |
445 | * For setting the GPIO direction, there are three supported configurations: | |
446 | * | |
447 | * - simple bidirection GPIO that requires no configuration. | |
448 | * - an output direction register (named "dirout") where a 1 bit | |
449 | * indicates the GPIO is an output. | |
450 | * - an input direction register (named "dirin") where a 1 bit indicates | |
451 | * the GPIO is an input. | |
e027d6f9 | 452 | */ |
280df6b3 JI |
453 | static int bgpio_setup_io(struct bgpio_chip *bgc, |
454 | void __iomem *dat, | |
455 | void __iomem *set, | |
b19e7f51 VZ |
456 | void __iomem *clr, |
457 | unsigned long flags) | |
8467afec | 458 | { |
aeec56e3 | 459 | |
280df6b3 | 460 | bgc->reg_dat = dat; |
aeec56e3 | 461 | if (!bgc->reg_dat) |
280df6b3 | 462 | return -EINVAL; |
e027d6f9 | 463 | |
280df6b3 JI |
464 | if (set && clr) { |
465 | bgc->reg_set = set; | |
466 | bgc->reg_clr = clr; | |
e027d6f9 | 467 | bgc->gc.set = bgpio_set_with_clear; |
73c4ceda | 468 | bgc->gc.set_multiple = bgpio_set_multiple_with_clear; |
280df6b3 JI |
469 | } else if (set && !clr) { |
470 | bgc->reg_set = set; | |
dd86a0cc | 471 | bgc->gc.set = bgpio_set_set; |
73c4ceda | 472 | bgc->gc.set_multiple = bgpio_set_multiple_set; |
91492a44 RV |
473 | } else if (flags & BGPIOF_NO_OUTPUT) { |
474 | bgc->gc.set = bgpio_set_none; | |
475 | bgc->gc.set_multiple = NULL; | |
e027d6f9 JI |
476 | } else { |
477 | bgc->gc.set = bgpio_set; | |
73c4ceda | 478 | bgc->gc.set_multiple = bgpio_set_multiple; |
aeec56e3 AV |
479 | } |
480 | ||
b19e7f51 VZ |
481 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
482 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) | |
483 | bgc->gc.get = bgpio_get_set; | |
484 | else | |
485 | bgc->gc.get = bgpio_get; | |
dd86a0cc | 486 | |
e027d6f9 JI |
487 | return 0; |
488 | } | |
489 | ||
280df6b3 JI |
490 | static int bgpio_setup_direction(struct bgpio_chip *bgc, |
491 | void __iomem *dirout, | |
91492a44 RV |
492 | void __iomem *dirin, |
493 | unsigned long flags) | |
31029116 | 494 | { |
280df6b3 | 495 | if (dirout && dirin) { |
31029116 | 496 | return -EINVAL; |
280df6b3 JI |
497 | } else if (dirout) { |
498 | bgc->reg_dir = dirout; | |
31029116 JI |
499 | bgc->gc.direction_output = bgpio_dir_out; |
500 | bgc->gc.direction_input = bgpio_dir_in; | |
db3b0fcc | 501 | bgc->gc.get_direction = bgpio_get_dir; |
280df6b3 JI |
502 | } else if (dirin) { |
503 | bgc->reg_dir = dirin; | |
31029116 JI |
504 | bgc->gc.direction_output = bgpio_dir_out_inv; |
505 | bgc->gc.direction_input = bgpio_dir_in_inv; | |
db3b0fcc | 506 | bgc->gc.get_direction = bgpio_get_dir_inv; |
31029116 | 507 | } else { |
91492a44 RV |
508 | if (flags & BGPIOF_NO_OUTPUT) |
509 | bgc->gc.direction_output = bgpio_dir_out_err; | |
510 | else | |
511 | bgc->gc.direction_output = bgpio_simple_dir_out; | |
31029116 JI |
512 | bgc->gc.direction_input = bgpio_simple_dir_in; |
513 | } | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
7b42e3db AF |
518 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
519 | { | |
520 | if (gpio_pin < chip->ngpio) | |
521 | return 0; | |
522 | ||
523 | return -EINVAL; | |
524 | } | |
525 | ||
4f5b0480 | 526 | int bgpio_remove(struct bgpio_chip *bgc) |
280df6b3 | 527 | { |
9f5132ae | 528 | gpiochip_remove(&bgc->gc); |
529 | return 0; | |
280df6b3 JI |
530 | } |
531 | EXPORT_SYMBOL_GPL(bgpio_remove); | |
532 | ||
4f5b0480 RK |
533 | int bgpio_init(struct bgpio_chip *bgc, struct device *dev, |
534 | unsigned long sz, void __iomem *dat, void __iomem *set, | |
535 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 536 | unsigned long flags) |
e027d6f9 | 537 | { |
e027d6f9 | 538 | int ret; |
e027d6f9 | 539 | |
280df6b3 JI |
540 | if (!is_power_of_2(sz)) |
541 | return -EINVAL; | |
e027d6f9 | 542 | |
280df6b3 JI |
543 | bgc->bits = sz * 8; |
544 | if (bgc->bits > BITS_PER_LONG) | |
545 | return -EINVAL; | |
546 | ||
547 | spin_lock_init(&bgc->lock); | |
548 | bgc->gc.dev = dev; | |
549 | bgc->gc.label = dev_name(dev); | |
550 | bgc->gc.base = -1; | |
551 | bgc->gc.ngpio = bgc->bits; | |
7b42e3db | 552 | bgc->gc.request = bgpio_request; |
280df6b3 | 553 | |
b19e7f51 | 554 | ret = bgpio_setup_io(bgc, dat, set, clr, flags); |
e027d6f9 JI |
555 | if (ret) |
556 | return ret; | |
aeec56e3 | 557 | |
2b78f1e1 AL |
558 | ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN, |
559 | flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); | |
8467afec JI |
560 | if (ret) |
561 | return ret; | |
aeec56e3 | 562 | |
91492a44 | 563 | ret = bgpio_setup_direction(bgc, dirout, dirin, flags); |
31029116 JI |
564 | if (ret) |
565 | return ret; | |
566 | ||
8467afec | 567 | bgc->data = bgc->read_reg(bgc->reg_dat); |
3e11f7b8 SG |
568 | if (bgc->gc.set == bgpio_set_set && |
569 | !(flags & BGPIOF_UNREADABLE_REG_SET)) | |
570 | bgc->data = bgc->read_reg(bgc->reg_set); | |
571 | if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) | |
572 | bgc->dir = bgc->read_reg(bgc->reg_dir); | |
924e7a9f | 573 | |
280df6b3 JI |
574 | return ret; |
575 | } | |
576 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 577 | |
c103de24 | 578 | #ifdef CONFIG_GPIO_GENERIC_PLATFORM |
aeec56e3 | 579 | |
280df6b3 JI |
580 | static void __iomem *bgpio_map(struct platform_device *pdev, |
581 | const char *name, | |
582 | resource_size_t sane_sz, | |
583 | int *err) | |
584 | { | |
585 | struct device *dev = &pdev->dev; | |
586 | struct resource *r; | |
587 | resource_size_t start; | |
588 | resource_size_t sz; | |
589 | void __iomem *ret; | |
590 | ||
591 | *err = 0; | |
592 | ||
593 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
594 | if (!r) | |
595 | return NULL; | |
596 | ||
597 | sz = resource_size(r); | |
598 | if (sz != sane_sz) { | |
599 | *err = -EINVAL; | |
600 | return NULL; | |
601 | } | |
602 | ||
603 | start = r->start; | |
604 | if (!devm_request_mem_region(dev, start, sz, r->name)) { | |
605 | *err = -EBUSY; | |
606 | return NULL; | |
607 | } | |
608 | ||
609 | ret = devm_ioremap(dev, start, sz); | |
610 | if (!ret) { | |
611 | *err = -ENOMEM; | |
612 | return NULL; | |
613 | } | |
aeec56e3 AV |
614 | |
615 | return ret; | |
616 | } | |
617 | ||
3836309d | 618 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
619 | { |
620 | struct device *dev = &pdev->dev; | |
621 | struct resource *r; | |
622 | void __iomem *dat; | |
623 | void __iomem *set; | |
624 | void __iomem *clr; | |
625 | void __iomem *dirout; | |
626 | void __iomem *dirin; | |
627 | unsigned long sz; | |
19338530 | 628 | unsigned long flags = pdev->id_entry->driver_data; |
280df6b3 JI |
629 | int err; |
630 | struct bgpio_chip *bgc; | |
631 | struct bgpio_pdata *pdata = dev_get_platdata(dev); | |
632 | ||
633 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
634 | if (!r) | |
635 | return -EINVAL; | |
636 | ||
637 | sz = resource_size(r); | |
638 | ||
639 | dat = bgpio_map(pdev, "dat", sz, &err); | |
640 | if (!dat) | |
641 | return err ? err : -EINVAL; | |
642 | ||
643 | set = bgpio_map(pdev, "set", sz, &err); | |
644 | if (err) | |
645 | return err; | |
646 | ||
647 | clr = bgpio_map(pdev, "clr", sz, &err); | |
648 | if (err) | |
649 | return err; | |
650 | ||
651 | dirout = bgpio_map(pdev, "dirout", sz, &err); | |
652 | if (err) | |
653 | return err; | |
654 | ||
655 | dirin = bgpio_map(pdev, "dirin", sz, &err); | |
656 | if (err) | |
657 | return err; | |
658 | ||
280df6b3 JI |
659 | bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); |
660 | if (!bgc) | |
661 | return -ENOMEM; | |
662 | ||
3e11f7b8 | 663 | err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
664 | if (err) |
665 | return err; | |
666 | ||
667 | if (pdata) { | |
781f6d71 PM |
668 | if (pdata->label) |
669 | bgc->gc.label = pdata->label; | |
280df6b3 JI |
670 | bgc->gc.base = pdata->base; |
671 | if (pdata->ngpio > 0) | |
672 | bgc->gc.ngpio = pdata->ngpio; | |
673 | } | |
674 | ||
675 | platform_set_drvdata(pdev, bgc); | |
676 | ||
677 | return gpiochip_add(&bgc->gc); | |
678 | } | |
679 | ||
206210ce | 680 | static int bgpio_pdev_remove(struct platform_device *pdev) |
aeec56e3 | 681 | { |
4ddb8ae2 | 682 | struct bgpio_chip *bgc = platform_get_drvdata(pdev); |
aeec56e3 | 683 | |
280df6b3 | 684 | return bgpio_remove(bgc); |
aeec56e3 AV |
685 | } |
686 | ||
687 | static const struct platform_device_id bgpio_id_table[] = { | |
19338530 AS |
688 | { |
689 | .name = "basic-mmio-gpio", | |
690 | .driver_data = 0, | |
691 | }, { | |
692 | .name = "basic-mmio-gpio-be", | |
693 | .driver_data = BGPIOF_BIG_ENDIAN, | |
694 | }, | |
695 | { } | |
aeec56e3 AV |
696 | }; |
697 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
698 | ||
699 | static struct platform_driver bgpio_driver = { | |
700 | .driver = { | |
701 | .name = "basic-mmio-gpio", | |
702 | }, | |
703 | .id_table = bgpio_id_table, | |
280df6b3 | 704 | .probe = bgpio_pdev_probe, |
8283c4ff | 705 | .remove = bgpio_pdev_remove, |
aeec56e3 AV |
706 | }; |
707 | ||
6f61415e | 708 | module_platform_driver(bgpio_driver); |
280df6b3 | 709 | |
c103de24 | 710 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
711 | |
712 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
713 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
714 | MODULE_LICENSE("GPL"); |